diff --new-file -upr binutils-2.9.1.0.22b/bfd/ChangeLog.linux binutils-2.9.1.0.23/bfd/ChangeLog.linux --- binutils-2.9.1.0.22b/bfd/ChangeLog.linux Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/bfd/ChangeLog.linux Wed Mar 31 09:34:16 1999 @@ -1,3 +1,16 @@ +Sat Mar 20 21:16:53 1999 Christopher C Chimelis + + * config.bfd (arm-*-elf*, arm-*-linux*): Add + targ_selvecs=armlinux_vec. + +Fri Sep 4 13:54:23 1998 David Miller + + * elf32-sparc.c (elf32_sparc_relocate_section): Properly adjust + the addend of a dynamic relocation referencing a section. + * elf64-sparc.c (sparc64_elf_relocate_section): Likewise. + (sparc64_elf_finish_dynamic_symbol): Fix the PLT relocation + offset. + Wed Feb 24 08:12:14 1999 H.J. Lu (hjl@gnu.org) * acinclude.m4: Updated from the gas snasphot 1999-02-23. diff --new-file -upr binutils-2.9.1.0.22b/bfd/config.bfd binutils-2.9.1.0.23/bfd/config.bfd --- binutils-2.9.1.0.22b/bfd/config.bfd Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/bfd/config.bfd Wed Mar 31 09:34:16 1999 @@ -115,6 +115,7 @@ case "${targ}" in ;; arm-*-elf* | arm-*-linux*) targ_defvec=bfd_elf32_arm_vec + targ_selvecs=armlinux_vec ;; thumb-*-coff) targ_defvec=armcoff_little_vec diff --new-file -upr binutils-2.9.1.0.22b/bfd/configure binutils-2.9.1.0.23/bfd/configure --- binutils-2.9.1.0.22b/bfd/configure Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/bfd/configure Wed Mar 31 09:34:16 1999 @@ -1042,7 +1042,7 @@ fi PACKAGE=bfd -VERSION=2.9.1.0.22 +VERSION=2.9.1.0.23 if test "`cd $srcdir && pwd`" != "`pwd`" && test -f $srcdir/config.status; then { echo "configure: error: source directory already configured; run "make distclean" there first" 1>&2; exit 1; } diff --new-file -upr binutils-2.9.1.0.22b/bfd/configure.in binutils-2.9.1.0.23/bfd/configure.in --- binutils-2.9.1.0.22b/bfd/configure.in Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/bfd/configure.in Wed Mar 31 09:34:16 1999 @@ -7,7 +7,7 @@ AC_INIT(libbfd.c) AC_CANONICAL_SYSTEM AC_ISC_POSIX -AM_INIT_AUTOMAKE(bfd, 2.9.1.0.22) +AM_INIT_AUTOMAKE(bfd, 2.9.1.0.23) dnl These must be called before AM_PROG_LIBTOOL, because it may want dnl to call AC_CHECK_PROG. diff --new-file -upr binutils-2.9.1.0.22b/bfd/doc/bfd.info binutils-2.9.1.0.23/bfd/doc/bfd.info --- binutils-2.9.1.0.22b/bfd/doc/bfd.info Fri Feb 5 13:58:17 1999 +++ binutils-2.9.1.0.23/bfd/doc/bfd.info Wed Mar 31 09:50:37 1999 @@ -28,9 +28,9 @@ Indirect: bfd.info-1: 942 bfd.info-2: 37582 bfd.info-3: 78554 -bfd.info-4: 113746 -bfd.info-5: 162632 -bfd.info-6: 188697 +bfd.info-4: 113808 +bfd.info-5: 162751 +bfd.info-6: 188816  Tag Table: (Indirect) @@ -60,36 +60,36 @@ Node: Formats75034 Node: Relocations77835 Node: typedef arelent78554 Node: howto manager93396 -Node: Core Files110764 -Node: Targets111785 -Node: bfd_target113746 -Node: Architectures131500 -Node: Opening and Closing142925 -Node: Internal146520 -Node: File Caching151702 -Node: Linker Functions154480 -Node: Creating a Linker Hash Table156146 -Node: Adding Symbols to the Hash Table157873 -Node: Differing file formats158763 -Node: Adding symbols from an object file160496 -Node: Adding symbols from an archive162632 -Node: Performing the Final Link165031 -Node: Information provided by the linker166262 -Node: Relocating the section contents167398 -Node: Writing the symbol table169135 -Node: Hash Tables171729 -Node: Creating and Freeing a Hash Table172920 -Node: Looking Up or Entering a String174076 -Node: Traversing a Hash Table175318 -Node: Deriving a New Hash Table Type176096 -Node: Define the Derived Structures177151 -Node: Write the Derived Creation Routine178217 -Node: Write Other Derived Routines180916 -Node: BFD back ends182216 -Node: What to Put Where182435 -Node: aout182573 -Node: coff188697 -Node: elf214728 -Node: Index215561 +Node: Core Files110826 +Node: Targets111847 +Node: bfd_target113808 +Node: Architectures131562 +Node: Opening and Closing143044 +Node: Internal146639 +Node: File Caching151821 +Node: Linker Functions154599 +Node: Creating a Linker Hash Table156265 +Node: Adding Symbols to the Hash Table157992 +Node: Differing file formats158882 +Node: Adding symbols from an object file160615 +Node: Adding symbols from an archive162751 +Node: Performing the Final Link165150 +Node: Information provided by the linker166381 +Node: Relocating the section contents167517 +Node: Writing the symbol table169254 +Node: Hash Tables171848 +Node: Creating and Freeing a Hash Table173039 +Node: Looking Up or Entering a String174195 +Node: Traversing a Hash Table175437 +Node: Deriving a New Hash Table Type176215 +Node: Define the Derived Structures177270 +Node: Write the Derived Creation Routine178336 +Node: Write Other Derived Routines181035 +Node: BFD back ends182335 +Node: What to Put Where182554 +Node: aout182692 +Node: coff188816 +Node: elf214847 +Node: Index215680  End Tag Table diff --new-file -upr binutils-2.9.1.0.22b/bfd/doc/bfd.info-3 binutils-2.9.1.0.23/bfd/doc/bfd.info-3 --- binutils-2.9.1.0.22b/bfd/doc/bfd.info-3 Fri Feb 5 13:58:17 1999 +++ binutils-2.9.1.0.23/bfd/doc/bfd.info-3 Wed Mar 31 09:50:37 1999 @@ -726,6 +726,9 @@ attributes. - : BFD_RELOC_PPC_EMB_RELSDA Power(rs6000) and PowerPC relocations. + - : BFD_RELOC_I370_D12 + Instruction 370/390 relocations + - : BFD_RELOC_CTOR The type of reloc used to build a contructor table - at the moment probably a 32 bit wide absolute relocation, but the target can diff --new-file -upr binutils-2.9.1.0.22b/bfd/doc/bfd.info-4 binutils-2.9.1.0.23/bfd/doc/bfd.info-4 --- binutils-2.9.1.0.22b/bfd/doc/bfd.info-4 Fri Feb 5 13:58:17 1999 +++ binutils-2.9.1.0.23/bfd/doc/bfd.info-4 Wed Mar 31 09:50:37 1999 @@ -502,6 +502,7 @@ i960 KB, and 68020 and 68030 for Motorol bfd_arch_we32k, /* AT&T WE32xxx */ bfd_arch_tahoe, /* CCI/Harris Tahoe */ bfd_arch_i860, /* Intel 860 */ + bfd_arch_i370, /* IBM 360/370 Mainframes */ bfd_arch_romp, /* IBM ROMP PC/RT */ bfd_arch_alliant, /* Alliant */ bfd_arch_convex, /* Convex */ diff --new-file -upr binutils-2.9.1.0.22b/bfd/doc/bfd.info-6 binutils-2.9.1.0.23/bfd/doc/bfd.info-6 --- binutils-2.9.1.0.22b/bfd/doc/bfd.info-6 Fri Feb 5 13:58:17 1999 +++ binutils-2.9.1.0.23/bfd/doc/bfd.info-6 Wed Mar 31 09:50:37 1999 @@ -867,6 +867,7 @@ Index * BFD_RELOC_HI16_S_GOTOFF: howto manager. * BFD_RELOC_HI16_S_PLTOFF: howto manager. * BFD_RELOC_HI22: howto manager. +* BFD_RELOC_I370_D12: howto manager. * BFD_RELOC_I960_CALLJ: howto manager. * BFD_RELOC_LO10: howto manager. * BFD_RELOC_LO16: howto manager. diff --new-file -upr binutils-2.9.1.0.22b/bfd/elf32-sparc.c binutils-2.9.1.0.23/bfd/elf32-sparc.c --- binutils-2.9.1.0.22b/bfd/elf32-sparc.c Mon Aug 10 06:46:27 1998 +++ binutils-2.9.1.0.23/bfd/elf32-sparc.c Wed Mar 31 09:34:16 1999 @@ -1357,7 +1357,15 @@ elf32_sparc_relocate_section (output_bfd } outrel.r_info = ELF32_R_INFO (indx, r_type); - outrel.r_addend = relocation + rel->r_addend; + + /* For non-RELATIVE dynamic relocations, we keep the + same symbol, and so generally the same addend. But + we do need to adjust those relocations referencing + sections. */ + outrel.r_addend = rel->r_addend; + if (r_symndx < symtab_hdr->sh_info + && ELF_ST_TYPE (sym->st_info) == STT_SECTION) + outrel.r_addend += sec->output_offset + sym->st_value; } } diff --new-file -upr binutils-2.9.1.0.22b/bfd/elf64-sparc.c binutils-2.9.1.0.23/bfd/elf64-sparc.c --- binutils-2.9.1.0.22b/bfd/elf64-sparc.c Fri Dec 4 19:38:53 1998 +++ binutils-2.9.1.0.23/bfd/elf64-sparc.c Wed Mar 31 09:34:16 1999 @@ -1590,7 +1590,15 @@ sparc64_elf_relocate_section (output_bfd } outrel.r_info = ELF64_R_INFO (indx, r_type); - outrel.r_addend = relocation + rel->r_addend; + + /* For non-RELATIVE dynamic relocations, we keep the + same symbol, and so generally the same addend. But + we do need to adjust those relocations referencing + sections. */ + outrel.r_addend = rel->r_addend; + if (r_symndx < symtab_hdr->sh_info + && ELF_ST_TYPE (sym->st_info) == STT_SECTION) + outrel.r_addend += sec->output_offset + sym->st_value; } } @@ -1904,6 +1912,7 @@ sparc64_elf_finish_dynamic_symbol (outpu rela.r_offset = sparc64_elf_plt_ptr_offset (h->plt_offset, max); rela.r_addend = -(sparc64_elf_plt_entry_offset (h->plt_offset) + 4); } + rela.r_offset += (splt->output_section->vma + splt->output_offset); rela.r_info = ELF64_R_INFO (h->dynindx, R_SPARC_JMP_SLOT); bfd_elf64_swap_reloca_out (output_bfd, &rela, diff --new-file -upr binutils-2.9.1.0.22b/binutils/ChangeLog.linux binutils-2.9.1.0.23/binutils/ChangeLog.linux --- binutils-2.9.1.0.22b/binutils/ChangeLog.linux Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/binutils/ChangeLog.linux Wed Mar 31 09:34:16 1999 @@ -1,3 +1,25 @@ +Tue Mar 30 08:34:28 1999 H.J. Lu (hjl@gnu.org) + + * objdump.c (disassemble_bytes): Make `buf' empty first and + print any error message for error return. + +Sun Mar 28 15:32:42 1999 H.J. Lu (hjl@gnu.org) + + * Makefile.in: Regenerated with automake 1.4. + +Thu Feb 25 15:32:08 1999 "H. Peter Anvin" + + * objcopy.c (section_list): Add "extract". + (sections_extracted): New variable. + (copy_options): Add 'j'. + (copy_usage): Add '-j section'. + (find_section_list): Handle "extract" and "sections_extracted". + (is_strip_section): Likewise. + (copy_object): Liekwise. + (setup_section): Likewise. + (copy_section): Likewise. + (copy_main): Likewise. + Wed Feb 24 08:12:14 1999 H.J. Lu (hjl@gnu.org) * aclocal.m4: Updated from the gas snasphot 1999-02-23. diff --new-file -upr binutils-2.9.1.0.22b/binutils/Makefile.in binutils-2.9.1.0.23/binutils/Makefile.in --- binutils-2.9.1.0.22b/binutils/Makefile.in Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/binutils/Makefile.in Wed Mar 31 09:34:16 1999 @@ -75,6 +75,7 @@ CC = @CC@ DATADIRNAME = @DATADIRNAME@ DLLTOOL = @DLLTOOL@ DLLTOOL_DEFS = @DLLTOOL_DEFS@ +EXEEXT = @EXEEXT@ GMOFILES = @GMOFILES@ GMSGFMT = @GMSGFMT@ GT_NO = @GT_NO@ @@ -252,6 +253,11 @@ ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs CONFIG_HEADER = config.h CONFIG_CLEAN_FILES = +bin_PROGRAMS = size$(EXEEXT) objdump$(EXEEXT) ar$(EXEEXT) \ +strings$(EXEEXT) ranlib$(EXEEXT) c++filt$(EXEEXT) objcopy$(EXEEXT) \ +@BUILD_NLMCONV@ @BUILD_SRCONV@ @BUILD_DLLTOOL@ @BUILD_WINDRES@ \ +addr2line$(EXEEXT) +noinst_PROGRAMS = nm-new$(EXEEXT) strip-new$(EXEEXT) PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS) @@ -474,68 +480,68 @@ distclean-libtool: maintainer-clean-libtool: -nlmconv: $(nlmconv_OBJECTS) $(nlmconv_DEPENDENCIES) - @rm -f nlmconv +nlmconv$(EXEEXT): $(nlmconv_OBJECTS) $(nlmconv_DEPENDENCIES) + @rm -f nlmconv$(EXEEXT) $(LINK) $(nlmconv_LDFLAGS) $(nlmconv_OBJECTS) $(nlmconv_LDADD) $(LIBS) -srconv: $(srconv_OBJECTS) $(srconv_DEPENDENCIES) - @rm -f srconv +srconv$(EXEEXT): $(srconv_OBJECTS) $(srconv_DEPENDENCIES) + @rm -f srconv$(EXEEXT) $(LINK) $(srconv_LDFLAGS) $(srconv_OBJECTS) $(srconv_LDADD) $(LIBS) -sysdump: $(sysdump_OBJECTS) $(sysdump_DEPENDENCIES) - @rm -f sysdump +sysdump$(EXEEXT): $(sysdump_OBJECTS) $(sysdump_DEPENDENCIES) + @rm -f sysdump$(EXEEXT) $(LINK) $(sysdump_LDFLAGS) $(sysdump_OBJECTS) $(sysdump_LDADD) $(LIBS) -coffdump: $(coffdump_OBJECTS) $(coffdump_DEPENDENCIES) - @rm -f coffdump +coffdump$(EXEEXT): $(coffdump_OBJECTS) $(coffdump_DEPENDENCIES) + @rm -f coffdump$(EXEEXT) $(LINK) $(coffdump_LDFLAGS) $(coffdump_OBJECTS) $(coffdump_LDADD) $(LIBS) -dlltool: $(dlltool_OBJECTS) $(dlltool_DEPENDENCIES) - @rm -f dlltool +dlltool$(EXEEXT): $(dlltool_OBJECTS) $(dlltool_DEPENDENCIES) + @rm -f dlltool$(EXEEXT) $(LINK) $(dlltool_LDFLAGS) $(dlltool_OBJECTS) $(dlltool_LDADD) $(LIBS) -windres: $(windres_OBJECTS) $(windres_DEPENDENCIES) - @rm -f windres +windres$(EXEEXT): $(windres_OBJECTS) $(windres_DEPENDENCIES) + @rm -f windres$(EXEEXT) $(LINK) $(windres_LDFLAGS) $(windres_OBJECTS) $(windres_LDADD) $(LIBS) -size: $(size_OBJECTS) $(size_DEPENDENCIES) - @rm -f size +size$(EXEEXT): $(size_OBJECTS) $(size_DEPENDENCIES) + @rm -f size$(EXEEXT) $(LINK) $(size_LDFLAGS) $(size_OBJECTS) $(size_LDADD) $(LIBS) -objdump: $(objdump_OBJECTS) $(objdump_DEPENDENCIES) - @rm -f objdump +objdump$(EXEEXT): $(objdump_OBJECTS) $(objdump_DEPENDENCIES) + @rm -f objdump$(EXEEXT) $(LINK) $(objdump_LDFLAGS) $(objdump_OBJECTS) $(objdump_LDADD) $(LIBS) -ar: $(ar_OBJECTS) $(ar_DEPENDENCIES) - @rm -f ar +ar$(EXEEXT): $(ar_OBJECTS) $(ar_DEPENDENCIES) + @rm -f ar$(EXEEXT) $(LINK) $(ar_LDFLAGS) $(ar_OBJECTS) $(ar_LDADD) $(LIBS) -strings: $(strings_OBJECTS) $(strings_DEPENDENCIES) - @rm -f strings +strings$(EXEEXT): $(strings_OBJECTS) $(strings_DEPENDENCIES) + @rm -f strings$(EXEEXT) $(LINK) $(strings_LDFLAGS) $(strings_OBJECTS) $(strings_LDADD) $(LIBS) -ranlib: $(ranlib_OBJECTS) $(ranlib_DEPENDENCIES) - @rm -f ranlib +ranlib$(EXEEXT): $(ranlib_OBJECTS) $(ranlib_DEPENDENCIES) + @rm -f ranlib$(EXEEXT) $(LINK) $(ranlib_LDFLAGS) $(ranlib_OBJECTS) $(ranlib_LDADD) $(LIBS) -c++filt: $(c__filt_OBJECTS) $(c__filt_DEPENDENCIES) - @rm -f c++filt +c++filt$(EXEEXT): $(c__filt_OBJECTS) $(c__filt_DEPENDENCIES) + @rm -f c++filt$(EXEEXT) $(LINK) $(c__filt_LDFLAGS) $(c__filt_OBJECTS) $(c__filt_LDADD) $(LIBS) -objcopy: $(objcopy_OBJECTS) $(objcopy_DEPENDENCIES) - @rm -f objcopy +objcopy$(EXEEXT): $(objcopy_OBJECTS) $(objcopy_DEPENDENCIES) + @rm -f objcopy$(EXEEXT) $(LINK) $(objcopy_LDFLAGS) $(objcopy_OBJECTS) $(objcopy_LDADD) $(LIBS) -addr2line: $(addr2line_OBJECTS) $(addr2line_DEPENDENCIES) - @rm -f addr2line +addr2line$(EXEEXT): $(addr2line_OBJECTS) $(addr2line_DEPENDENCIES) + @rm -f addr2line$(EXEEXT) $(LINK) $(addr2line_LDFLAGS) $(addr2line_OBJECTS) $(addr2line_LDADD) $(LIBS) -nm-new: $(nm_new_OBJECTS) $(nm_new_DEPENDENCIES) - @rm -f nm-new +nm-new$(EXEEXT): $(nm_new_OBJECTS) $(nm_new_DEPENDENCIES) + @rm -f nm-new$(EXEEXT) $(LINK) $(nm_new_LDFLAGS) $(nm_new_OBJECTS) $(nm_new_LDADD) $(LIBS) -strip-new: $(strip_new_OBJECTS) $(strip_new_DEPENDENCIES) - @rm -f strip-new +strip-new$(EXEEXT): $(strip_new_OBJECTS) $(strip_new_DEPENDENCIES) + @rm -f strip-new$(EXEEXT) $(LINK) $(strip_new_LDFLAGS) $(strip_new_OBJECTS) $(strip_new_LDADD) $(LIBS) .l.c: $(SHELL) $(YLWRAP) "$(LEX)" $< $(LEX_OUTPUT_ROOT).c $@ -- $(AM_LFLAGS) $(LFLAGS) diff --new-file -upr binutils-2.9.1.0.22b/binutils/objcopy.c binutils-2.9.1.0.23/binutils/objcopy.c --- binutils-2.9.1.0.22b/binutils/objcopy.c Sat Jan 23 08:52:36 1999 +++ binutils-2.9.1.0.23/binutils/objcopy.c Wed Mar 31 09:34:16 1999 @@ -130,6 +130,9 @@ struct section_list boolean used; /* Whether to remove this section. */ boolean remove; + /* Wheter to extract this section (if --section + is specified, all other sections are removed) */ + boolean extract; /* Whether to adjust or set VMA. */ enum { ignore_vma, adjust_vma, set_vma } adjust; /* Amount to adjust by or set to. */ @@ -141,7 +144,7 @@ struct section_list }; static struct section_list *adjust_sections; -static boolean sections_removed; +static boolean sections_removed, sections_extracted; /* Adjustments to the start address. */ static bfd_vma adjust_start = 0; @@ -261,6 +264,7 @@ static struct option copy_options[] = {"debugging", no_argument, 0, OPTION_DEBUGGING}, {"discard-all", no_argument, 0, 'x'}, {"discard-locals", no_argument, 0, 'X'}, + {"extract-section", required_argument, 0, 'j'}, {"format", required_argument, 0, 'F'}, /* Obsolete */ {"gap-fill", required_argument, 0, OPTION_GAP_FILL}, {"help", no_argument, 0, 'h'}, @@ -317,7 +321,7 @@ Usage: %s [-vVSpgxX] [-I bfdname] [-O bf [--gap-fill=val] [--pad-to=address] [--preserve-dates]\n\ [--set-start=val] [--adjust-start=incr]\n\ [--adjust-vma=incr] [--adjust-section-vma=section{=,+,-}val]\n\ - [--adjust-warnings] [--no-adjust-warnings]\n\ + [--adjust-warnings] [--no-adjust-warnings] [-j section]\n\ [--set-section-flags=section=flags] [--add-section=sectionname=filename]\n\ [--keep-symbol symbol] [-K symbol] [--strip-symbol symbol] [-N symbol]\n\ [--localize-symbol symbol] [-L symbol] [--weaken-symbol symbol]\n\ @@ -426,6 +430,7 @@ find_section_list (name, add) p->name = name; p->used = false; p->remove = false; + p->extract = false; p->adjust = ignore_vma; p->val = 0; p->set_flags = false; @@ -487,10 +492,11 @@ is_strip_section (abfd, sec) || convert_debugging)) return true; - if (! sections_removed) + if (! sections_removed && ! sections_extracted) return false; p = find_section_list (bfd_get_section_name (abfd, sec), false); - return p != NULL && p->remove ? true : false; + return ((p && p->remove && sections_removed) || + (!(p && p->extract) && sections_extracted)); } /* Choose which symbol entries to copy; put the result in OSYMS. @@ -918,6 +924,7 @@ copy_object (ibfd, obfd) || localize_specific_list != NULL || weaken_specific_list != NULL || sections_removed + || sections_extracted || convert_debugging || change_leading_char || remove_leading_char @@ -1227,7 +1234,8 @@ setup_section (ibfd, isection, obfdarg) if (p != NULL) p->used = true; - if (p != NULL && p->remove) + if ((p && p->remove && sections_removed) || + (!(p && p->extract) && sections_extracted)) return; osection = bfd_make_section_anyway (obfd, bfd_section_name (ibfd, isection)); @@ -1339,7 +1347,8 @@ copy_section (ibfd, isection, obfdarg) p = find_section_list (bfd_section_name (ibfd, isection), false); - if (p != NULL && p->remove) + if ((p && p->remove && sections_removed) || + (!(p && p->extract) && sections_extracted)) return; osection = isection->output_section; @@ -1921,7 +1930,7 @@ copy_main (argc, argv) struct section_list *p; struct stat statbuf; - while ((c = getopt_long (argc, argv, "b:i:I:K:N:s:O:d:F:L:R:SpgxXVvW:", + while ((c = getopt_long (argc, argv, "b:i:I:j:K:N:s:O:d:F:L:R:SpgxXVvW:", copy_options, (int *) 0)) != EOF) { switch (c) @@ -1954,6 +1963,11 @@ copy_main (argc, argv) break; case 'F': input_target = output_target = optarg; + break; + case 'j': + p = find_section_list (optarg, true); + p->extract = true; + sections_extracted = true; break; case 'R': p = find_section_list (optarg, true); diff --new-file -upr binutils-2.9.1.0.22b/binutils/objdump.c binutils-2.9.1.0.23/binutils/objdump.c --- binutils-2.9.1.0.22b/binutils/objdump.c Sat Feb 20 16:56:56 1999 +++ binutils-2.9.1.0.23/binutils/objdump.c Wed Mar 31 09:34:16 1999 @@ -1267,6 +1267,8 @@ disassemble_bytes (info, disassemble_fn, if (insns) { sfile.buffer = sfile.current = buf; + /* We make `buf' empty first. */ + buf [0] = '\0'; info->fprintf_func = (fprintf_ftype) objdump_sprintf; info->stream = (FILE *) &sfile; info->bytes_per_line = 0; @@ -1282,7 +1284,13 @@ disassemble_bytes (info, disassemble_fn, if (info->bytes_per_line != 0) bytes_per_line = info->bytes_per_line; if (bytes < 0) - break; + { + if (buf [0] != '\0') + /* We check if `buf` is empty. We may have some + error message in `buf'. */ + printf ("%s", buf); + break; + } } else { diff --new-file -upr binutils-2.9.1.0.22b/gas/ChangeLog.linux binutils-2.9.1.0.23/gas/ChangeLog.linux --- binutils-2.9.1.0.22b/gas/ChangeLog.linux Wed Feb 24 13:23:36 1999 +++ binutils-2.9.1.0.23/gas/ChangeLog.linux Wed Mar 31 10:21:36 1999 @@ -1,3 +1,36 @@ +Sun Mar 28 15:32:42 1999 H.J. Lu (hjl@gnu.org) + + * Makefile.in: Regenerated with automake 1.4. + +Sat Mar 27 20:53:07 1999 Linas Vepstas (linas@linas.org) + + * config/tc-i370.c: Fix a literal pool bug, correct support + for the supervisor (aka privledged aka kernel) instructions. + +Fri Sep 4 13:57:43 1998 Jakub Jelinek + + * config/tc-sparc.c (in_signed_range): Sign extend 32-bit words + to the host width. + +Wed Sep 2 11:31:14 1998 Richard Henderson + + * frags.c (frag_grow): Include the size of the frag struct in + the obstack chunk size. + + * subsegs.c (subseg_set_rest): Adjust the seginfo frchain start + if the new subseg comes before the old. + +Tue Sep 1 15:01:33 1998 Jakub Jelinek + + * config/tc-sparc.c (sparc_ip): Allow all digits in an + instruction to handle edge8 and edge16. + +1999-03-11 Andreas Schwab + + * config/atof-ieee.c (gen_to_words): Correctly round a + denormalized number. Fix off-by-one in range checking for + exponent in a denormal. + Wed Feb 24 13:18:50 1999 H.J. Lu (hjl@gnu.org) * config/tc-i386.h (RegRegmem): New. diff --new-file -upr binutils-2.9.1.0.22b/gas/Makefile.in binutils-2.9.1.0.23/gas/Makefile.in --- binutils-2.9.1.0.22b/gas/Makefile.in Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/gas/Makefile.in Wed Mar 31 09:34:16 1999 @@ -744,14 +744,16 @@ SCRIPTS = $(noinst_SCRIPTS) LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@ LEXLIB = @LEXLIB@ +YLWRAP = $(top_srcdir)/../ylwrap CFLAGS = @CFLAGS@ COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) CCLD = $(CC) LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@ DIST_COMMON = README ./stamp-h.in COPYING ChangeLog Makefile.am \ -Makefile.in NEWS acconfig.h acinclude.m4 aclocal.m4 config.in configure \ -configure.in gdbinit.in itbl-lex.c itbl-parse.c +Makefile.in NEWS acconfig.h acinclude.m4 aclocal.m4 config.in \ +config/m68k-parse.c configure configure.in gdbinit.in itbl-lex.c \ +itbl-parse.c DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) @@ -870,10 +872,8 @@ gasp-new$(EXEEXT): $(gasp_new_OBJECTS) $ .l.c: $(LEX) $(AM_LFLAGS) $(LFLAGS) $< && mv $(LEX_OUTPUT_ROOT).c $@ .y.c: - $(YACC) $(AM_YFLAGS) $(YFLAGS) $< && mv y.tab.c $*.c - if test -f y.tab.h; then \ - if cmp -s y.tab.h $*.h; then rm -f y.tab.h; else mv y.tab.h $*.h; fi; \ - else :; fi + $(SHELL) $(YLWRAP) "$(YACC)" $< y.tab.c $*.c y.tab.h $*.h -- $(AM_YFLAGS) $(YFLAGS) +config/m68k-parse.h: config/m68k-parse.c itbl-parse.h: itbl-parse.c @@ -1092,7 +1092,7 @@ distclean-generic: -test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES) maintainer-clean-generic: - -test -z "itbl-lexlitbl-parsehitbl-parsec" || rm -f itbl-lexl itbl-parseh itbl-parsec + -test -z "itbl-lexlconfig/m68k-parsehconfig/m68k-parsecitbl-parsehitbl-parsec" || rm -f itbl-lexl config/m68k-parseh config/m68k-parsec itbl-parseh itbl-parsec mostlyclean-am: mostlyclean-hdr mostlyclean-noinstPROGRAMS \ mostlyclean-compile mostlyclean-libtool \ mostlyclean-tags mostlyclean-generic diff --new-file -upr binutils-2.9.1.0.22b/gas/config/atof-ieee.c binutils-2.9.1.0.23/gas/config/atof-ieee.c --- binutils-2.9.1.0.22b/gas/config/atof-ieee.c Tue Mar 31 14:25:19 1998 +++ binutils-2.9.1.0.23/gas/config/atof-ieee.c Wed Mar 31 09:34:16 1999 @@ -460,7 +460,7 @@ gen_to_words (words, precision, exponent /* Bigger than one littlenum */ num_bits -= (LITTLENUM_NUMBER_OF_BITS - 1) - exponent_bits; *lp++ = word1; - if (num_bits + exponent_bits + 1 >= precision * LITTLENUM_NUMBER_OF_BITS) + if (num_bits + exponent_bits + 1 > precision * LITTLENUM_NUMBER_OF_BITS) { /* Exponent overflow */ make_invalid_floating_point_number (words); @@ -501,7 +501,7 @@ gen_to_words (words, precision, exponent if (next_bits (1)) { --lp; - if (prec_bits > LITTLENUM_NUMBER_OF_BITS) + if (prec_bits >= LITTLENUM_NUMBER_OF_BITS) { int n = 0; int tmp_bits; @@ -515,7 +515,19 @@ gen_to_words (words, precision, exponent --n; tmp_bits -= LITTLENUM_NUMBER_OF_BITS; } - if (tmp_bits > LITTLENUM_NUMBER_OF_BITS || (lp[n] & mask[tmp_bits]) != mask[tmp_bits]) + if (tmp_bits > LITTLENUM_NUMBER_OF_BITS + || (lp[n] & mask[tmp_bits]) != mask[tmp_bits] + || (prec_bits != (precision * LITTLENUM_NUMBER_OF_BITS + - exponent_bits - 1) +#ifdef TC_I386 + /* An extended precision float with only the integer + bit set would be invalid. That must be converted + to the smallest normalized number. */ + && !(precision == X_PRECISION + && prec_bits == (precision * LITTLENUM_NUMBER_OF_BITS + - exponent_bits - 2)) +#endif + )) { unsigned long carry; @@ -539,11 +551,18 @@ gen_to_words (words, precision, exponent << ((LITTLENUM_NUMBER_OF_BITS - 1) - exponent_bits)); *lp++ = word1; +#ifdef TC_I386 + /* Set the integer bit in the extended precision format. + This cannot happen on the m68k where the mantissa + just overflows into the integer bit above. */ + if (precision == X_PRECISION) + *lp++ = 1 << (LITTLENUM_NUMBER_OF_BITS - 1); +#endif while (lp < words_end) *lp++ = 0; } } - else if ((*lp & mask[prec_bits]) != mask[prec_bits]) + else *lp += 1; } diff --new-file -upr binutils-2.9.1.0.22b/gas/config/tc-i370.c binutils-2.9.1.0.23/gas/config/tc-i370.c --- binutils-2.9.1.0.22b/gas/config/tc-i370.c Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/gas/config/tc-i370.c Wed Mar 31 09:34:16 1999 @@ -95,10 +95,13 @@ S/370 options: (these have not yet been static void i370_byte PARAMS ((int)); static void i370_tc PARAMS ((int)); +static void i370_ebcdic PARAMS ((int)); static void i370_dc PARAMS ((int)); static void i370_ds PARAMS ((int)); static void i370_rmode PARAMS ((int)); +static void i370_csect PARAMS ((int)); +static void i370_dsect PARAMS ((int)); static void i370_ltorg PARAMS ((int)); static void i370_using PARAMS ((int)); static void i370_drop PARAMS ((int)); @@ -124,6 +127,11 @@ const pseudo_typeS md_pseudo_table[] = { "dc", i370_dc, 0 }, { "ds", i370_ds, 0 }, { "rmode", i370_rmode, 0 }, + { "csect", i370_csect, 0 }, + { "dsect", i370_dsect, 0 }, + + /* enable ebcdic strings e.g. for 3270 support */ + { "ebcdic", i370_ebcdic, 0 }, #ifdef OBJ_ELF { "long", i370_elf_cons, 4 }, @@ -160,7 +168,6 @@ static i370_insn_t i370_insert_operand PARAMS ((i370_insn_t insn, const struct i370_operand *operand, offsetT val, char *file, unsigned int line)); static void i370_macro PARAMS ((char *str, const struct i370_macro *macro)); -// static int ppc_is_toc_sym PARAMS ((symbolS *sym)); /* Predefined register names if -mregnames */ /* In general, there are lots of them, in an attempt to be compatible */ @@ -337,6 +344,8 @@ register_name (expressionP) else if (!reg_names_p) return false; + while (' ' == *name) name = ++input_line_pointer; + /* if its a number, treat it as a number */ /* if its alpha, look to see if it's in the register table */ if (!isalpha (name[0])) { @@ -366,53 +375,6 @@ register_name (expressionP) return false; } -/* Whether to do the special parsing. */ -static boolean cr_operand = false; - -/* Names to recognize in a condition code. This table is sorted. */ -// hack alert -- the i370 has no externally addressible condition register? -// these are never really used in so are irrelevent. -static const struct pd_reg cond_names[] = -{ - { "eq", 0 }, - { "gt", 1 }, - { "lt", 2 }, -// { "so", 3 }, - { "un", 3 } -}; - -/* Parsing function. This returns non-zero if it recognized an - expression. */ -/* This function is called for each symbol seen in an expression. - Currently, it does mostly nothing, since condition names are not - used in the assembly. However, it is a potentially powerful - place to do stuff .. - - */ - -int -i370_parse_name (name, expr) - const char *name; - expressionS *expr; -{ - int val; - - return 0; // just punt for now. - - if (! cr_operand) - return 0; - - val = reg_name_search (cond_names, sizeof cond_names / sizeof cond_names[0], - name); - if (val < 0) - return 0; - - expr->X_op = O_constant; - expr->X_add_number = val; - - return 1; -} - /* Local variables. */ /* The type of processor we are assembling for. This is one or more @@ -747,7 +709,15 @@ i370_insert_operand (insn, operand, val, #ifdef OBJ_ELF -/* Parse @got, etc. and return the desired relocation. */ +/* Parse @got, etc. and return the desired relocation. + * Currently, i370 does not support (don't really need to support) any + * of these fancier markups ... for example, no one is going to + * write 'L 6,=V(bogus)@got' it just doesn't make sense (at least to me). + * So basically, we could get away with this routine returning + * BFD_RELOC_UNUSED in all circumstances. However, I'll leave + * in for now in case someone ambitious finds a good use for this stuff ... + * this routine was pretty much just copied from the powerpc code ... + */ static bfd_reloc_code_real_type i370_elf_suffix (str_p, exp_p) char **str_p; @@ -777,22 +747,20 @@ i370_elf_suffix (str_p, exp_p) // MAP ("got@h", BFD_RELOC_HI16_GOTOFF), // MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), MAP ("fixup", BFD_RELOC_CTOR), /* warnings with -mrelocatable */ -// MAP ("plt", BFD_RELOC_24_PLT_PCREL), -// MAP ("pltrel24", BFD_RELOC_24_PLT_PCREL), +// MAP ("plt", BFD_RELOC_24_PLT_PCREL), +// MAP ("pltrel24", BFD_RELOC_24_PLT_PCREL), +// MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), +// MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), +// MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), // MAP ("copy", BFD_RELOC_PPC_COPY), + // MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), -// MAP ("local24pc", BFD_RELOC_PPC_LOCAL24PC), -// MAP ("local", BFD_RELOC_PPC_LOCAL24PC), // MAP ("pltrel", BFD_RELOC_32_PLT_PCREL), -// MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), -// MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), -// MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), // MAP ("sdarel", BFD_RELOC_GPREL16), // MAP ("sectoff", BFD_RELOC_32_BASEREL), // MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), // MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), // MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), -// MAP ("xgot", BFD_RELOC_PPC_TOC16), // { (char *)0, 0, BFD_RELOC_UNUSED } }; @@ -895,6 +863,161 @@ i370_elf_cons (nbytes) } +/* ASCII to EBCDIC conversion table. */ +static unsigned char ascebc[256] = +{ + /*00 NL SH SX EX ET NQ AK BL */ + 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F, + /*08 BS HT LF VT FF CR SO SI */ + 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + /*10 DL D1 D2 D3 D4 NK SN EB */ + 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26, + /*18 CN EM SB EC FS GS RS US */ + 0x18, 0x19, 0x3F, 0x27, 0x1C, 0x1D, 0x1E, 0x1F, + /*20 SP ! " # $ % & ' */ + 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D, + /*28 ( ) * + , - . / */ + 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61, + /*30 0 1 2 3 4 5 6 7 */ + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, + /*38 8 9 : ; < = > ? */ + 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F, + /*40 @ A B C D E F G */ + 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, + /*48 H I J K L M N O */ + 0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, + /*50 P Q R S T U V W */ + 0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, + /*58 X Y Z [ \ ] ^ _ */ + 0xE7, 0xE8, 0xE9, 0xAD, 0xE0, 0xBD, 0x5F, 0x6D, + /*60 ` a b c d e f g */ + 0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + /*68 h i j k l m n o */ + 0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, + /*70 p q r s t u v w */ + 0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, + /*78 x y z { | } ~ DL */ + 0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, + 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0xFF +}; + +/* EBCDIC to ASCII conversion table. */ +unsigned char ebcasc[256] = +{ + /*00 NU SH SX EX PF HT LC DL */ + 0x00, 0x01, 0x02, 0x03, 0x00, 0x09, 0x00, 0x7F, + /*08 SM VT FF CR SO SI */ + 0x00, 0x00, 0x00, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + /*10 DE D1 D2 TM RS NL BS IL */ + 0x10, 0x11, 0x12, 0x13, 0x14, 0x0A, 0x08, 0x00, + /*18 CN EM CC C1 FS GS RS US */ + 0x18, 0x19, 0x00, 0x00, 0x1C, 0x1D, 0x1E, 0x1F, + /*20 DS SS FS BP LF EB EC */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x17, 0x1B, + /*28 SM C2 EQ AK BL */ + 0x00, 0x00, 0x00, 0x00, 0x05, 0x06, 0x07, 0x00, + /*30 SY PN RS UC ET */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + /*38 C3 D4 NK SU */ + 0x00, 0x00, 0x00, 0x00, 0x14, 0x15, 0x00, 0x1A, + /*40 SP */ + 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*48 . < ( + | */ + 0x00, 0x00, 0x00, 0x2E, 0x3C, 0x28, 0x2B, 0x7C, + /*50 & */ + 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*58 ! $ * ) ; ^ */ + 0x00, 0x00, 0x21, 0x24, 0x2A, 0x29, 0x3B, 0x5E, + /*60 - / */ + 0x2D, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*68 , % _ > ? */ + 0x00, 0x00, 0x00, 0x2C, 0x25, 0x5F, 0x3E, 0x3F, + /*70 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*78 ` : # @ ' = " */ + 0x00, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22, + /*80 a b c d e f g */ + 0x00, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + /*88 h i { */ + 0x68, 0x69, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x00, + /*90 j k l m n o p */ + 0x00, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, + /*98 q r } */ + 0x71, 0x72, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x00, + /*A0 ~ s t u v w x */ + 0x00, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, + /*A8 y z [ */ + 0x79, 0x7A, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, + /*B0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*B8 ] */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x5D, 0x00, 0x00, + /*C0 { A B C D E F G */ + 0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + /*C8 H I */ + 0x48, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*D0 } J K L M N O P */ + 0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, + /*D8 Q R */ + 0x51, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*E0 \ S T U V W X */ + 0x5C, 0x00, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, + /*E8 Y Z */ + 0x59, 0x5A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /*F0 0 1 2 3 4 5 6 7 */ + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + /*F8 8 9 */ + 0x38, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF +}; + +/* ebcdic translation tables needed for 3270 support */ +static void +i370_ebcdic (xxx) + int xxx; +{ + char *p, *end; + char delim = 0; + size_t nbytes; + + nbytes = strlen (input_line_pointer); + end = input_line_pointer + nbytes; + while ('\r' == *end) end --; + while ('\n' == *end) end --; + + delim = *input_line_pointer; + if (('\'' == delim) || ('\"' == delim)) { + input_line_pointer ++; + end = rindex (input_line_pointer, delim); + } + + if (end > input_line_pointer) { + nbytes = end - input_line_pointer +1; + p = frag_more (nbytes); + while (end > input_line_pointer) { + *p = ascebc [(unsigned char)(*input_line_pointer)]; + ++p; ++input_line_pointer; + } + *p = '\0'; + } + if (delim == *input_line_pointer) ++input_line_pointer; +} + + /* stub out a couple of routines */ static void i370_rmode (xxx) @@ -903,6 +1026,28 @@ i370_rmode (xxx) as_tsktsk ("rmode ignored"); } +static void +i370_dsect (xxx) + int xxx; +{ + as_tsktsk ("dsect not supported"); +} + +static void +i370_csect (xxx) + int xxx; +{ + char *save_line = input_line_pointer; + static char section[] = ".text\n"; + + /* Just pretend this is .section .text */ + input_line_pointer = section; + obj_elf_section (xxx); + + input_line_pointer = save_line; +} + + /* DC Define Const is only partially supported. * For samplecode on what to do, look at i370_elf_cons() above. * This code handles pseudoops of the style @@ -1186,8 +1331,8 @@ i370_elf_validate_fix (fixp, seg) #define LITERAL_POOL_SUPPORT #ifdef LITERAL_POOL_SUPPORT -/* First cut at supporting literal pools within the text section. */ -/* Brazenly copied from tc-arm.c */ +/* Provide support for literal pools within the text section. */ +/* Loosely based on similar code from tc-arm.c */ /* * current_poolP points at the symbol that names our literal pool * lit_pool_num increments from zero to infinity and uniquely id's @@ -1201,7 +1346,6 @@ typedef struct literalS struct expressionS exp; char * sym_name; char size; /* 1,2,4 or 8 */ -// symbolS *symp; } literalT; literalT literals[MAX_LITERAL_POOL_SIZE]; @@ -1233,6 +1377,7 @@ static void add_to_lit_pool (expressionS *exx, char *name, int sz) { int lit_count = 0; + int total_sz = 0; /* start a new pool, if necessary */ if (NULL == current_poolP) current_poolP = symbol_make_empty(); @@ -1240,10 +1385,13 @@ add_to_lit_pool (expressionS *exx, char /* Check if this literal value is already in the pool: */ /* hack alert -- we should probably be checking expressions * of type O_symbol as well ... */ + /* hack alert XXX this is probably(certainly?) broken for O_big, + * which includes 64-bit long-longs ... + */ while (lit_count < next_literal_pool_place) { if ( - (exx->X_op == O_constant) + ( (exx->X_op == O_constant) ) && (literals[lit_count].exp.X_op == exx->X_op) && (literals[lit_count].exp.X_add_number == exx->X_add_number) && (literals[lit_count].exp.X_unsigned == exx->X_unsigned) @@ -1255,6 +1403,7 @@ add_to_lit_pool (expressionS *exx, char && (NULL != name) && (!strcmp (name, literals[lit_count].sym_name)) ) { break; } + total_sz += literals[lit_count].size; lit_count ++; } @@ -1281,14 +1430,8 @@ add_to_lit_pool (expressionS *exx, char * recent .using directive. Thus, the grand total value of the * expression is the distance from .using to the literal. */ - - /* hack alert --- should be size, not 4. In fact, these are - * supposed to be getting stored in size-sorted order, which means - * that we don't/won't even know the X_add_number value until - * we actually dump the literal pool. Yuck. - */ exx->X_add_symbol = current_poolP; - exx->X_add_number = (lit_count)*4; + exx->X_add_number = total_sz; exx->X_op_symbol = NULL; i370_make_relative (exx); } @@ -1348,30 +1491,52 @@ symbol_locate (symbolP, name, segment, v #endif /* DEBUG_SYMS */ } -/* handle expressions that are USING-relative offsets - * these are expressions typically of the form "* + const" - * where "*" means relative offset since the last using +/* i370_addr_offset() will convert operand expressions + * that appear to be absolute into thier base-register + * relative form. These expressions come in two types: + * + * (1) of the form "* + const" * where "*" means + * relative offset since the last using * i.e. "*" means ".-using_baseaddr" + * + * (2) labels, which are never absolute, but are always + * relative to the last "using". Anything with an alpha + * character is considered to be a label (since symbols + * can never be operands), and since we've already handled + * register operands. For example, "BL .L33" branch low + * to .L33 RX form insn frequently terminates for-loops, */ static boolean i370_addr_offset (expressionS *exx) { - char *dot; + char *dot, *lab; + int islabel = 0; + + /* search for a label; anything with an alpha will do */ + lab = input_line_pointer; + while (*lab && (',' != *lab) && ('(' != *lab)) { + if (isdigit(*lab)) break; + if (isalpha(*lab)) { + islabel = 1; + break; + } + ++lab; + } /* See if operand has a * in it */ dot = strchr (input_line_pointer, '*'); - if (!dot) return false; + if (!dot && !islabel) return false; /* replace * with . and let expr munch on it. */ - *dot = '.'; + if (dot) *dot = '.'; expression (exx); /* OK, now we have to subtract the "using" location */ i370_make_relative (exx); /* put the * back */ - *dot = '*'; + if (dot) *dot = '*'; return true; } @@ -1410,7 +1575,7 @@ i370_addr_cons (expressionS *exp) expression (exp); /* we use a simple string name to collapse together - * multiple refrences to the same accress literal + * multiple refrences to the same address literal */ name_len = strcspn (sym_name, ", "); delim = *(sym_name + name_len); @@ -1437,7 +1602,7 @@ i370_addr_cons (expressionS *exp) /* extract length, if it is present; hack alert -- assume single-digit * length */ if ('L' == name[1]) { - cons_len = name[2] - '0'; /* should work for ascii and ebcidic */ + cons_len = name[2] - '0'; /* should work for ascii and ebcdic */ input_line_pointer += 2; } @@ -1500,9 +1665,7 @@ i370_addr_cons (expressionS *exp) /* Dump the contents of the literal pool that we've accumulated so far. - * This aligns the pool to the size of the largest literal in the pool, - * and then dumps them in a sorted order, with the largest literals - * getting dumped first. + * This aligns the pool to the size of the largest literal in the pool. */ static void @@ -1512,7 +1675,6 @@ i370_ltorg (ignore) int lit_count = 0; int biggest_literal_size = 0; int biggest_align = 0; - int size=0; char pool_name[20]; if (NULL == current_poolP) @@ -1549,30 +1711,26 @@ i370_ltorg (ignore) * entries in the pool .... wonder how to make it print more ... */ /* output largest literals first, then the smaller ones. */ - for (size=biggest_literal_size; size>1; size /=2) { - lit_count = 0; - while (lit_count < next_literal_pool_place) { + lit_count = 0; + while (lit_count < next_literal_pool_place) { - if (literals[lit_count].size == size) { #define EMIT_ADDR_CONS_SYMBOLS #ifdef EMIT_ADDR_CONS_SYMBOLS - /* create a bogus symbol, add it to the pool ... - * For the most part, I think this is a useless excercise, - * except that having these symbol names in the objects - * is vaguely useful for debugging ... - */ - if (literals[lit_count].sym_name) { - symbolS * symP = symbol_make_empty(); - symbol_locate (symP, literals[lit_count].sym_name, now_seg, - (valueT) frag_now_fix (), frag_now); - symbol_table_insert (symP); - } + /* create a bogus symbol, add it to the pool ... + * For the most part, I think this is a useless excercise, + * except that having these symbol names in the objects + * is vaguely useful for debugging ... + */ + if (literals[lit_count].sym_name) { + symbolS * symP = symbol_make_empty(); + symbol_locate (symP, literals[lit_count].sym_name, now_seg, + (valueT) frag_now_fix (), frag_now); + symbol_table_insert (symP); + } #endif /* EMIT_ADDR_CONS_SYMBOLS */ - emit_expr (&(literals[lit_count].exp), literals[lit_count].size); - } - lit_count ++; - } + emit_expr (&(literals[lit_count].exp), literals[lit_count].size); + lit_count ++; } next_literal_pool_place = 0; @@ -1705,8 +1863,7 @@ md_assemble (str) int have_optional_index, have_optional_basereg, have_optional_reg; int skip_optional_index, skip_optional_basereg, skip_optional_reg; int off_by_one; - int need_paren; - int next_opindex; + int need_paren = 0; struct i370_fixup fixups[MAX_INSN_FIXUPS]; int fc; char *f; @@ -1744,8 +1901,8 @@ md_assemble (str) while (isspace (*str)) ++str; - /* I370 operands are just expressions. The only real issue is - that many operand types are optional. The optional operands + /* I370 operands are either expressions or address constants. + Many operand types are optional. The optional operands are always surrounded by parens, and are used to denote the base register ... e.g. "A R1, D2" or "A R1, D2(,B2) as opposed to the fully-formed "A R1, D2(X2,B2)". Note also the = sign, @@ -1813,14 +1970,17 @@ md_assemble (str) */ off_by_one = 0; if (0 == strcasecmp ("CLC", opcode->name)) off_by_one = 1; + else if (0 == strcasecmp ("ED", opcode->name)) off_by_one = 1; + else if (0 == strcasecmp ("EDMK", opcode->name)) off_by_one = 1; else if (0 == strcasecmp ("MVC", opcode->name)) off_by_one = 1; + else if (0 == strcasecmp ("MVCIN", opcode->name)) off_by_one = 1; + else if (0 == strcasecmp ("MVN", opcode->name)) off_by_one = 1; + else if (0 == strcasecmp ("MVZ", opcode->name)) off_by_one = 1; else if (0 == strcasecmp ("NC", opcode->name)) off_by_one = 1; else if (0 == strcasecmp ("OC", opcode->name)) off_by_one = 1; else if (0 == strcasecmp ("XC", opcode->name)) off_by_one = 1; /* Gather the operands. */ - need_paren = 0; - next_opindex = 0; fc = 0; for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) { @@ -1830,58 +1990,36 @@ md_assemble (str) expressionS ex; char endc; - if (next_opindex == 0) - operand = &i370_operands[*opindex_ptr]; - else - { - operand = &i370_operands[next_opindex]; - next_opindex = 0; - } - + operand = &i370_operands[*opindex_ptr]; errmsg = NULL; -// /* If this is a fake operand, then we do not expect anything -// from the input. */ -// if ((operand->flags & PPC_OPERAND_FAKE) != 0) -// { -// insn = (*operand->insert) (insn, 0L, &errmsg); -// if (errmsg != (const char *) NULL) -// as_bad (errmsg); -// continue; -// } - /* If this is an index operand, and we are skipping it, just insert a zero. */ - if ((operand->flags & I370_OPERAND_INDEX) != 0 - && skip_optional_index) + if (skip_optional_index && + ((operand->flags & I370_OPERAND_INDEX) != 0)) { insn = i370_insert_operand (insn, operand, 0, (char *) NULL, 0); -// if ((operand->flags & PPC_OPERAND_NEXT) != 0) -// next_opindex = *opindex_ptr + 1; continue; } /* If this is the base operand, and we are skipping it, just insert the current using basreg. */ - if ((operand->flags & I370_OPERAND_BASE) != 0 - && skip_optional_basereg) + if (skip_optional_basereg && + ((operand->flags & I370_OPERAND_BASE) != 0)) { - if (0 > i370_using_regno) { as_bad ("not using any base register"); } insn = i370_insert_operand (insn, operand, i370_using_regno, (char *) NULL, 0); -// if ((operand->flags & PPC_OPERAND_NEXT) != 0) -// next_opindex = *opindex_ptr + 1; continue; } /* If this is an optional operand, and we are skipping it, Use zero (since a non-zero value would denote a register) */ - if ((operand->flags & I370_OPERAND_OPTIONAL) != 0 - && skip_optional_reg) + if (skip_optional_reg && + ((operand->flags & I370_OPERAND_OPTIONAL) != 0)) { insn = i370_insert_operand (insn, operand, 0, (char *) NULL, 0); @@ -1899,6 +2037,7 @@ md_assemble (str) if (skip_optional_index && (',' == *input_line_pointer)) { *input_line_pointer = ' '; + input_line_pointer ++; } if (! register_name (&ex)) { @@ -1918,7 +2057,7 @@ md_assemble (str) /* perform some off-by-one hacks on the length field of certain instructions. * Its such a shame to have to do this, but the problem is that HLASM got * defined so that the programmer specifies a length that is one greater - * than what the machine isntruction wants. + * than what the machine instruction wants. * Sigh. */ if (off_by_one && (0 == strcasecmp ("SS L", operand->name))) @@ -1938,7 +2077,10 @@ md_assemble (str) else if (ex.X_op == O_constant) { #ifdef OBJ_ELF - /* Allow @HA, @L, @H on constants. */ + /* Allow @HA, @L, @H on constants. + * Well actually, no we don't; there really don't make sense + * (at least not to me) for the i370. However, this code is + * left here for any dubious future expansion reasons ... */ char *orig_str = str; if ((reloc = i370_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED) @@ -1977,7 +2119,7 @@ md_assemble (str) #ifdef OBJ_ELF else if ((reloc = i370_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED) { -printf ("md_assemble(): duuuuuuude suffixed relo\n"); + as_tsktsk ("md_assemble(): suffixed relocations not supported\n"); /* We need to generate a fixup for this expression. */ if (fc >= MAX_INSN_FIXUPS) @@ -2108,29 +2250,6 @@ printf (" gwana doo fixup %d \n", i); } } -// #ifndef WORKING_DOT_WORD -// /* Handle long and short jumps */ -// void -// md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) -// char *ptr; -// addressT from_addr, to_addr; -// fragS *frag; -// symbolS *to_symbol; -// { -// abort (); -// } -// -// void -// md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) -// char *ptr; -// addressT from_addr, to_addr; -// fragS *frag; -// symbolS *to_symbol; -// { -// abort (); -// } -// #endif -// /* Handle a macro. Gather all the operands, transform them as described by the macro, and call md_assemble recursively. All the operands are separated by commas; we don't accept parentheses diff --new-file -upr binutils-2.9.1.0.22b/gas/config/tc-sparc.c binutils-2.9.1.0.23/gas/config/tc-sparc.c --- binutils-2.9.1.0.22b/gas/config/tc-sparc.c Tue Mar 31 14:25:25 1998 +++ binutils-2.9.1.0.23/gas/config/tc-sparc.c Wed Mar 31 09:34:16 1999 @@ -758,7 +758,11 @@ in_signed_range (val, max) if (max <= 0) abort (); if (val > max) - return 0; + { + if (sparc_arch_size >= BFD_ARCH_SIZE + || (val = val << 32 >> 32) > max) + return 0; + } if (val < ~max) return 0; return 1; @@ -1124,7 +1128,7 @@ sparc_ip (str, pinsn) int comma = 0; int v9_arg_p; - for (s = str; islower ((unsigned char) *s) || (*s >= '0' && *s <= '3'); ++s) + for (s = str; islower ((unsigned char) *s) || (s > str && *s >= '0' && *s <= '8'); ++s) ; switch (*s) diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/ChangeLog.linux binutils-2.9.1.0.23/gas/doc/ChangeLog.linux --- binutils-2.9.1.0.22b/gas/doc/ChangeLog.linux Thu Oct 8 16:10:22 1998 +++ binutils-2.9.1.0.23/gas/doc/ChangeLog.linux Wed Mar 31 10:25:55 1999 @@ -1,3 +1,18 @@ +Sat Mar 27 20:53:07 1999 Linas Vepstas (linas@linas.org) + + * all.texi: Add I370 documentations. + * as.texinfo: Likewise. + + * c-i370.texi: New. + + * Makefile.am (CPU_DOCS): Add c-i370.texi. + + * Makefile.in: Regenerated. + +Sun Mar 7 16:16:57 1999 H.J. Lu (hjl@gnu.org) + + * c-i386.texi: Updated from gas-990223. + Fri Oct 2 08:03:07 1998 "Jeff B Epler" * gas/doc/c-i386.texi: Add i386-SIMD. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/Makefile.am binutils-2.9.1.0.23/gas/doc/Makefile.am --- binutils-2.9.1.0.22b/gas/doc/Makefile.am Mon Apr 27 12:03:52 1998 +++ binutils-2.9.1.0.23/gas/doc/Makefile.am Wed Mar 31 09:34:16 1999 @@ -22,6 +22,7 @@ CPU_DOCS = \ c-h8300.texi \ c-h8500.texi \ c-hppa.texi \ + c-i370.texi \ c-i386.texi \ c-i960.texi \ c-m68k.texi \ diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/Makefile.in binutils-2.9.1.0.23/gas/doc/Makefile.in --- binutils-2.9.1.0.22b/gas/doc/Makefile.in Mon Jun 29 08:37:10 1998 +++ binutils-2.9.1.0.23/gas/doc/Makefile.in Wed Mar 31 09:34:16 1999 @@ -102,6 +102,7 @@ CPU_DOCS = \ c-h8500.texi \ c-hppa.texi \ c-i386.texi \ + c-i370.texi \ c-i960.texi \ c-m68k.texi \ c-mips.texi \ diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/all.texi binutils-2.9.1.0.23/gas/doc/all.texi --- binutils-2.9.1.0.22b/gas/doc/all.texi Thu Jan 15 09:36:35 1998 +++ binutils-2.9.1.0.23/gas/doc/all.texi Wed Mar 31 09:34:16 1999 @@ -32,6 +32,7 @@ @set H8/300 @set H8/500 @set SH +@set I370 @set I80386 @set I960 @set MIPS diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info binutils-2.9.1.0.23/gas/doc/as.info --- binutils-2.9.1.0.22b/gas/doc/as.info Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info Wed Mar 31 09:51:20 1999 @@ -28,10 +28,10 @@ Indirect: as.info-1: 884 as.info-2: 48330 as.info-3: 97421 -as.info-4: 147389 -as.info-5: 197240 -as.info-6: 240836 -as.info-7: 280099 +as.info-4: 146933 +as.info-5: 196717 +as.info-6: 245265 +as.info-7: 286210  Tag Table: (Indirect) @@ -172,141 +172,149 @@ Node: Uleb128120991 Node: Word121306 Node: Deprecated123143 Node: Machine Dependencies123379 -Node: ARC-Dependent125075 -Node: ARC-Opts125389 -Node: ARC-Float126123 -Node: ARC-Directives126421 -Node: AMD29K-Dependent126814 -Node: AMD29K Options127195 -Node: AMD29K Syntax127369 -Node: AMD29K-Macros127633 -Node: AMD29K-Chars127884 -Node: AMD29K-Regs128147 -Node: AMD29K Floating Point129411 -Node: AMD29K Directives129617 -Node: AMD29K Opcodes131025 -Node: ARM-Dependent131361 -Node: ARM Options131735 -Node: ARM Syntax133475 -Node: ARM-Chars133695 -Node: ARM-Regs133894 -Node: ARM Floating Point134066 -Node: ARM Directives134256 -Node: ARM Opcodes135175 -Node: D10V-Dependent135511 -Node: D10V-Opts135855 -Node: D10V-Syntax136488 -Node: D10V-Size137008 -Node: D10V-Subs137968 -Node: D10V-Chars138990 -Node: D10V-Regs140576 -Node: D10V-Addressing141607 -Node: D10V-Word142280 -Node: D10V-Float142781 -Node: D10V-Opcodes143083 -Node: H8/300-Dependent143467 -Node: H8/300 Options143871 -Node: H8/300 Syntax144052 -Node: H8/300-Chars144339 -Node: H8/300-Regs144623 -Node: H8/300-Addressing145527 -Node: H8/300 Floating Point146553 -Node: H8/300 Directives146869 -Node: H8/300 Opcodes147389 -Node: H8/500-Dependent155742 -Node: H8/500 Options156146 -Node: H8/500 Syntax156327 -Node: H8/500-Chars156614 -Node: H8/500-Regs156905 -Node: H8/500-Addressing157661 -Node: H8/500 Floating Point158278 -Node: H8/500 Directives158594 -Node: H8/500 Opcodes158913 -Node: HPPA-Dependent164026 -Node: HPPA Notes164448 -Node: HPPA Options165195 -Node: HPPA Syntax165379 -Node: HPPA Floating Point166638 -Node: HPPA Directives166833 -Node: HPPA Opcodes173424 -Node: i386-Dependent173672 -Node: i386-Options174418 -Node: i386-Syntax174562 -Node: i386-Opcodes176512 -Node: i386-Regs178631 -Node: i386-prefixes179772 -Node: i386-Memory181441 -Node: i386-jumps183715 -Node: i386-Float184785 -Node: i386-SIMD186275 -Node: i386-16bit187458 -Node: i386-Notes189849 -Node: i960-Dependent190690 -Node: Options-i960191082 -Node: Floating Point-i960194963 -Node: Directives-i960195220 -Node: Opcodes for i960197240 -Node: callj-i960197846 -Node: Compare-and-branch-i960198321 -Node: M68K-Dependent200210 -Node: M68K-Opts200664 -Node: M68K-Syntax205612 -Node: M68K-Moto-Syntax207440 -Node: M68K-Float210018 -Node: M68K-Directives210527 -Node: M68K-opcodes211122 -Node: M68K-Branch211334 -Node: M68K-Chars214149 -Node: MIPS-Dependent214547 -Node: MIPS Opts215427 -Node: MIPS Object218263 -Node: MIPS Stabs219818 -Node: MIPS ISA220529 -Node: MIPS autoextend221637 -Node: MIPS insn222348 -Node: MIPS option stack222834 -Node: SH-Dependent223547 -Node: SH Options223930 -Node: SH Syntax224095 -Node: SH-Chars224354 -Node: SH-Regs224633 -Node: SH-Addressing225232 -Node: SH Floating Point226126 -Node: SH Directives226422 -Node: SH Opcodes226778 -Node: Sparc-Dependent231025 -Node: Sparc-Opts231397 -Node: Sparc-Aligned-Data233643 -Node: Sparc-Float234487 -Node: Sparc-Directives234677 -Node: Z8000-Dependent235895 -Node: Z8000 Options236854 -Node: Z8000 Syntax237029 -Node: Z8000-Chars237305 -Node: Z8000-Regs237523 -Node: Z8000-Addressing238295 -Node: Z8000 Directives239238 -Node: Z8000 Opcodes240836 -Node: Vax-Dependent250772 -Node: VAX-Opts251279 -Node: VAX-float253569 -Node: VAX-directives254190 -Node: VAX-opcodes255039 -Node: VAX-branch255417 -Node: VAX-operands257913 -Node: VAX-no258665 -Node: V850-Dependent258891 -Node: V850 Options259277 -Node: V850 Syntax260307 -Node: V850-Chars260533 -Node: V850-Regs260683 -Node: V850 Floating Point262058 -Node: V850 Directives262253 -Node: V850 Opcodes262927 -Node: Reporting Bugs267420 -Node: Bug Criteria268143 -Node: Bug Reporting268903 -Node: Acknowledgements275472 -Node: Index280099 +Node: ARC-Dependent125139 +Node: ARC-Opts125453 +Node: ARC-Float126187 +Node: ARC-Directives126485 +Node: AMD29K-Dependent126878 +Node: AMD29K Options127259 +Node: AMD29K Syntax127433 +Node: AMD29K-Macros127697 +Node: AMD29K-Chars127948 +Node: AMD29K-Regs128211 +Node: AMD29K Floating Point129475 +Node: AMD29K Directives129681 +Node: AMD29K Opcodes131089 +Node: ARM-Dependent131425 +Node: ARM Options131799 +Node: ARM Syntax133539 +Node: ARM-Chars133759 +Node: ARM-Regs133958 +Node: ARM Floating Point134130 +Node: ARM Directives134320 +Node: ARM Opcodes135239 +Node: D10V-Dependent135575 +Node: D10V-Opts135919 +Node: D10V-Syntax136552 +Node: D10V-Size137072 +Node: D10V-Subs138032 +Node: D10V-Chars139054 +Node: D10V-Regs140640 +Node: D10V-Addressing141671 +Node: D10V-Word142344 +Node: D10V-Float142845 +Node: D10V-Opcodes143147 +Node: H8/300-Dependent143531 +Node: H8/300 Options143935 +Node: H8/300 Syntax144116 +Node: H8/300-Chars144403 +Node: H8/300-Regs144687 +Node: H8/300-Addressing145591 +Node: H8/300 Floating Point146617 +Node: H8/300 Directives146933 +Node: H8/300 Opcodes147453 +Node: H8/500-Dependent155806 +Node: H8/500 Options156210 +Node: H8/500 Syntax156391 +Node: H8/500-Chars156678 +Node: H8/500-Regs156969 +Node: H8/500-Addressing157725 +Node: H8/500 Floating Point158342 +Node: H8/500 Directives158658 +Node: H8/500 Opcodes158977 +Node: HPPA-Dependent164090 +Node: HPPA Notes164515 +Node: HPPA Options165262 +Node: HPPA Syntax165446 +Node: HPPA Floating Point166705 +Node: HPPA Directives166900 +Node: HPPA Opcodes173491 +Node: ESA/390-Dependent173739 +Node: ESA/390 Notes174189 +Node: ESA/390 Options174788 +Node: ESA/390 Syntax174987 +Node: ESA/390 Floating Point177148 +Node: ESA/390 Directives177417 +Node: ESA/390 Opcodes178727 +Node: i386-Dependent178978 +Node: i386-Options179786 +Node: i386-Syntax179930 +Node: i386-Mnemonics182043 +Node: i386-Regs184185 +Node: i386-Prefixes185328 +Node: i386-Memory187416 +Node: i386-jumps189725 +Node: i386-Float190815 +Node: i386-SIMD192633 +Node: i386-16bit193731 +Node: i386-Bugs195137 +Node: i386-Notes195877 +Node: i960-Dependent196717 +Node: Options-i960197109 +Node: Floating Point-i960200990 +Node: Directives-i960201247 +Node: Opcodes for i960203267 +Node: callj-i960203873 +Node: Compare-and-branch-i960204348 +Node: M68K-Dependent206237 +Node: M68K-Opts206691 +Node: M68K-Syntax211639 +Node: M68K-Moto-Syntax213467 +Node: M68K-Float216045 +Node: M68K-Directives216554 +Node: M68K-opcodes217149 +Node: M68K-Branch217361 +Node: M68K-Chars220176 +Node: MIPS-Dependent220574 +Node: MIPS Opts221454 +Node: MIPS Object224290 +Node: MIPS Stabs225845 +Node: MIPS ISA226556 +Node: MIPS autoextend227664 +Node: MIPS insn228375 +Node: MIPS option stack228861 +Node: SH-Dependent229574 +Node: SH Options229957 +Node: SH Syntax230122 +Node: SH-Chars230381 +Node: SH-Regs230660 +Node: SH-Addressing231259 +Node: SH Floating Point232153 +Node: SH Directives232449 +Node: SH Opcodes232805 +Node: Sparc-Dependent237052 +Node: Sparc-Opts237424 +Node: Sparc-Aligned-Data239670 +Node: Sparc-Float240514 +Node: Sparc-Directives240704 +Node: Z8000-Dependent241922 +Node: Z8000 Options242881 +Node: Z8000 Syntax243056 +Node: Z8000-Chars243332 +Node: Z8000-Regs243550 +Node: Z8000-Addressing244322 +Node: Z8000 Directives245265 +Node: Z8000 Opcodes246863 +Node: Vax-Dependent256799 +Node: VAX-Opts257306 +Node: VAX-float259596 +Node: VAX-directives260217 +Node: VAX-opcodes261066 +Node: VAX-branch261444 +Node: VAX-operands263940 +Node: VAX-no264692 +Node: V850-Dependent264918 +Node: V850 Options265304 +Node: V850 Syntax266334 +Node: V850-Chars266560 +Node: V850-Regs266710 +Node: V850 Floating Point268085 +Node: V850 Directives268280 +Node: V850 Opcodes268954 +Node: Reporting Bugs273447 +Node: Bug Criteria274170 +Node: Bug Reporting274930 +Node: Acknowledgements281499 +Node: Index286210  End Tag Table diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info-3 binutils-2.9.1.0.23/gas/doc/as.info-3 --- binutils-2.9.1.0.22b/gas/doc/as.info-3 Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info-3 Wed Mar 31 09:51:20 1999 @@ -798,6 +798,8 @@ subject, see the hardware manufacturer's * HPPA-Dependent:: HPPA Dependent Features +* ESA/390-Dependent:: IBM ESA/390 Dependent Features + * i386-Dependent:: Intel 80386 Dependent Features * i960-Dependent:: Intel 80960 Dependent Features @@ -1570,20 +1572,4 @@ Floating Point The H8/300 family has no hardware floating point, but the `.float' directive generates IEEE floating-point numbers for compatibility with other development tools. - - -File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent - -H8/300 Machine Directives -------------------------- - - `as' has only one machine-dependent directive for the H8/300: - -`.h8300h' - Recognize and emit additional instructions for the H8/300H - variant, and also make `.int' emit 32-bit numbers rather than the - usual (16-bit) for the H8/300 family. - - On the H8/300 family (including the H8/300H) `.word' directives -generate 16-bit numbers. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info-4 binutils-2.9.1.0.23/gas/doc/as.info-4 --- binutils-2.9.1.0.22b/gas/doc/as.info-4 Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info-4 Wed Mar 31 09:51:20 1999 @@ -24,6 +24,22 @@ manual into another language, under the versions.  +File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent + +H8/300 Machine Directives +------------------------- + + `as' has only one machine-dependent directive for the H8/300: + +`.h8300h' + Recognize and emit additional instructions for the H8/300H + variant, and also make `.int' emit 32-bit numbers rather than the + usual (16-bit) for the H8/300 family. + + On the H8/300 family (including the H8/300H) `.word' directives +generate 16-bit numbers. + + File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent Opcodes @@ -459,7 +475,7 @@ pseudo-instructions are needed on this f mov[:g] sz ea,rd  -File: as.info, Node: HPPA-Dependent, Next: i386-Dependent, Prev: H8/500-Dependent, Up: Machine Dependencies +File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/500-Dependent, Up: Machine Dependencies HPPA Dependent Features ======================= @@ -728,7 +744,157 @@ Opcodes 09740-90039).  -File: as.info, Node: i386-Dependent, Next: i960-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies +File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies + +ESA/390 Dependent Features +========================== + +* Menu: + +* ESA/390 Notes:: Notes +* ESA/390 Options:: Options +* ESA/390 Syntax:: Syntax +* ESA/390 Floating Point:: Floating Point +* ESA/390 Directives:: ESA/390 Machine Directives +* ESA/390 Opcodes:: Opcodes + + +File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent + +Notes +----- + + As a back end for GNU CC `as' has been tested but should still be +considered experimental. It will not work with HLASM-style assembly +because it supports only a small subset of the HLASM directives. Note +that that only ELF-style binary file formats are supported; none of the +usual MVS/VM/OE/USS object file formats are supported. + + The ESA/390 `as' port generates only a 31-bit relocation; many more +are available in the ELF object file format but are not supported, and +may fail silently. + + +File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent + +Options +------- + + `as' has no machine-dependent command-line options for the ESA/390. + + +File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent + +Syntax +------ + + The opcode/operand syntax follows the ESA/390 Principles of Operation +manual; assembler directives and general syntax are loosely based on the +prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives +are *not* supported for the most part, with the exception of those +described herein. + + A leading dot in front of directives is optional, and teh case of +directives is ignored; thus for example, .using and USING have the same +effect. + + A colon may immediately follow a label definition. This is simply +for compatibility with how most assembly language programmers write +code. + + `#' is the line comment character. + + `;' can be used instead of a newline to separate statements. + + Since `$' has no special meaning, you may use it in symbol names. + + Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, +fp6. By using thesse symbolic names, `as' can detect simple syntax +errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for +r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base +for r3 and rpgt or r.pgt for r4. + + `*' is the current location counter. Unlike `.' it is always +relative to the last USING directive. Note that this means that +expressions cannot use multiplication, as any occurence of `*' will be +interpreted as a location counter. + + All labels are relative to the last USING. Thus, branches to a label +always imply the use of base+displacement. + + Many of the usual forms of address constants / address literals are +supported. Thus, + .using *,r3 + L r15,=A(some_routine) + LM r6,r7,=V(some_longlong_extern) + A r1,=F'12' + AH r0,=H'42' + ME r6,=E'3.1416' + MD r6,=D'3.14159265358979' + O r6,=XL4'cacad0d0' + .ltorg + should all behave as expected: that is, an entry in the literal pool +will be created (or reused if it already exists), and the instruction +operands will be the displacement into the literal pool using the +current base register (as last declared with the `.using' directive). + + +File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent + +Floating Point +-------------- + + The assembler generates only IEEE floating-point numbers. The older +floiating point formats are not supported. + + +File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent + +ESA/390 Assembler Directives +---------------------------- + + `as' for the ESA/390 supports all of the standard ELF/SVR4 assembler +directives that are documented in the main part of this documentation. +Several additional directives are supported in order to implement the +ESA/390 addressing model. The most important of these are `.using' and +`.ltorg' + + These are the additional directives in `as' for the ESA/390: + +`.dc' + A small subset of the usual DC directive is supported. + +`.drop REGNO' + Stop using REGNO as the base register. + +`.ebcdic STRING' + Emit the EBCDIC equivalent of the indicated string. The emitted + string will be null terminated. Note that the directives + `.string' etc. emit ascii strings by default. + +`EQU' + The standard HLASM-style EQU directive is not supported; however, + the standard `as' directive .equ can be used to the same effect. + +`.ltorg' + Dump the literal pool accumulated so far; begin a new literal pool. + +`.using EXPR,REGNO' + Use REGNO as the base register for all subsequent RX, RS, and SS + form instructions. The EXPR will be evaluated to obtain the base + address; usually, EXPR will merely be `*'. + + +File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent + +Opcodes +------- + + For detailed information on the ESA/390 machine instruction set, see +`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). + + +File: as.info, Node: i386-Dependent, Next: i960-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 80386 Dependent Features ======================== @@ -737,14 +903,15 @@ File: as.info, Node: i386-Dependent, N * i386-Options:: Options * i386-Syntax:: AT&T Syntax versus Intel Syntax -* i386-Opcodes:: Opcode Naming +* i386-Mnemonics:: Instruction Naming * i386-Regs:: Register Naming -* i386-prefixes:: Opcode Prefixes +* i386-Prefixes:: Instruction Prefixes * i386-Memory:: Memory References * i386-jumps:: Handling of Jump Instructions * i386-Float:: Floating Point * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations * i386-16bit:: Writing 16-bit Code +* i386-Bugs:: AT&T Syntax bugs * i386-Notes:: Notes  @@ -756,7 +923,7 @@ Options The 80386 has no machine dependent options.  -File: as.info, Node: i386-Syntax, Next: i386-Opcodes, Prev: i386-Options, Up: i386-Dependent +File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Options, Up: i386-Dependent AT&T Syntax versus Intel Syntax ------------------------------- @@ -764,8 +931,8 @@ AT&T Syntax versus Intel Syntax In order to maintain compatibility with the output of `gcc', `as' supports AT&T System V/386 assembler syntax. This is quite different from Intel syntax. We mention these differences because almost all -80386 documents used only Intel syntax. Notable differences between -the two syntaxes are: +80386 documents use Intel syntax. Notable differences between the two +syntaxes are: * AT&T immediate operands are preceded by `$'; Intel immediate operands are undelimited (Intel `push 4' is AT&T `pushl $4'). @@ -777,15 +944,17 @@ the two syntaxes are: * AT&T and Intel syntax use the opposite order for source and destination operands. Intel `add eax, 4' is `addl $4, %eax'. The `source, dest' convention is maintained for compatibility with - previous Unix assemblers. + previous Unix assemblers. Note that instructions with more than + one source operand, such as the `enter' instruction, do *not* have + reversed order. *Note i386-Bugs::. * In AT&T syntax the size of memory operands is determined from the - last character of the opcode name. Opcode suffixes of `b', `w', - and `l' specify byte (8-bit), word (16-bit), and long (32-bit) - memory references. Intel syntax accomplishes this by prefixes - memory operands (*not* the opcodes themselves) with `byte ptr', - `word ptr', and `dword ptr'. Thus, Intel `mov al, byte ptr FOO' - is `movb FOO, %al' in AT&T syntax. + last character of the instruction mnemonic. Mnemonic suffixes of + `b', `w', and `l' specify byte (8-bit), word (16-bit), and long + (32-bit) memory references. Intel syntax accomplishes this by + prefixing memory operands (*not* the instruction mnemonics) with + `byte ptr', `word ptr', and `dword ptr'. Thus, Intel `mov al, + byte ptr FOO' is `movb FOO, %al' in AT&T syntax. * Immediate form long jumps and calls are `lcall/ljmp $SECTION, $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far @@ -798,34 +967,35 @@ the two syntaxes are: sections.  -File: as.info, Node: i386-Opcodes, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent +File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent -Opcode Naming -------------- +Instruction Naming +------------------ - Opcode names are suffixed with one character modifiers which specify -the size of operands. The letters `b', `w', and `l' specify byte, -word, and long operands. If no suffix is specified by an instruction -and it contains no memory operands then `as' tries to fill in the -missing suffix based on the destination register operand (the last one -by convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; -also, `mov $1, %bx' is equivalent to `movw $1, %bx'. Note that this is -incompatible with the AT&T Unix assembler which assumes that a missing -opcode suffix implies long operand size. (This incompatibility does -not affect compiler output since compilers always explicitly specify -the opcode suffix.) + Instruction mnemonics are suffixed with one character modifiers which +specify the size of operands. The letters `b', `w', and `l' specify +byte, word, and long operands. If no suffix is specified by an +instruction then `as' tries to fill in the missing suffix based on the +destination register operand (the last one by convention). Thus, `mov +%ax, %bx' is equivalent to `movw %ax, %bx'; also, `mov $1, %bx' is +equivalent to `movw $1, %bx'. Note that this is incompatible with the +AT&T Unix assembler which assumes that a missing mnemonic suffix +implies long operand size. (This incompatibility does not affect +compiler output since compilers always explicitly specify the mnemonic +suffix.) - Almost all opcodes have the same names in AT&T and Intel format. + Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend *from* and a size to zero extend *to*. This is -accomplished by using two opcode suffixes in AT&T syntax. Base names -for sign extend and zero extend are `movs...' and `movz...' in AT&T -syntax (`movsx' and `movzx' in Intel syntax). The opcode suffixes are -tacked on to this base name, the *from* suffix before the *to* suffix. -Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend *from* -%al *to* %edx." Possible suffixes, thus, are `bl' (from byte to long), -`bw' (from byte to word), and `wl' (from word to long). +accomplished by using two instruction mnemonic suffixes in AT&T syntax. +Base names for sign extend and zero extend are `movs...' and `movz...' +in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction +mnemonic suffixes are tacked on to this base name, the *from* suffix +before the *to* suffix. Thus, `movsbl %al, %edx' is AT&T syntax for +"move sign extend *from* %al *to* %edx." Possible suffixes, thus, are +`bl' (from byte to long), `bw' (from byte to word), and `wl' (from word +to long). The Intel-syntax conversion instructions @@ -844,12 +1014,12 @@ accepts either naming for these instruct but are `call far' and `jump far' in Intel convention.  -File: as.info, Node: i386-Regs, Next: i386-prefixes, Prev: i386-Opcodes, Up: i386-Dependent +File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent Register Naming --------------- - Register operands are always prefixes with `%'. The 80386 registers + Register operands are always prefixed with `%'. The 80386 registers consist of * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', @@ -878,46 +1048,55 @@ consist of `%st(6)', and `%st(7)'.  -File: as.info, Node: i386-prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent +File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent -Opcode Prefixes ---------------- +Instruction Prefixes +-------------------- - Opcode prefixes are used to modify the following opcode. They are -used to repeat string instructions, to provide section overrides, to -perform bus lock operations, and to give operand and address size -(16-bit operands are specified in an instruction by prefixing what would -normally be 32-bit operands with a "operand size" opcode prefix). -Opcode prefixes are usually given as single-line instructions with no -operands, and must directly precede the instruction they act upon. For -example, the `scas' (scan string) instruction is repeated with: - repne - scas + Instruction prefixes are used to modify the following instruction. +They are used to repeat string instructions, to provide section +overrides, to perform bus lock operations, and to change operand and +address sizes. (Most instructions that normally operate on 32-bit +operands will use 16-bit operands if the instruction has an "operand +size" prefix.) Instruction prefixes are best written on the same line +as the instruction they act upon. For example, the `scas' (scan string) +instruction is repeated with: + + repne scas %es:(%edi),%al + + You may also place prefixes on the lines immediately preceding the +instruction, but this circumvents checks that `as' does with prefixes, +and will not work with all prefixes. - Here is a list of opcode prefixes: + Here is a list of instruction prefixes: * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. These are automatically added by specifying using the SECTION:MEMORY-OPERAND form for memory references. * Operand/Address size prefixes `data16' and `addr16' change 32-bit - operands/addresses into 16-bit operands/addresses. Note that - 16-bit addressing modes (i.e. 8086 and 80286 addressing modes) are - not supported (yet). + operands/addresses into 16-bit operands/addresses, while `data32' + and `addr32' change 16-bit ones (in a `.code16' section) into + 32-bit operands/addresses. These prefixes *must* appear on the + same line of code as the instruction they modify. For example, in + a 16-bit `.code16' section, you might write: + + addr32 jmpl *(%ebx) * The bus lock prefix `lock' inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details). - * The wait for coprocessor prefix `wait' waits for the coprocessor - to complete the current instruction. This should never be needed - for the 80386/80387 combination. + * The wait for coprocessor prefix `wait' waits for the coprocessor to + complete the current instruction. This should never be needed for + the 80386/80387 combination. * The `rep', `repe', and `repne' prefixes are added to string - instructions to make them repeat `%ecx' times. + instructions to make them repeat `%ecx' times (`%cx' times if the + current address size is 16-bits).  -File: as.info, Node: i386-Memory, Next: i386-jumps, Prev: i386-prefixes, Up: i386-Dependent +File: as.info, Node: i386-Memory, Next: i386-jumps, Prev: i386-Prefixes, Up: i386-Dependent Memory References ----------------- @@ -936,7 +1115,7 @@ DISP is the optional displacement, and S no SCALE is specified, SCALE is taken to be 1. SECTION specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register -defaults). Note that section overrides in AT&T syntax *must* have be +defaults). Note that section overrides in AT&T syntax *must* be preceded by a `%'. If you specify a section override which coincides with the default section register, `as' does *not* output any section register override prefixes to assemble the given instruction. Thus, @@ -967,9 +1146,9 @@ AT&T: `%gs:foo'; Intel `gs:foo' prefixed with `*'. If no `*' is specified, `as' always chooses PC relative addressing for jump/call labels. - Any instruction that has a memory operand *must* specify its size -(byte, word, or long) with an opcode suffix (`b', `w', or `l', -respectively). + Any instruction that has a memory operand, but no register operand, +*must* specify its size (byte, word, or long) with an instruction +mnemonic suffix (`b', `w', or `l', respectively).  File: as.info, Node: i386-jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent @@ -981,9 +1160,10 @@ Handling of Jump Instructions displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long (32-bit) displacement is used. We do not support -word (16-bit) displacement jumps (i.e. prefixing the jump instruction -with the `addr16' opcode prefix), since the 80386 insists upon masking -`%eip' to 16 bits after the word displacement is added. +word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump +instruction with the `data16' instruction prefix), since the 80386 +insists upon masking `%eip' to 16 bits after the word displacement is +added. Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' and `loopne' instructions only come in byte displacements, so that if @@ -1006,26 +1186,30 @@ Floating Point (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each -supported type has an opcode suffix and a constructor associated with -it. Opcode suffixes specify operand's data types. Constructors build -these data types into memory. +supported type has an instruction mnemonic suffix and a constructor +associated with it. Instruction mnemonic suffixes specify the operand's +data type. Constructors build these data types into memory. * Floating point constructors are `.float' or `.single', `.double', and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond - to opcode suffixes `s', `l', and `t'. `t' stands for temporary - real, and that the 80387 only supports this format via the `fldt' - (load temporary real to stack top) and `fstpt' (store temporary - real and pop stack) instructions. + to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for + 80-bit (ten byte) real. The 80387 only supports this format via + the `fldt' (load 80-bit real to stack top) and `fstpt' (store + 80-bit real and pop stack) instructions. * Integer constructors are `.word', `.long' or `.int', and `.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding - opcode suffixes are `s' (single), `l' (long), and `q' (quad). As - with the temporary real format the 64-bit `q' format is only - present in the `fildq' (load quad integer to stack top) and - `fistpq' (store quad integer and pop stack) instructions. - - Register to register operations do not require opcode suffixes, so -that `fst %st, %st(1)' is equivalent to `fstl %st, %st(1)'. + instruction mnemonic suffixes are `s' (single), `l' (long), and + `q' (quad). As with the 80-bit real format, the 64-bit `q' format + is only present in the `fildq' (load quad integer to stack top) + and `fistpq' (store quad integer and pop stack) instructions. + + Register to register operations should not use instruction mnemonic +suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as +if you wrote `fst %st, %st(1)', since all register to register +operations use 80-bit floating point operands. (Contrast this with +`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating +point format, then stores the result in the 4 byte location `mem')  File: as.info, Node: i386-SIMD, Next: i386-16bit, Prev: i386-Float, Up: i386-Dependent @@ -1033,75 +1217,80 @@ File: as.info, Node: i386-SIMD, Next: Intel's MMX and AMD's 3DNow! SIMD Operations -------------------------------------------- - GAS supports Intel's MMX instruction set (SIMD instructions for + `as' supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and -probably others. It also supports AMD's 3DNow! instruction set (SIMD +probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future. - Currently, GAS does not support Intel's floating point SIMD, Katmai + Currently, `as' does not support Intel's floating point SIMD, Katmai (KNI). - None of these instructions are used by gcc, though there is no -reason they shouldn't be aside from the lack of expressiveness of SIMD -operations in C. - - The 8 64-bit MMX operands, shared by 3DNow! are called `%mm0', -`%mm1', ... `%mm7', and conceptually contain from eight 8-bit values to -two 32-bit float values. The MMX registers cannot be used at the same + The eight 64-bit MMX operands, also used by 3DNow!, are called +`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four +16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit +floating point values. The MMX registers cannot be used at the same time as the floating point stack. See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.  -File: as.info, Node: i386-16bit, Next: i386-Notes, Prev: i386-SIMD, Up: i386-Dependent +File: as.info, Node: i386-16bit, Next: i386-Bugs, Prev: i386-SIMD, Up: i386-Dependent Writing 16-bit Code ------------------- - While GAS normally writes only "pure" 32-bit i386 code, it has -limited support for writing code to run in real mode or in 16-bit -protected mode code segments. To do this, insert a `.code16' directive -before the assembly language instructions to be run in 16-bit mode. -You can switch GAS back to writing normal 32-bit code with the -`.code32' directive. - - GAS understands exactly the same assembly language syntax in 16-bit -mode as in 32-bit mode. The function of any given instruction is -exactly the same regardless of mode, as long as the resulting object -code is executed in the mode for which GAS wrote it. So, for example, -the `ret' mnemonic produces a 32-bit return instruction regardless of -whether it is to be run in 16-bit or 32-bit mode. (If GAS is in 16-bit -mode, it will add an operand size prefix to the instruction to force it -to be a 32-bit return.) - - This means, for one thing, that you can use GNU CC to write code to -be run in real mode or 16-bit protected mode. Just insert the statement -`asm(".code16");' at the beginning of your C source file, and while GNU -CC will still be generating 32-bit code, GAS will automatically add all -the necessary size prefixes to make that code run in 16-bit mode. Of -course, since GNU CC only writes small-model code (it doesn't know how -to attach segment selectors to pointers like native x86 compilers do), -any 16-bit code you write with GNU CC will essentially be limited to a -64K address space. Also, there will be a code size and performance -penalty due to all the extra address and operand size prefixes GAS has -to add to the instructions. - - Note that placing GAS in 16-bit mode does not mean that the resulting -code will necessarily run on a 16-bit pre-80386 processor. To write -code that runs on such a processor, you would have to refrain from using -*any* 32-bit constructs which require GAS to output address or operand -size prefixes. At the moment this would be rather difficult, because -GAS currently supports *only* 32-bit addressing modes: when writing -16-bit code, it *always* outputs address size prefixes for any -instruction that uses a non-register addressing mode. So you can write -code that runs on 16-bit processors, but only if that code never -references memory. + While `as' normally writes only "pure" 32-bit i386 code, it also +supports writing code to run in real mode or in 16-bit protected mode +code segments. To do this, put a `.code16' directive before the +assembly language instructions to be run in 16-bit mode. You can +switch `as' back to writing normal 32-bit code with the `.code32' +directive. + + The code which `as' generates in 16-bit mode will not necessarily +run on a 16-bit pre-80386 processor. To write code that runs on such a +processor, you must refrain from using *any* 32-bit constructs which +require `as' to output address or operand size prefixes. + + Note that writing 16-bit code instructions by explicitly specifying a +prefix or an instruction mnemonic suffix within a 32-bit code section +generates different machine instructions than those generated for a +16-bit code segment. In a 32-bit code section, the following code +generates the machine opcode bytes `66 6a 04', which pushes the value +`4' onto the stack, decrementing `%esp' by 2. + + pushw $4 + + The same code in a 16-bit code section would generate the machine +opcode bytes `6a 04' (ie. without the operand size prefix), which is +correct since the processor default operand size is assumed to be 16 +bits in a 16-bit code section. + + +File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-16bit, Up: i386-Dependent + +AT&T Syntax bugs +---------------- + + The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we're stuck +with it. + + For example + + fsub %st,%st(3) + +results in `%st(3)' being updated to `%st - %st(3)' rather than the +expected `%st(3) - %st'. This happens with all the non-commutative +arithmetic floating point operations with two register operands where +the source register is `%st' and the destination register is `%st(i)'.  -File: as.info, Node: i386-Notes, Prev: i386-16bit, Up: i386-Dependent +File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent Notes ----- @@ -1119,151 +1308,4 @@ an immediate mode expression and the sec This is just a shorthand, so that, multiplying `%eax' by 69, for example, can be done with `imul $69, %eax' rather than `imul $69, %eax, %eax'. - - -File: as.info, Node: i960-Dependent, Next: M68K-Dependent, Prev: i386-Dependent, Up: Machine Dependencies - -Intel 80960 Dependent Features -============================== - -* Menu: - -* Options-i960:: i960 Command-line Options -* Floating Point-i960:: Floating Point -* Directives-i960:: i960 Machine Directives -* Opcodes for i960:: i960 Opcodes - - -File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent - -i960 Command-line Options -------------------------- - -`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' - Select the 80960 architecture. Instructions or features not - supported by the selected architecture cause fatal errors. - - `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. - Synonyms are provided for compatibility with other tools. - - If you do not specify any of these options, `as' generates code - for any instruction or feature that is supported by *some* version - of the 960 (even if this means mixing architectures!). In - principle, `as' attempts to deduce the minimal sufficient - processor type if none is specified; depending on the object code - format, the processor type may be recorded in the object file. If - it is critical that the `as' output match a specific architecture, - specify that architecture explicitly. - -`-b' - Add code to collect information about conditional branches taken, - for later optimization using branch prediction bits. (The - conditional branch instructions have branch prediction bits in the - CA, CB, and CC architectures.) If BR represents a conditional - branch instruction, the following represents the code generated by - the assembler when `-b' is specified: - - call INCREMENT ROUTINE - .word 0 # pre-counter - Label: BR - call INCREMENT ROUTINE - .word 0 # post-counter - - The counter following a branch records the number of times that - branch was *not* taken; the differenc between the two counters is - the number of times the branch *was* taken. - - A table of every such `Label' is also generated, so that the - external postprocessor `gbr960' (supplied by Intel) can locate all - the counters. This table is always labelled `__BRANCH_TABLE__'; - this is a local symbol to permit collecting statistics for many - separate object files. The table is word aligned, and begins with - a two-word header. The first word, initialized to 0, is used in - maintaining linked lists of branch tables. The second word is a - count of the number of entries in the table, which follow - immediately: each is a word, pointing to one of the labels - illustrated above. - - +------------+------------+------------+ ... +------------+ - | | | | | | - | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | - | | | | | | - +------------+------------+------------+ ... +------------+ - - __BRANCH_TABLE__ layout - - The first word of the header is used to locate multiple branch - tables, since each object file may contain one. Normally the links - are maintained with a call to an initialization routine, placed at - the beginning of each function in the file. The GNU C compiler - generates these calls automatically when you give it a `-b' option. - For further details, see the documentation of `gbr960'. - -`-no-relax' - Normally, Compare-and-Branch instructions with targets that require - displacements greater than 13 bits (or that have external targets) - are replaced with the corresponding compare (or `chkbit') and - branch instructions. You can use the `-no-relax' option to - specify that `as' should generate errors instead, if the target - displacement is larger than 13 bits. - - This option does not affect the Compare-and-Jump instructions; the - code emitted for them is *always* adjusted when necessary - (depending on displacement size), regardless of whether you use - `-no-relax'. - - -File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent - -Floating Point --------------- - - `as' generates IEEE floating-point numbers for the directives -`.float', `.double', `.extended', and `.single'. - - -File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent - -i960 Machine Directives ------------------------ - -`.bss SYMBOL, LENGTH, ALIGN' - Reserve LENGTH bytes in the bss section for a local SYMBOL, - aligned to the power of two specified by ALIGN. LENGTH and ALIGN - must be positive absolute expressions. This directive differs - from `.lcomm' only in that it permits you to specify an alignment. - *Note `.lcomm': Lcomm. - -`.extended FLONUMS' - `.extended' expects zero or more flonums, separated by commas; for - each flonum, `.extended' emits an IEEE extended-format (80-bit) - floating-point number. - -`.leafproc CALL-LAB, BAL-LAB' - You can use the `.leafproc' directive in conjunction with the - optimized `callj' instruction to enable faster calls of leaf - procedures. If a procedure is known to call no other procedures, - you may define an entry point that skips procedure prolog code - (and that does not depend on system-supplied saved context), and - declare it as the BAL-LAB using `.leafproc'. If the procedure - also has an entry point that goes through the normal prolog, you - can specify that entry point as CALL-LAB. - - A `.leafproc' declaration is meant for use in conjunction with the - optimized call instruction `callj'; the directive records the data - needed later to choose between converting the `callj' into a `bal' - or a `call'. - - CALL-LAB is optional; if only one argument is present, or if the - two arguments are identical, the single argument is assumed to be - the `bal' entry point. - -`.sysproc NAME, INDEX' - The `.sysproc' directive defines a name for a system procedure. - After you define it using `.sysproc', you can use NAME to refer to - the system procedure identified by INDEX when calling procedures - with the optimized call instruction `callj'. - - Both arguments are required; INDEX must be between 0 and 31 - (inclusive). diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info-5 binutils-2.9.1.0.23/gas/doc/as.info-5 --- binutils-2.9.1.0.22b/gas/doc/as.info-5 Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info-5 Wed Mar 31 09:51:20 1999 @@ -24,6 +24,153 @@ manual into another language, under the versions.  +File: as.info, Node: i960-Dependent, Next: M68K-Dependent, Prev: i386-Dependent, Up: Machine Dependencies + +Intel 80960 Dependent Features +============================== + +* Menu: + +* Options-i960:: i960 Command-line Options +* Floating Point-i960:: Floating Point +* Directives-i960:: i960 Machine Directives +* Opcodes for i960:: i960 Opcodes + + +File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent + +i960 Command-line Options +------------------------- + +`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' + Select the 80960 architecture. Instructions or features not + supported by the selected architecture cause fatal errors. + + `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. + Synonyms are provided for compatibility with other tools. + + If you do not specify any of these options, `as' generates code + for any instruction or feature that is supported by *some* version + of the 960 (even if this means mixing architectures!). In + principle, `as' attempts to deduce the minimal sufficient + processor type if none is specified; depending on the object code + format, the processor type may be recorded in the object file. If + it is critical that the `as' output match a specific architecture, + specify that architecture explicitly. + +`-b' + Add code to collect information about conditional branches taken, + for later optimization using branch prediction bits. (The + conditional branch instructions have branch prediction bits in the + CA, CB, and CC architectures.) If BR represents a conditional + branch instruction, the following represents the code generated by + the assembler when `-b' is specified: + + call INCREMENT ROUTINE + .word 0 # pre-counter + Label: BR + call INCREMENT ROUTINE + .word 0 # post-counter + + The counter following a branch records the number of times that + branch was *not* taken; the differenc between the two counters is + the number of times the branch *was* taken. + + A table of every such `Label' is also generated, so that the + external postprocessor `gbr960' (supplied by Intel) can locate all + the counters. This table is always labelled `__BRANCH_TABLE__'; + this is a local symbol to permit collecting statistics for many + separate object files. The table is word aligned, and begins with + a two-word header. The first word, initialized to 0, is used in + maintaining linked lists of branch tables. The second word is a + count of the number of entries in the table, which follow + immediately: each is a word, pointing to one of the labels + illustrated above. + + +------------+------------+------------+ ... +------------+ + | | | | | | + | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | + | | | | | | + +------------+------------+------------+ ... +------------+ + + __BRANCH_TABLE__ layout + + The first word of the header is used to locate multiple branch + tables, since each object file may contain one. Normally the links + are maintained with a call to an initialization routine, placed at + the beginning of each function in the file. The GNU C compiler + generates these calls automatically when you give it a `-b' option. + For further details, see the documentation of `gbr960'. + +`-no-relax' + Normally, Compare-and-Branch instructions with targets that require + displacements greater than 13 bits (or that have external targets) + are replaced with the corresponding compare (or `chkbit') and + branch instructions. You can use the `-no-relax' option to + specify that `as' should generate errors instead, if the target + displacement is larger than 13 bits. + + This option does not affect the Compare-and-Jump instructions; the + code emitted for them is *always* adjusted when necessary + (depending on displacement size), regardless of whether you use + `-no-relax'. + + +File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent + +Floating Point +-------------- + + `as' generates IEEE floating-point numbers for the directives +`.float', `.double', `.extended', and `.single'. + + +File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent + +i960 Machine Directives +----------------------- + +`.bss SYMBOL, LENGTH, ALIGN' + Reserve LENGTH bytes in the bss section for a local SYMBOL, + aligned to the power of two specified by ALIGN. LENGTH and ALIGN + must be positive absolute expressions. This directive differs + from `.lcomm' only in that it permits you to specify an alignment. + *Note `.lcomm': Lcomm. + +`.extended FLONUMS' + `.extended' expects zero or more flonums, separated by commas; for + each flonum, `.extended' emits an IEEE extended-format (80-bit) + floating-point number. + +`.leafproc CALL-LAB, BAL-LAB' + You can use the `.leafproc' directive in conjunction with the + optimized `callj' instruction to enable faster calls of leaf + procedures. If a procedure is known to call no other procedures, + you may define an entry point that skips procedure prolog code + (and that does not depend on system-supplied saved context), and + declare it as the BAL-LAB using `.leafproc'. If the procedure + also has an entry point that goes through the normal prolog, you + can specify that entry point as CALL-LAB. + + A `.leafproc' declaration is meant for use in conjunction with the + optimized call instruction `callj'; the directive records the data + needed later to choose between converting the `callj' into a `bal' + or a `call'. + + CALL-LAB is optional; if only one argument is present, or if the + two arguments are identical, the single argument is assumed to be + the `bal' entry point. + +`.sysproc NAME, INDEX' + The `.sysproc' directive defines a name for a system procedure. + After you define it using `.sysproc', you can use NAME to refer to + the system procedure identified by INDEX when calling procedures + with the optimized call instruction `callj'. + + Both arguments are required; INDEX must be between 0 and 31 + (inclusive). + + File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent i960 Opcodes @@ -1241,63 +1388,4 @@ Addressing Modes `#XX' Immediate data XX. - - -File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent - -Assembler Directives for the Z8000 ----------------------------------- - - The Z8000 port of as includes these additional assembler directives, -for compatibility with other Z8000 assemblers. As shown, these do not -begin with `.' (unlike the ordinary as directives). - -`segm' - Generates code for the segmented Z8001. - -`unsegm' - Generates code for the unsegmented Z8002. - -`name' - Synonym for `.file' - -`global' - Synonym for `.global' - -`wval' - Synonym for `.word' - -`lval' - Synonym for `.long' - -`bval' - Synonym for `.byte' - -`sval' - Assemble a string. `sval' expects one string literal, delimited by - single quotes. It assembles each byte of the string into - consecutive addresses. You can use the escape sequence `%XX' - (where XX represents a two-digit hexadecimal number) to represent - the character whose ASCII value is XX. Use this feature to - describe single quote and other characters that may not appear in - string literals as themselves. For example, the C statement - `char *a = "he said \"it's 50% off\"";' is represented in Z8000 - assembly language (shown with the assembler output in hex at the - left) as - - 68652073 sval 'he said %22it%27s 50%25 off%22%00' - 61696420 - 22697427 - 73203530 - 25206F66 - 662200 - -`rsect' - synonym for `.section' - -`block' - synonym for `.space' - -`even' - special case of `.align'; aligns output to even byte boundary. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info-6 binutils-2.9.1.0.23/gas/doc/as.info-6 --- binutils-2.9.1.0.22b/gas/doc/as.info-6 Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info-6 Wed Mar 31 09:51:20 1999 @@ -24,6 +24,65 @@ manual into another language, under the versions.  +File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent + +Assembler Directives for the Z8000 +---------------------------------- + + The Z8000 port of as includes these additional assembler directives, +for compatibility with other Z8000 assemblers. As shown, these do not +begin with `.' (unlike the ordinary as directives). + +`segm' + Generates code for the segmented Z8001. + +`unsegm' + Generates code for the unsegmented Z8002. + +`name' + Synonym for `.file' + +`global' + Synonym for `.global' + +`wval' + Synonym for `.word' + +`lval' + Synonym for `.long' + +`bval' + Synonym for `.byte' + +`sval' + Assemble a string. `sval' expects one string literal, delimited by + single quotes. It assembles each byte of the string into + consecutive addresses. You can use the escape sequence `%XX' + (where XX represents a two-digit hexadecimal number) to represent + the character whose ASCII value is XX. Use this feature to + describe single quote and other characters that may not appear in + string literals as themselves. For example, the C statement + `char *a = "he said \"it's 50% off\"";' is represented in Z8000 + assembly language (shown with the assembler output in hex at the + left) as + + 68652073 sval 'he said %22it%27s 50%25 off%22%00' + 61696420 + 22697427 + 73203530 + 25206F66 + 662200 + +`rsect' + synonym for `.section' + +`block' + synonym for `.space' + +`even' + special case of `.align'; aligns output to even byte boundary. + + File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent Opcodes @@ -1033,6 +1092,9 @@ Cygnus Support (original, incomplete imp Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, and some initial 64-bit support). + + Linas Vepstas added GAS support for the ESA/390 "Instruction 370" +architecture. Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.info-7 binutils-2.9.1.0.23/gas/doc/as.info-7 --- binutils-2.9.1.0.22b/gas/doc/as.info-7 Fri Feb 5 13:58:18 1999 +++ binutils-2.9.1.0.23/gas/doc/as.info-7 Wed Mar 31 09:51:20 1999 @@ -225,10 +225,10 @@ Index * bug criteria: Bug Criteria. * bug reports: Bug Reporting. * bugs in assembler: Reporting Bugs. -* bus lock prefixes, i386: i386-prefixes. +* bus lock prefixes, i386: i386-Prefixes. * bval: Z8000 Directives. * byte directive: Byte. -* call instructions, i386: i386-Opcodes. +* call instructions, i386: i386-Mnemonics. * callj, i960 pseudo-opcode: callj-i960. * carriage return (\r): Strings. * character constants: Characters. @@ -270,8 +270,8 @@ Index * constants, number: Numbers. * constants, string: Strings. * continuing statements: Statements. -* conversion instructions, i386: i386-Opcodes. -* coprocessor wait, i386: i386-prefixes. +* conversion instructions, i386: i386-Mnemonics. +* coprocessor wait, i386: i386-Prefixes. * cpu directive, SPARC: ARC-Directives. * cputype directive, AMD 29K: AMD29K Directives. * crash of assembler: Bug Criteria. @@ -341,6 +341,10 @@ Index * error messsages: Errors. * error on valid input: Bug Criteria. * errors, continuing after: Z. +* ESA/390 floating point (IEEE): ESA/390 Floating Point. +* ESA/390 support: ESA/390-Dependent. +* ESA/390 Syntax: ESA/390 Options. +* ESA/390-only directives: ESA/390 Directives. * escape codes, character: Strings. * even: Z8000 Directives. * even directive, M680x0: M68K-Directives. @@ -379,6 +383,7 @@ Index * floating point, ARC (IEEE): ARC-Float. * floating point, ARM (IEEE): ARM Floating Point. * floating point, D10V: D10V-Float. +* floating point, ESA/390 (IEEE): ESA/390 Floating Point. * floating point, H8/300 (IEEE): H8/300 Floating Point. * floating point, H8/500 (IEEE): H8/500 Floating Point. * floating point, HPPA (IEEE): HPPA Floating Point. @@ -433,17 +438,18 @@ Index * HPPA Syntax: HPPA Options. * HPPA-only directives: HPPA Directives. * hword directive: hword. +* i370 support: ESA/390-Dependent. * i386 16-bit code: i386-16bit. -* i386 conversion instructions: i386-Opcodes. +* i386 conversion instructions: i386-Mnemonics. * i386 floating point: i386-Float. * i386 immediate operands: i386-Syntax. +* i386 instruction naming: i386-Mnemonics. +* i386 instruction prefixes: i386-Prefixes. * i386 jump optimization: i386-jumps. * i386 jump, call, return: i386-Syntax. * i386 jump/call operands: i386-Syntax. * i386 memory references: i386-Memory. * i386 mul, imul instructions: i386-Notes. -* i386 opcode naming: i386-Opcodes. -* i386 opcode prefixes: i386-prefixes. * i386 options (none): i386-Options. * i386 register operands: i386-Syntax. * i386 registers: i386-Regs. @@ -478,9 +484,11 @@ Index * include directive search path: I. * indirect character, VAX: VAX-operands. * infix operators: Infix Ops. -* inhibiting interrupts, i386: i386-prefixes. +* inhibiting interrupts, i386: i386-Prefixes. * input: Input Files. * input file linenumbers: Input Files. +* instruction naming, i386: i386-Mnemonics. +* instruction prefixes, i386: i386-Prefixes. * instruction set, M680x0: M68K-opcodes. * instruction summary, D10V: D10V-Opcodes. * instruction summary, H8/300: H8/300 Opcodes. @@ -509,7 +517,7 @@ Index * irp directive: Irp. * irpc directive: Irpc. * joining text and data sections: R. -* jump instructions, i386: i386-Opcodes. +* jump instructions, i386: i386-Mnemonics. * jump optimization, i386: i386-jumps. * jump/call operands, i386: i386-Syntax. * label (:): Statements. @@ -619,6 +627,7 @@ Index * MIPS processor: MIPS-Dependent. * MIT: M68K-Syntax. * MMX, i386: i386-SIMD. +* mnemonic suffixes, i386: i386-Syntax. * mnemonics for opcodes, VAX: VAX-opcodes. * mnemonics, D10V: D10V-Opcodes. * mnemonics, H8/300: H8/300 Opcodes. @@ -656,9 +665,6 @@ Index * octal integers: Integers. * offset directive, V850: V850 Directives. * opcode mnemonics, VAX: VAX-opcodes. -* opcode naming, i386: i386-Opcodes. -* opcode prefixes, i386: i386-prefixes. -* opcode suffixes, i386: i386-Syntax. * opcode summary, D10V: D10V-Opcodes. * opcode summary, H8/300: H8/300 Opcodes. * opcode summary, H8/500: H8/500 Opcodes. @@ -710,7 +716,7 @@ Index * precedence of operators: Infix Ops. * precision, floating point: Flonums. * prefix operators: Prefix Ops. -* prefixes, i386: i386-prefixes. +* prefixes, i386: i386-Prefixes. * preprocessing: Preprocessing. * preprocessing, turning on and off: Preprocessing. * primary attributes, COFF symbols: COFF Symbols. @@ -738,7 +744,7 @@ Index * registers, Z8000: Z8000-Regs. * relocation: Sections. * relocation example: Ld Sections. -* repeat prefixes, i386: i386-prefixes. +* repeat prefixes, i386: i386-Prefixes. * reporting bugs in assembler: Reporting Bugs. * rept directive: Rept. * reserve directive, SPARC: Sparc-Directives. @@ -751,7 +757,7 @@ Index * sect directive, AMD 29K: AMD29K Directives. * section directive: Section. * section directive, V850: V850 Directives. -* section override prefixes, i386: i386-prefixes. +* section override prefixes, i386: i386-Prefixes. * section-relative addressing: Secs Background. * sections: Sections. * sections in messages, internal: As Sections. @@ -779,7 +785,7 @@ Index * size directive: Size. * size modifiers, D10V: D10V-Size. * size modifiers, M680x0: M68K-Syntax. -* size prefixes, i386: i386-prefixes. +* size prefixes, i386: i386-Prefixes. * size suffixes, H8/300: H8/300 Opcodes. * sizes operands, i386: i386-Syntax. * skip directive: Skip. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/as.texinfo binutils-2.9.1.0.23/gas/doc/as.texinfo --- binutils-2.9.1.0.22b/gas/doc/as.texinfo Sat Apr 4 08:54:48 1998 +++ binutils-2.9.1.0.23/gas/doc/as.texinfo Wed Mar 31 09:34:16 1999 @@ -4679,6 +4679,9 @@ subject, see the hardware manufacturer's @ifset HPPA * HPPA-Dependent:: HPPA Dependent Features @end ifset +@ifset I370 +* ESA/390-Dependent:: IBM ESA/390 Dependent Features +@end ifset @ifset I80386 * i386-Dependent:: Intel 80386 Dependent Features @end ifset @@ -4840,6 +4843,10 @@ family. @include c-hppa.texi @end ifset +@ifset I370 +@include c-i370.texi +@end ifset + @ifset I80386 @include c-i386.texi @end ifset @@ -5166,6 +5173,8 @@ Support (original, incomplete implementa Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, and some initial 64-bit support). + +Linas Vepstas added GAS support for the ESA/390 "Instruction 370" architecture. Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha. diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/c-i370.texi binutils-2.9.1.0.23/gas/doc/c-i370.texi --- binutils-2.9.1.0.22b/gas/doc/c-i370.texi Wed Dec 31 16:00:00 1969 +++ binutils-2.9.1.0.23/gas/doc/c-i370.texi Wed Mar 31 09:34:16 1999 @@ -0,0 +1,147 @@ +@c Copyright (C) 1999 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node ESA/390-Dependent +@chapter ESA/390 Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter ESA/390 Dependent Features +@end ifclear + +@cindex i370 support +@cindex ESA/390 support + +@menu +* ESA/390 Notes:: Notes +* ESA/390 Options:: Options +* ESA/390 Syntax:: Syntax +* ESA/390 Floating Point:: Floating Point +* ESA/390 Directives:: ESA/390 Machine Directives +* ESA/390 Opcodes:: Opcodes +@end menu + +@node ESA/390 Notes +@section Notes +As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been tested +but should still be considered experimental. It will not work with +HLASM-style assembly because it supports only a small subset of the +HLASM directives. Note that that only ELF-style binary file formats are +supported; none of the usual MVS/VM/OE/USS object file formats are +supported. + +The ESA/390 @code{@value{AS}} port generates only a 31-bit relocation; +many more are available in the ELF object file format but are not +supported, and may fail silently. + +@node ESA/390 Options +@section Options +@code{@value{AS}} has no machine-dependent command-line options for the ESA/390. + +@cindex ESA/390 Syntax +@node ESA/390 Syntax +@section Syntax +The opcode/operand syntax follows the ESA/390 Principles of Operation +manual; assembler directives and general syntax are loosely based on the +prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives +are @emph{not} supported for the most part, with the exception of those +described herein. + +A leading dot in front of directives is optional, and teh case of +directives is ignored; thus for example, .using and USING have the same +effect. + +A colon may immediately follow a label definition. This is +simply for compatibility with how most assembly language programmers +write code. + +@samp{#} is the line comment character. + +@samp{;} can be used instead of a newline to separate statements. + +Since @samp{$} has no special meaning, you may use it in symbol names. + +Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. +By using thesse symbolic names, @code{@value{AS}} can detect simple +syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca +for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base +for r3 and rpgt or r.pgt for r4. + +@samp{*} is the current location counter. Unlike @samp{.} it is always +relative to the last USING directive. Note that this means that +expressions cannot use multiplication, as any occurence of @samp{*} +will be interpreted as a location counter. + +All labels are relative to the last USING. Thus, branches to a label +always imply the use of base+displacement. + +Many of the usual forms of address constants / address literals +are supported. Thus, +@example + .using *,r3 + L r15,=A(some_routine) + LM r6,r7,=V(some_longlong_extern) + A r1,=F'12' + AH r0,=H'42' + ME r6,=E'3.1416' + MD r6,=D'3.14159265358979' + O r6,=XL4'cacad0d0' + .ltorg +@end example +should all behave as expected: that is, an entry in the literal +pool will be created (or reused if it already exists), and the +instruction operands will be the displacement into the literal pool +using the current base register (as last declared with the @code{.using} +directive). + +@node ESA/390 Floating Point +@section Floating Point +@cindex floating point, ESA/390 (@sc{ieee}) +@cindex ESA/390 floating point (@sc{ieee}) +The assembler generates only @sc{ieee} floating-point numbers. The older +floiating point formats are not supported. + + +@node ESA/390 Directives +@section ESA/390 Assembler Directives + +@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4 +assembler directives that are documented in the main part of this +documentation. Several additional directives are supported in order +to implement the ESA/390 addressing model. The most important of these +are @code{.using} and @code{.ltorg} + +@cindex ESA/390-only directives +These are the additional directives in @code{@value{AS}} for the ESA/390: + +@table @code +@item .dc +A small subset of the usual DC directive is supported. + +@item .drop @var{regno} +Stop using @var{regno} as the base register. + +@item .ebcdic @var{string} +Emit the EBCDIC equivalent of the indicated string. The emitted string +will be null terminated. Note that the directives @code{.string} etc. emit +ascii strings by default. + +@item EQU +The standard HLASM-style EQU directive is not supported; however, the +standard @code{@value{AS}} directive .equ can be used to the same effect. + +@item .ltorg +Dump the literal pool accumulated so far; begin a new literal pool. + +@item .using @var{expr},@var{regno} +Use @var{regno} as the base register for all subsequent RX, RS, and SS form +instructions. The @var{expr} will be evaluated to obtain the base address; +usually, @var{expr} will merely be @samp{*}. +@end table + +@node ESA/390 Opcodes +@section Opcodes +For detailed information on the ESA/390 machine instruction set, see +@cite{ESA/390 Principles of Operation} (IBM Publication Number DZ9AR004). diff --new-file -upr binutils-2.9.1.0.22b/gas/doc/c-i386.texi binutils-2.9.1.0.23/gas/doc/c-i386.texi --- binutils-2.9.1.0.22b/gas/doc/c-i386.texi Thu Oct 8 16:10:22 1998 +++ binutils-2.9.1.0.23/gas/doc/c-i386.texi Wed Mar 31 09:34:16 1999 @@ -1,4 +1,4 @@ -@c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc. +@c Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -16,14 +16,15 @@ @menu * i386-Options:: Options * i386-Syntax:: AT&T Syntax versus Intel Syntax -* i386-Opcodes:: Opcode Naming +* i386-Mnemonics:: Instruction Naming * i386-Regs:: Register Naming -* i386-prefixes:: Opcode Prefixes +* i386-Prefixes:: Instruction Prefixes * i386-Memory:: Memory References * i386-jumps:: Handling of Jump Instructions * i386-Float:: Floating Point * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations * i386-16bit:: Writing 16-bit Code +* i386-Bugs:: AT&T Syntax bugs * i386-Notes:: Notes @end menu @@ -42,7 +43,7 @@ The 80386 has no machine dependent optio In order to maintain compatibility with the output of @code{@value{GCC}}, @code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite different from Intel syntax. We mention these differences because -almost all 80386 documents used only Intel syntax. Notable differences +almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are: @cindex immediate operands, i386 @@ -66,19 +67,21 @@ operands are prefixed by @samp{*}; they AT&T and Intel syntax use the opposite order for source and destination operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The @samp{source, dest} convention is maintained for compatibility with -previous Unix assemblers. +previous Unix assemblers. Note that instructions with more than one +source operand, such as the @samp{enter} instruction, do @emph{not} have +reversed order. @ref{i386-Bugs}. -@cindex opcode suffixes, i386 +@cindex mnemonic suffixes, i386 @cindex sizes operands, i386 @cindex i386 size suffixes @item In AT&T syntax the size of memory operands is determined from the last -character of the opcode name. Opcode suffixes of @samp{b}, @samp{w}, -and @samp{l} specify byte (8-bit), word (16-bit), and long (32-bit) -memory references. Intel syntax accomplishes this by prefixes memory -operands (@emph{not} the opcodes themselves) with @samp{byte ptr}, -@samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, byte -ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. +character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, +@samp{w}, and @samp{l} specify byte (8-bit), word (16-bit), and long +(32-bit) memory references. Intel syntax accomplishes this by prefixing +memory operands (@emph{not} the instruction mnemonics) with @samp{byte +ptr}, @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, +byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. @cindex return instructions, i386 @cindex i386 jump, call, return @@ -98,32 +101,33 @@ The AT&T assembler does not provide supp programs. Unix style systems expect all programs to be single sections. @end itemize -@node i386-Opcodes -@section Opcode Naming +@node i386-Mnemonics +@section Instruction Naming -@cindex i386 opcode naming -@cindex opcode naming, i386 -Opcode names are suffixed with one character modifiers which specify the -size of operands. The letters @samp{b}, @samp{w}, and @samp{l} specify -byte, word, and long operands. If no suffix is specified by an -instruction and it contains no memory operands then @code{@value{AS}} tries to -fill in the missing suffix based on the destination register operand -(the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent -to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to -@samp{movw $1, %bx}. Note that this is incompatible with the AT&T Unix -assembler which assumes that a missing opcode suffix implies long -operand size. (This incompatibility does not affect compiler output -since compilers always explicitly specify the opcode suffix.) - -Almost all opcodes have the same names in AT&T and Intel format. There -are a few exceptions. The sign extend and zero extend instructions need -two sizes to specify them. They need a size to sign/zero extend -@emph{from} and a size to zero extend @emph{to}. This is accomplished -by using two opcode suffixes in AT&T syntax. Base names for sign extend -and zero extend are @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T -syntax (@samp{movsx} and @samp{movzx} in Intel syntax). The opcode -suffixes are tacked on to this base name, the @emph{from} suffix before -the @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for +@cindex i386 instruction naming +@cindex instruction naming, i386 +Instruction mnemonics are suffixed with one character modifiers which +specify the size of operands. The letters @samp{b}, @samp{w}, and +@samp{l} specify byte, word, and long operands. If no suffix is +specified by an instruction then @code{@value{AS}} tries to fill in the +missing suffix based on the destination register operand (the last one +by convention). Thus, @samp{mov %ax, %bx} is equivalent to @samp{movw +%ax, %bx}; also, @samp{mov $1, %bx} is equivalent to @samp{movw $1, +%bx}. Note that this is incompatible with the AT&T Unix assembler which +assumes that a missing mnemonic suffix implies long operand size. (This +incompatibility does not affect compiler output since compilers always +explicitly specify the mnemonic suffix.) + +Almost all instructions have the same names in AT&T and Intel format. +There are a few exceptions. The sign extend and zero extend +instructions need two sizes to specify them. They need a size to +sign/zero extend @emph{from} and a size to zero extend @emph{to}. This +is accomplished by using two instruction mnemonic suffixes in AT&T +syntax. Base names for sign extend and zero extend are +@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} +and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes +are tacked on to this base name, the @emph{from} suffix before the +@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), and @samp{wl} (from word to long). @@ -161,7 +165,7 @@ convention. @cindex i386 registers @cindex registers, i386 -Register operands are always prefixes with @samp{%}. The 80386 registers +Register operands are always prefixed with @samp{%}. The 80386 registers consist of @itemize @bullet @@ -202,26 +206,30 @@ the 8 floating point register stack @sam @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. @end itemize -@node i386-prefixes -@section Opcode Prefixes +@node i386-Prefixes +@section Instruction Prefixes -@cindex i386 opcode prefixes -@cindex opcode prefixes, i386 +@cindex i386 instruction prefixes +@cindex instruction prefixes, i386 @cindex prefixes, i386 -Opcode prefixes are used to modify the following opcode. They are used -to repeat string instructions, to provide section overrides, to perform -bus lock operations, and to give operand and address size (16-bit -operands are specified in an instruction by prefixing what would -normally be 32-bit operands with a ``operand size'' opcode prefix). -Opcode prefixes are usually given as single-line instructions with no -operands, and must directly precede the instruction they act upon. For -example, the @samp{scas} (scan string) instruction is repeated with: +Instruction prefixes are used to modify the following instruction. They +are used to repeat string instructions, to provide section overrides, to +perform bus lock operations, and to change operand and address sizes. +(Most instructions that normally operate on 32-bit operands will use +16-bit operands if the instruction has an ``operand size'' prefix.) +Instruction prefixes are best written on the same line as the instruction +they act upon. For example, the @samp{scas} (scan string) instruction is +repeated with: + @smallexample - repne - scas + repne scas %es:(%edi),%al @end smallexample -Here is a list of opcode prefixes: +You may also place prefixes on the lines immediately preceding the +instruction, but this circumvents checks that @code{@value{AS}} does +with prefixes, and will not work with all prefixes. + +Here is a list of instruction prefixes: @cindex section override prefixes, i386 @itemize @bullet @@ -233,27 +241,35 @@ using the @var{section}:@var{memory-oper @cindex size prefixes, i386 @item Operand/Address size prefixes @samp{data16} and @samp{addr16} -change 32-bit operands/addresses into 16-bit operands/addresses. Note -that 16-bit addressing modes (i.e. 8086 and 80286 addressing modes) -are not supported (yet). +change 32-bit operands/addresses into 16-bit operands/addresses, +while @samp{data32} and @samp{addr32} change 16-bit ones (in a +@code{.code16} section) into 32-bit operands/addresses. These prefixes +@emph{must} appear on the same line of code as the instruction they +modify. For example, in a 16-bit @code{.code16} section, you might +write: + +@smallexample + addr32 jmpl *(%ebx) +@end smallexample @cindex bus lock prefixes, i386 @cindex inhibiting interrupts, i386 @item -The bus lock prefix @samp{lock} inhibits interrupts during -execution of the instruction it precedes. (This is only valid with -certain instructions; see a 80386 manual for details). +The bus lock prefix @samp{lock} inhibits interrupts during execution of +the instruction it precedes. (This is only valid with certain +instructions; see a 80386 manual for details). @cindex coprocessor wait, i386 @item -The wait for coprocessor prefix @samp{wait} waits for the -coprocessor to complete the current instruction. This should never be -needed for the 80386/80387 combination. +The wait for coprocessor prefix @samp{wait} waits for the coprocessor to +complete the current instruction. This should never be needed for the +80386/80387 combination. @cindex repeat prefixes, i386 @item The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added -to string instructions to make them repeat @samp{%ecx} times. +to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} +times if the current address size is 16-bits). @end itemize @node i386-Memory @@ -282,7 +298,7 @@ to calculate the address of the operand. specified, @var{scale} is taken to be 1. @var{section} specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register -defaults). Note that section overrides in AT&T syntax @emph{must} have +defaults). Note that section overrides in AT&T syntax @emph{must} be preceded by a @samp{%}. If you specify a section override which coincides with the default section register, @code{@value{AS}} does @emph{not} output any section register override prefixes to assemble the given @@ -316,9 +332,9 @@ Absolute (as opposed to PC relative) cal prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} always chooses PC relative addressing for jump/call labels. -Any instruction that has a memory operand @emph{must} specify its size (byte, -word, or long) with an opcode suffix (@samp{b}, @samp{w}, or @samp{l}, -respectively). +Any instruction that has a memory operand, but no register operand, +@emph{must} specify its size (byte, word, or long) with an instruction +mnemonic suffix (@samp{b}, @samp{w}, or @samp{l}, respectively). @node i386-jumps @section Handling of Jump Instructions @@ -329,9 +345,10 @@ Jump instructions are always optimized t displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long (32-bit) displacement is used. We do not support -word (16-bit) displacement jumps (i.e. prefixing the jump instruction -with the @samp{addr16} opcode prefix), since the 80386 insists upon masking -@samp{%eip} to 16 bits after the word displacement is added. +word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump +instruction with the @samp{data16} instruction prefix), since the 80386 +insists upon masking @samp{%eip} to 16 bits after the word displacement +is added. Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte @@ -356,9 +373,9 @@ All 80387 floating point types except pa (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. -Each supported type has an opcode suffix and a constructor -associated with it. Opcode suffixes specify operand's data -types. Constructors build these data types into memory. +Each supported type has an instruction mnemonic suffix and a constructor +associated with it. Instruction mnemonic suffixes specify the operand's +data type. Constructors build these data types into memory. @cindex @code{float} directive, i386 @cindex @code{single} directive, i386 @@ -368,10 +385,10 @@ types. Constructors build these data ty @item Floating point constructors are @samp{.float} or @samp{.single}, @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. -These correspond to opcode suffixes @samp{s}, @samp{l}, and @samp{t}. -@samp{t} stands for temporary real, and that the 80387 only supports -this format via the @samp{fldt} (load temporary real to stack top) and -@samp{fstpt} (store temporary real and pop stack) instructions. +These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, +and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 +only supports this format via the @samp{fldt} (load 80-bit real to stack +top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. @cindex @code{word} directive, i386 @cindex @code{long} directive, i386 @@ -379,15 +396,20 @@ this format via the @samp{fldt} (load te @cindex @code{quad} directive, i386 @item Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and -@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The corresponding -opcode suffixes are @samp{s} (single), @samp{l} (long), and @samp{q} -(quad). As with the temporary real format the 64-bit @samp{q} format is -only present in the @samp{fildq} (load quad integer to stack top) and -@samp{fistpq} (store quad integer and pop stack) instructions. +@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The +corresponding instruction mnemonic suffixes are @samp{s} (single), +@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, +the 64-bit @samp{q} format is only present in the @samp{fildq} (load +quad integer to stack top) and @samp{fistpq} (store quad integer and pop +stack) instructions. @end itemize -Register to register operations do not require opcode suffixes, -so that @samp{fst %st, %st(1)} is equivalent to @samp{fstl %st, %st(1)}. +Register to register operations should not use instruction mnemonic suffixes. +@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you +wrote @samp{fst %st, %st(1)}, since all register to register operations +use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, +which converts @samp{%st} from 80-bit to 64-bit floating point format, +then stores the result in the 4 byte location @samp{mem}) @node i386-SIMD @section Intel's MMX and AMD's 3DNow! SIMD Operations @@ -396,21 +418,20 @@ so that @samp{fst %st, %st(1)} is equiva @cindex 3DNow!, i386 @cindex SIMD, i386 -GAS supports Intel's MMX instruction set (SIMD instructions for integer -data), available on Intel's Pentium MMX processors and Pentium II -processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and -probably others. It also supports AMD's 3DNow! instruction set (SIMD -instructions for 32-bit floating point data) available on AMD's K6-2 -processor and possibly others in the future. - -Currently, GAS does not support Intel's floating point SIMD, Katmai (KNI). - -None of these instructions are used by gcc, though there is no reason they -shouldn't be aside from the lack of expressiveness of SIMD operations in C. - -The 8 64-bit MMX operands, shared by 3DNow! are called @samp{%mm0}, @samp{%mm1}, -... @samp{%mm7}, and conceptually contain from eight 8-bit values to two -32-bit float values. The MMX registers cannot be used at the same time +@code{@value{AS}} supports Intel's MMX instruction set (SIMD +instructions for integer data), available on Intel's Pentium MMX +processors and Pentium II processors, AMD's K6 and K6-2 processors, +Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! +instruction set (SIMD instructions for 32-bit floating point data) +available on AMD's K6-2 processor and possibly others in the future. + +Currently, @code{@value{AS}} does not support Intel's floating point +SIMD, Katmai (KNI). + +The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, +@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four +16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit +floating point values. The MMX registers cannot be used at the same time as the floating point stack. See Intel and AMD documentation, keeping in mind that the operand order in @@ -424,42 +445,55 @@ instructions is reversed from the Intel @cindex real-mode code, i386 @cindex @code{code16} directive, i386 @cindex @code{code32} directive, i386 -While GAS normally writes only ``pure'' 32-bit i386 code, it has limited -support for writing code to run in real mode or in 16-bit protected mode -code segments. To do this, insert a @samp{.code16} directive before the -assembly language instructions to be run in 16-bit mode. You can switch -GAS back to writing normal 32-bit code with the @samp{.code32} directive. - -GAS understands exactly the same assembly language syntax in 16-bit mode as -in 32-bit mode. The function of any given instruction is exactly the same -regardless of mode, as long as the resulting object code is executed in the -mode for which GAS wrote it. So, for example, the @samp{ret} mnemonic -produces a 32-bit return instruction regardless of whether it is to be run -in 16-bit or 32-bit mode. (If GAS is in 16-bit mode, it will add an -operand size prefix to the instruction to force it to be a 32-bit return.) - -This means, for one thing, that you can use @sc{gnu} @sc{cc} to write code to be run -in real mode or 16-bit protected mode. Just insert the statement -@samp{asm(".code16");} at the beginning of your C source file, and while -@sc{gnu} @sc{cc} will still be generating 32-bit code, GAS will automatically add -all the necessary size prefixes to make that code run in 16-bit mode. Of -course, since @sc{gnu} @sc{cc} only writes small-model code (it doesn't know how to -attach segment selectors to pointers like native x86 compilers do), any -16-bit code you write with @sc{gnu} @sc{cc} will essentially be limited to a 64K -address space. Also, there will be a code size and performance penalty -due to all the extra address and operand size prefixes GAS has to add to -the instructions. - -Note that placing GAS in 16-bit mode does not mean that the resulting -code will necessarily run on a 16-bit pre-80386 processor. To write code -that runs on such a processor, you would have to refrain from using -@emph{any} 32-bit constructs which require GAS to output address or -operand size prefixes. At the moment this would be rather difficult, -because GAS currently supports @emph{only} 32-bit addressing modes: when -writing 16-bit code, it @emph{always} outputs address size prefixes for any -instruction that uses a non-register addressing mode. So you can write -code that runs on 16-bit processors, but only if that code never references -memory. +While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code, +it also supports writing code to run in real mode or in 16-bit protected +mode code segments. To do this, put a @samp{.code16} directive before +the assembly language instructions to be run in 16-bit mode. You can +switch @code{@value{AS}} back to writing normal 32-bit code with the +@samp{.code32} directive. + +The code which @code{@value{AS}} generates in 16-bit mode will not +necessarily run on a 16-bit pre-80386 processor. To write code that +runs on such a processor, you must refrain from using @emph{any} 32-bit +constructs which require @code{@value{AS}} to output address or operand +size prefixes. + +Note that writing 16-bit code instructions by explicitly specifying a +prefix or an instruction mnemonic suffix within a 32-bit code section +generates different machine instructions than those generated for a +16-bit code segment. In a 32-bit code section, the following code +generates the machine opcode bytes @samp{66 6a 04}, which pushes the +value @samp{4} onto the stack, decrementing @samp{%esp} by 2. + +@smallexample + pushw $4 +@end smallexample + +The same code in a 16-bit code section would generate the machine +opcode bytes @samp{6a 04} (ie. without the operand size prefix), which +is correct since the processor default operand size is assumed to be 16 +bits in a 16-bit code section. + +@node i386-Bugs +@section AT&T Syntax bugs + +The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we're stuck +with it. + +For example + +@smallexample + fsub %st,%st(3) +@end smallexample +@noindent +results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather +than the expected @samp{%st(3) - %st}. This happens with all the +non-commutative arithmetic floating point operations with two register +operands where the source register is @samp{%st} and the destination +register is @samp{%st(i)}. @node i386-Notes @section Notes diff --new-file -upr binutils-2.9.1.0.22b/gas/frags.c binutils-2.9.1.0.23/gas/frags.c --- binutils-2.9.1.0.22b/gas/frags.c Tue Mar 31 14:25:07 1998 +++ binutils-2.9.1.0.23/gas/frags.c Wed Mar 31 09:34:16 1999 @@ -67,20 +67,17 @@ frag_grow (nchars) { if (obstack_room (&frchain_now->frch_obstack) < nchars) { - unsigned int n, oldn; + unsigned int n; long oldc; frag_wane (frag_now); frag_new (0); - oldn = (unsigned) -1; oldc = frchain_now->frch_obstack.chunk_size; - frchain_now->frch_obstack.chunk_size = 2 * nchars; - while ((n = obstack_room (&frchain_now->frch_obstack)) < nchars - && n < oldn) + frchain_now->frch_obstack.chunk_size = 2 * nchars + SIZEOF_STRUCT_FRAG; + while ((n = obstack_room (&frchain_now->frch_obstack)) < nchars) { frag_wane (frag_now); frag_new (0); - oldn = n; } frchain_now->frch_obstack.chunk_size = oldc; } diff --new-file -upr binutils-2.9.1.0.22b/gas/subsegs.c binutils-2.9.1.0.23/gas/subsegs.c --- binutils-2.9.1.0.22b/gas/subsegs.c Fri Oct 31 19:09:04 1997 +++ binutils-2.9.1.0.23/gas/subsegs.c Wed Mar 31 09:34:16 1999 @@ -298,6 +298,16 @@ subseg_set_rest (seg, subseg) *lastPP = newP; newP->frch_next = frcP; /* perhaps NULL */ + +#ifdef BFD_ASSEMBLER + { + segment_info_type *seginfo; + seginfo = seg_info (seg); + if (seginfo && seginfo->frchainP == frcP) + seginfo->frchainP = newP; + } +#endif + frcP = newP; } /* diff --new-file -upr binutils-2.9.1.0.22b/gprof/ChangeLog.linux binutils-2.9.1.0.23/gprof/ChangeLog.linux --- binutils-2.9.1.0.22b/gprof/ChangeLog.linux Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/gprof/ChangeLog.linux Wed Mar 31 09:34:16 1999 @@ -1,3 +1,7 @@ +Sun Mar 28 15:32:42 1999 H.J. Lu (hjl@gnu.org) + + * Makefile.in: Regenerated with automake 1.4. + Tue Aug 25 17:14:38 1998 H.J. Lu (hjl@gnu.org) * aclocal.m4: Updated from the gas snasphot 1999-02-23. diff --new-file -upr binutils-2.9.1.0.22b/gprof/Makefile.in binutils-2.9.1.0.23/gprof/Makefile.in --- binutils-2.9.1.0.22b/gprof/Makefile.in Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/gprof/Makefile.in Wed Mar 31 09:34:16 1999 @@ -69,6 +69,7 @@ CATOBJEXT = @CATOBJEXT@ CC = @CC@ DATADIRNAME = @DATADIRNAME@ DLLTOOL = @DLLTOOL@ +EXEEXT = @EXEEXT@ GMOFILES = @GMOFILES@ GMSGFMT = @GMSGFMT@ GT_NO = @GT_NO@ @@ -121,6 +122,7 @@ ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs CONFIG_HEADER = gconfig.h CONFIG_CLEAN_FILES = +bin_PROGRAMS = gprof$(EXEEXT) PROGRAMS = $(bin_PROGRAMS) @@ -269,8 +271,8 @@ distclean-libtool: maintainer-clean-libtool: -gprof: $(gprof_OBJECTS) $(gprof_DEPENDENCIES) - @rm -f gprof +gprof$(EXEEXT): $(gprof_OBJECTS) $(gprof_DEPENDENCIES) + @rm -f gprof$(EXEEXT) $(LINK) $(gprof_LDFLAGS) $(gprof_OBJECTS) $(gprof_LDADD) $(LIBS) gprof.info: gprof.texi diff --new-file -upr binutils-2.9.1.0.22b/ld/ChangeLog.linux binutils-2.9.1.0.23/ld/ChangeLog.linux --- binutils-2.9.1.0.22b/ld/ChangeLog.linux Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/ld/ChangeLog.linux Wed Mar 31 09:34:16 1999 @@ -1,3 +1,8 @@ +Sat Apr 18 18:41:12 1998 Richard Henderson + + * ldlang.c (lang_one_common): Manipulate the section's cooked + size rather than its raw size. + Wed Feb 24 08:12:14 1999 H.J. Lu (hjl@gnu.org) * aclocal.m4: Updated from the gas snasphot 1999-02-23. diff --new-file -upr binutils-2.9.1.0.22b/ld/ldlang.c binutils-2.9.1.0.23/ld/ldlang.c --- binutils-2.9.1.0.22b/ld/ldlang.c Tue Mar 31 14:25:42 1998 +++ binutils-2.9.1.0.23/ld/ldlang.c Wed Mar 31 09:34:16 1999 @@ -2824,8 +2824,8 @@ lang_one_common (h, info) section = h->u.c.p->section; /* Increase the size of the section. */ - section->_raw_size = ALIGN_N (section->_raw_size, - (bfd_size_type) (1 << power_of_two)); + section->_cooked_size = ALIGN_N (section->_cooked_size, + (bfd_size_type) (1 << power_of_two)); /* Adjust the alignment if necessary. */ if (power_of_two > section->alignment_power) @@ -2834,10 +2834,10 @@ lang_one_common (h, info) /* Change the symbol from common to defined. */ h->type = bfd_link_hash_defined; h->u.def.section = section; - h->u.def.value = section->_raw_size; + h->u.def.value = section->_cooked_size; /* Increase the size of the section. */ - section->_raw_size += size; + section->_cooked_size += size; /* Make sure the section is allocated in memory, and make sure that it is no longer a common section. */ diff --new-file -upr binutils-2.9.1.0.22b/opcodes/ChangeLog.linux binutils-2.9.1.0.23/opcodes/ChangeLog.linux --- binutils-2.9.1.0.22b/opcodes/ChangeLog.linux Thu Feb 25 13:57:54 1999 +++ binutils-2.9.1.0.23/opcodes/ChangeLog.linux Wed Mar 31 09:34:16 1999 @@ -1,3 +1,20 @@ +Sun Mar 28 11:48:17 1999 H.J. Lu (hjl@gnu.org) + + * i386-dis.c (INSN_FWAIT): New, defined. + (fetch_data): Return 0 if fwait is the last instruction. + (ckprefix): Do while if prefixes != INSN_FWAIT. + (print_insn_x86): Print fwait if prefixes == INSN_FWAIT. + (putop): Print fwait if necessary. + +Sun Mar 28 11:48:17 1999 H.J. Lu (hjl@gnu.org) + + * i386-dis.c (print_insn_x86): Set bytes_per_line to 7. + +Sat Mar 27 20:53:07 1999 Linas Vepstas (linas@linas.org) + + * i370-opc.c: Correct support for the supervisor (aka + privledged, aka kernel) instructions. + Thu Feb 25 13:12:41 1999 H.J. Lu (hjl@gnu.org) * i386-dis.c (twobyte_has_modrm): Fix "movlps" (0x13). diff --new-file -upr binutils-2.9.1.0.22b/opcodes/i370-opc.c binutils-2.9.1.0.23/opcodes/i370-opc.c --- binutils-2.9.1.0.22b/opcodes/i370-opc.c Wed Feb 24 09:11:51 1999 +++ binutils-2.9.1.0.23/opcodes/i370-opc.c Wed Mar 31 09:34:16 1999 @@ -44,8 +44,16 @@ static long extract_ss_d2 PARAMS (( i370 /* The operands table. - - The fields are bits, shift, insert, extract, flags, name. */ + The fields are bits, shift, insert, extract, flags, name. + The types: + I370_OPERAND_GPR register, must name a register, must be present + I370_OPERAND_RELATIVE displacement or legnth field, must be present + I370_OPERAND_BASE base register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_INDEX index register; if present, must name a register + if absent, should take value of zero + I370_OPERAND_OPTIONAL other optional operand (usuall reg?) +*/ const struct i370_operand i370_operands[] = { @@ -64,8 +72,13 @@ const struct i370_operand i370_operands[ #define RR_R2_MASK (0xf) { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" }, + /* The I field in an RR form SVC-style instruction. */ +#define RR_I (RR_R2 + 1) +#define RR_I_MASK (0xff) + { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" }, + /* The R1 register field in an RX, RS, RSI, or RI form instruction. */ -#define RX_R1 (RR_R2 + 1) +#define RX_R1 (RR_I + 1) #define RX_R1_MASK (0xf << 20) { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" }, @@ -94,16 +107,11 @@ const struct i370_operand i370_operands[ #define RS_R3_MASK (0xf << 16) { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" }, - /* The ignored field in an RS form instruction. */ - /* treat as an index as far as optional-operand counting is concerned */ -#define RS_IGN (RS_R3 + 1) -#define RS_IGN_MASK (0xf << 16) - { 4, 16, 0, 0, I370_OPERAND_INDEX, "RS IGNORE" }, - /* The optional B2 base field in an RS form instruction. */ -#define RS_B2_OPT (RS_IGN + 1) + /* Note that this field will almost always be absent */ +#define RS_B2_OPT (RS_R3 + 1) #define RS_B2_OPT_MASK (0xf << 12) - { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RX B2 OPT"}, + { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"}, /* The I2 index field in an SI form instruction. */ #define SI_I2 (RS_B2_OPT + 1) @@ -232,6 +240,12 @@ extract_ss_d2 (insn, invalid) #define RR_MASK RR (0xff, 0x0, 0x0) +/* An SVC-style instruction. */ +#define RI(op, i) \ + (OPS (op) | (((unsigned short)(i)) & 0xff)) + +#define RI_MASK RI (0xff, 0x0) + /* An RX form instruction. */ #define RX(op, r1, x2, b2, d2) \ (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ @@ -316,8 +330,8 @@ extract_ss_d2 (insn, invalid) const struct i370_opcode i370_opcodes[] = { /* E form instructions */ -{ "pr", 2, E(0x0101), 0, E_MASK, 0, ANY, NULL}, -{ "upt", 2, E(0x0102), 0, E_MASK, 0, ANY, NULL}, +{ "pr", 2, E(0x0101), 0, E_MASK, 0, ANY, 0}, +{ "upt", 2, E(0x0102), 0, E_MASK, 0, ANY, 0}, /* RR form instructions */ { "ar", 2, RR(0x1a,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, @@ -371,14 +385,16 @@ const struct i370_opcode i370_opcodes[] { "sdr", 2, RR(0x2b,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "ser", 2, RR(0x3b,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "slr", 2, RR(0x1f,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, -{ "spm", 2, RR(0x04,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, +{ "spm", 2, RR(0x04,0,0), 0, RR_MASK, 0, ANY, { RR_R1 } }, { "sr", 2, RR(0x1b,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "sur", 2, RR(0x3f,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "swr", 2, RR(0x2f,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "sxr", 2, RR(0x37,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, -{ "svc", 2, RR(0x0a,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, { "xr", 2, RR(0x17,0,0), 0, RR_MASK, 0, ANY, { RR_R1, RR_R2 } }, +/* unusual RR formats */ +{ "svc", 2, RI(0x0a,0), 0, RI_MASK, 0, ANY, { RR_I } }, + /* RX form instructions */ { "a", 4, RX(0x5a,0,0,0,0), 0, RX_MASK, 0, ANY, {RX_R1, RX_D2, RX_X2, RX_B2}}, { "ad", 4, RX(0x6a,0,0,0,0), 0, RX_MASK, 0, ANY, {RX_R1, RX_D2, RX_X2, RX_B2}}, @@ -452,14 +468,14 @@ const struct i370_opcode i370_opcodes[] { "trace", 4, RS(0x99,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_R3, RS_D2, RX_B2}}, /* RS form instructions with blank R3 and optional B2 (shift left/right) */ -{ "sla", 4, RS(0x8b,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "slda", 4, RS(0x8f,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "sldl", 4, RS(0x8d,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "sll", 4, RS(0x89,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "sra", 4, RS(0x8a,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "srda", 4, RS(0x8e,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "srdl", 4, RS(0x8c,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, -{ "srl", 4, RS(0x88,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_IGN, RS_D2, RS_B2_OPT}}, +{ "sla", 4, RS(0x8b,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "slda", 4, RS(0x8f,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "sldl", 4, RS(0x8d,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "sll", 4, RS(0x89,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "sra", 4, RS(0x8a,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "srda", 4, RS(0x8e,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "srdl", 4, RS(0x8c,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, +{ "srl", 4, RS(0x88,0,0,0,0), 0, RS_MASK, 0, ANY, {RX_R1, RS_D2, RS_B2_OPT}}, /* SI form instructions */ { "cli", 4, SI(0x95,0,0,0), 0, SI_MASK, 0, ANY, { SI_D1, SI_B1, SI_I2}}, @@ -499,19 +515,19 @@ const struct i370_opcode i370_opcodes[] /* S form instructions */ { "cfc", 4, S(0xb21a,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "csch", 4, S(0xb230,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "hsch", 4, S(0xb231,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "ipk", 4, S(0xb20b,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, +{ "csch", 4, S(0xb230,0,0), 0, S_MASK, 0, ANY, 0}, +{ "hsch", 4, S(0xb231,0,0), 0, S_MASK, 0, ANY, 0}, +{ "ipk", 4, S(0xb20b,0,0), 0, S_MASK, 0, ANY, 0}, { "lpsw", 4, S(0x8200,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, { "msch", 4, S(0xb232,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, { "pc", 4, S(0xb218,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "ptlb", 4, S(0xb20d,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "rchp", 4, S(0xb23b,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "rsch", 4, S(0xb238,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, +{ "ptlb", 4, S(0xb20d,0,0), 0, S_MASK, 0, ANY, 0}, +{ "rchp", 4, S(0xb23b,0,0), 0, S_MASK, 0, ANY, 0}, +{ "rsch", 4, S(0xb238,0,0), 0, S_MASK, 0, ANY, 0}, { "sac", 4, S(0xb219,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, { "sacf", 4, S(0xb279,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "sal", 4, S(0xb237,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, -{ "schm", 4, S(0xb23c,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, +{ "sal", 4, S(0xb237,0,0), 0, S_MASK, 0, ANY, 0}, +{ "schm", 4, S(0xb23c,0,0), 0, S_MASK, 0, ANY, 0}, { "sck", 4, S(0xb204,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, { "sckc", 4, S(0xb206,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, { "spka", 4, S(0xb20a,0,0), 0, S_MASK, 0, ANY, { S_D2, S_B2}}, @@ -542,21 +558,21 @@ const struct i370_opcode i370_opcodes[] { "cuse", 4, RRE(0xb257,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "dxr", 4, RRE(0xb22d,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "ear", 4, RRE(0xb24f,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "epar", 4, RRE(0xb226,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "epar", 4, RRE(0xb226,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, { "ereg", 4, RRE(0xb249,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "esar", 4, RRE(0xb227,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "esar", 4, RRE(0xb227,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, { "esta", 4, RRE(0xb24a,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "iac", 4, RRE(0xb224,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "ipm", 4, RRE(0xb222,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "iac", 4, RRE(0xb224,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, +{ "ipm", 4, RRE(0xb222,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, { "ipte", 4, RRE(0xb221,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "iske", 4, RRE(0xb229,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "ivsk", 4, RRE(0xb223,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "lura", 4, RRE(0xb24b,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "msr", 4, RRE(0xb252,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "msta", 4, RRE(0xb247,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "msta", 4, RRE(0xb247,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, { "mvpg", 4, RRE(0xb254,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "mvst", 4, RRE(0xb255,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "palb", 4, RRE(0xb248,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "palb", 4, RRE(0xb248,0,0), 0, RRE_MASK, 0, ANY, 0}, { "prbe", 4, RRE(0xb22a,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "pt", 4, RRE(0xb228,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "rrbe", 4, RRE(0xb22a,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, @@ -564,7 +580,7 @@ const struct i370_opcode i370_opcodes[] { "sqdr", 4, RRE(0xb244,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "sqer", 4, RRE(0xb245,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "srst", 4, RRE(0xb25e,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, -{ "ssar", 4, RRE(0xb225,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, +{ "ssar", 4, RRE(0xb225,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1}}, { "sske", 4, RRE(0xb22b,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "stura", 4, RRE(0xb246,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, { "tar", 4, RRE(0xb24c,0,0), 0, RRE_MASK, 0, ANY, { RRE_R1, RRE_R2}}, @@ -597,6 +613,24 @@ const struct i370_macro i370_macros[] = { "bnlr", 1, ANY, "bcr 11,%0" }, { "bne", 1, ANY, "bc 7,%0" }, { "bner", 1, ANY, "bcr 7,%0" }, + +{ "bp", 1, ANY, "bc 2,%0" }, +{ "bpr", 1, ANY, "bcr 2,%0" }, +{ "bm", 1, ANY, "bc 4,%0" }, +{ "bmr", 1, ANY, "bcr 4,%0" }, +{ "bz", 1, ANY, "bc 8,%0" }, +{ "bzr", 1, ANY, "bcr 8,%0" }, +{ "bo", 1, ANY, "bc 1,%0" }, +{ "bor", 1, ANY, "bcr 1,%0" }, + +{ "bnp", 1, ANY, "bc 13,%0" }, +{ "bnpr", 1, ANY, "bcr 13,%0" }, +{ "bnm", 1, ANY, "bc 11,%0" }, +{ "bnmr", 1, ANY, "bcr 11,%0" }, +{ "bnz", 1, ANY, "bc 7,%0" }, +{ "bnzr", 1, ANY, "bcr 7,%0" }, +{ "bno", 1, ANY, "bc 14,%0" }, +{ "bnor", 1, ANY, "bcr 14,%0" }, { "sync", 0, ANY, "bcr 15,0" }, diff --new-file -upr binutils-2.9.1.0.22b/opcodes/i386-dis.c binutils-2.9.1.0.23/opcodes/i386-dis.c --- binutils-2.9.1.0.22b/opcodes/i386-dis.c Thu Feb 25 13:36:46 1999 +++ binutils-2.9.1.0.23/opcodes/i386-dis.c Wed Mar 31 09:34:16 1999 @@ -39,6 +39,7 @@ Foundation, Inc., 59 Temple Place - Suit #define MAXLEN 20 #include +#include static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); @@ -51,6 +52,22 @@ struct dis_private jmp_buf bailout; }; +#define PREFIX_REPZ 1 +#define PREFIX_REPNZ 2 +#define PREFIX_LOCK 4 +#define PREFIX_CS 8 +#define PREFIX_SS 0x10 +#define PREFIX_DS 0x20 +#define PREFIX_ES 0x40 +#define PREFIX_FS 0x80 +#define PREFIX_GS 0x100 +#define PREFIX_DATA 0x200 +#define PREFIX_ADR 0x400 +#define PREFIX_FWAIT 0x800 +#define INSN_FWAIT 0x1000 + +static int prefixes; + /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) to ADDR (exclusive) are valid. Returns 1 for success, longjmps on error. */ @@ -73,8 +90,17 @@ fetch_data (info, addr) info); if (status != 0) { - (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); + if ((prefixes & PREFIX_FWAIT) == PREFIX_FWAIT && status == EIO) + { + /* It is possible that fwait is the last instruction. We make + it an instruction. */ + prefixes = INSN_FWAIT; + return 0; + } + else { + (*info->memory_error_func) (status, start, info); + longjmp (priv->bailout, 1); + } } else priv->max_fetched = addr; @@ -1265,26 +1291,11 @@ static struct dis386 prefix_user_table[] } }; -#define PREFIX_REPZ 1 -#define PREFIX_REPNZ 2 -#define PREFIX_LOCK 4 -#define PREFIX_CS 8 -#define PREFIX_SS 0x10 -#define PREFIX_DS 0x20 -#define PREFIX_ES 0x40 -#define PREFIX_FS 0x80 -#define PREFIX_GS 0x100 -#define PREFIX_DATA 0x200 -#define PREFIX_ADR 0x400 -#define PREFIX_FWAIT 0x800 - -static int prefixes; - static void ckprefix () { prefixes = 0; - while (1) + while (prefixes != INSN_FWAIT) { FETCH_DATA (the_info, codep + 1); switch (*codep) @@ -1381,9 +1392,9 @@ print_insn_x86 (pc, info, aflag, dflag) struct dis_private priv; bfd_byte *inbuf = priv.the_buffer; - /* The output looks better if we put 5 bytes on a line, since that + /* The output looks better if we put 7 bytes on a line, since that puts long word instructions on a single line. */ - info->bytes_per_line = 6; + info->bytes_per_line = 7; info->private_data = (PTR) &priv; priv.max_fetched = priv.the_buffer; @@ -1406,6 +1417,13 @@ print_insn_x86 (pc, info, aflag, dflag) ckprefix (); + if (prefixes == INSN_FWAIT) + { + /* fwait not followed by any instructions */ + (*info->fprintf_func) (info->stream, "fwait"); + return (1); + } + FETCH_DATA (info, codep + 1); if (*codep == 0xc8) enter_instruction = 1; @@ -1873,6 +1891,14 @@ putop (template, aflag, dflag) { char *p; + if ((prefixes & PREFIX_FWAIT) && !strchr (template, 'N')) + { + /* We print out fwait if it is not the part of the instuctions. */ +#define FWAIT_STRING "fwait; " + strcat (obufp, FWAIT_STRING); + obufp += sizeof (FWAIT_STRING) - 1; + } + for (p = template; *p; p++) { switch (*p)