--- avr-libc-2.0.0+Atmel3.6.1.orig/debian/avr-man +++ avr-libc-2.0.0+Atmel3.6.1/debian/avr-man @@ -0,0 +1,2 @@ +#! /bin/sh +exec man -s 3avr "$@" --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/avr-man.1 +++ avr-libc-2.0.0+Atmel3.6.1/debian/avr-man.1 @@ -0,0 +1,17 @@ +.TH "AVR_MAN" 1 "2014-01-02" +.SH NAME +avr-man - a man(1) replacement to access the avr-libc manual pages +.SH SYNOPSIS +\fB avr-man \fR [ \fIOPTION\fR ] \fIpage\fR +.SH DESCRIPTION +.B avr-man +is a wrapper script for \fBman\fR(1), displaying results for the specified \fIpage\fR from the manual pages shipped with the +.IR avr-libc +package. +.PP +\fIOPTION\fR parameters are passed to man. It is included for backwards compatibility. The recommended way to access these pages is now: + + man 3avr page + +.SH "SEE ALSO" +\fBman\fR(1) --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/bug_675759.patch +++ avr-libc-2.0.0+Atmel3.6.1/debian/bug_675759.patch @@ -0,0 +1,15 @@ +Index: include/avr/pgmspace.h +=================================================================== +--- include/avr/pgmspace.h (revision 2293) ++++ include/avr/pgmspace.h (revision 2294) +@@ -1081,8 +1081,8 @@ + extern int memcmp_PF(const void *, uint_farptr_t, size_t) __ATTR_PURE__; + + +-__attribute__((__always_inline__)) static inline size_t strlen_P(const char * s); +-static inline size_t strlen_P(const char *s) { ++__attribute__((__always_inline__)) static __inline__ size_t strlen_P(const char * s); ++static __inline__ size_t strlen_P(const char *s) { + return __builtin_constant_p(__builtin_strlen(s)) + ? __builtin_strlen(s) : __strlen_P(s); + } --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/changelog +++ avr-libc-2.0.0+Atmel3.6.1/debian/changelog @@ -0,0 +1,361 @@ +avr-libc (1:2.0.0+Atmel3.6.1-2) unstable; urgency=medium + + [ Hakan Ardo ] + * Fix latex errors (closes: #921775) + + [ Ondřej Nový ] + * d/control: Deprecating priority extra as per policy 4.0.1 + * d/changelog: Remove trailing whitespaces + * d/control: Remove trailing whitespaces + * d/rules: Remove trailing whitespaces + * d/control: Add Vcs-* field + + -- Hakan Ardo Sat, 16 Feb 2019 16:54:38 +0100 + +avr-libc (1:2.0.0+Atmel3.6.1-1) unstable; urgency=medium + + * New upstream release + + -- Hakan Ardo Thu, 28 Jun 2018 12:03:45 +0200 + +avr-libc (1:2.0.0+Atmel3.6.0-1) unstable; urgency=medium + + * New upstream release + + -- Hakan Ardo Fri, 04 Aug 2017 19:22:45 +0200 + +avr-libc (1:2.0.0+Atmel3.5.4-1.1) unstable; urgency=medium + + * Non-maintainer upload. + * Replaced the versioned build-dependency on autoconf2.59 by a + dependency on autoconf, which closes: #859535 + + -- Georges Khaznadar Wed, 12 Jul 2017 10:03:02 +0200 + +avr-libc (1:2.0.0+Atmel3.5.4-1) unstable; urgency=medium + + * New upstream release (closes: #779495, #787715, #762303, #785797) + + -- Hakan Ardo Wed, 05 Apr 2017 19:32:00 +0200 + +avr-libc (1:1.8.0+Atmel3.5.0-1) unstable; urgency=medium + + * New upstream release + * Add configure option --enable-device-lib + + -- Hakan Ardo Fri, 11 Dec 2015 16:58:02 +0100 + +avr-libc (1:1.8.0+Atmel3.4.5-1) unstable; urgency=medium + + * Added watch file + * New upstream release + + -- Hakan Ardo Wed, 01 Apr 2015 20:17:29 +0200 + +avr-libc (1:1.8.0+Atmel3.4.4-1) unstable; urgency=medium + + * New upstream release from Atmel-AVR-GNU-Toolchain v3.4.4 + (http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU- + Toolchain/3.4.4/) (closes: #740391, #739953, #695514, #719635) + * Moved manpages to the 3avr section of /usr/share/man + * Added avr-man manpage (closes: #733939) + * Added build-arch and build-indep targets + * Moved build to binary-indep target + * Increased standards version to 3.9.5 + * Added ${misc:Depends} dependency + * Applied upstream fix to make pgmspace.h ansi compatible (closes: + #675759) + + -- Hakan Ardo Tue, 03 Jun 2014 14:25:22 +0200 + +avr-libc (1:1.8.0-4.1) unstable; urgency=medium + + * Non-maintainer upload. + * debian/control: Switch to automake1.11. (Closes: #724351) + + -- Eric Dorland Sun, 02 Mar 2014 18:14:01 -0500 + +avr-libc (1:1.8.0-4) unstable; urgency=low + + * Recompiled with gcc 4.8 + + -- Hakan Ardo Sat, 05 Oct 2013 15:54:43 +0200 + +avr-libc (1:1.8.0-3) unstable; urgency=low + + * Move man pages to /usr/share/doc/avr-libc/man (closes: #678584, + #677059) + + -- Hakan Ardo Thu, 26 Jul 2012 07:31:00 +0200 + +avr-libc (1:1.8.0-2) unstable; urgency=low + + * New upstream release + + -- Hakan Ardo Wed, 23 May 2012 10:30:07 +0200 + +avr-libc (1:1.8.0-1) experimental; urgency=low + + * new upstream release + + -- Hakan Ardo Thu, 22 Mar 2012 21:01:33 +0100 + +avr-libc (1:1.7.1-3) experimental; urgency=low + + * recompiled with gcc 4.7 + + -- Hakan Ardo Thu, 22 Mar 2012 20:43:05 +0100 + +avr-libc (1:1.7.1-2) unstable; urgency=low + + * include/util/delay.h.in: Add math.h to list of includes (closes: + #633822) + + -- Hakan Ardo Thu, 14 Jul 2011 11:15:32 +0200 + +avr-libc (1:1.7.1-1) unstable; urgency=low + + * New upstream release (closes: #626119) + * Now build-depends on doxygen-latex (closes: #616199) + + -- Hakan Ardo Sun, 10 Jul 2011 16:46:05 +0200 + +avr-libc (1:1.6.8-2) unstable; urgency=low + + * Recompiled with new toolchain + * Added ATmega325P to wdt.h (closes: #587574) + + -- Hakan Ardo Fri, 30 Jul 2010 10:55:29 +0200 + +avr-libc (1:1.6.8-1) unstable; urgency=low + + * New upstream release + * Replaced builddep on gs-gpl with ghostscript + * Autotools executed during build. + * Now build-depends on doxygen >= 1.6.2 + * Errors in first two latex passes ignored (closes: #562312) + + -- Hakan Ardo Sun, 21 Feb 2010 11:54:12 +0100 + +avr-libc (1:1.6.7-1) unstable; urgency=low + + * New upstream relese (closes: #544030) + * Added lintian overrides (closes: #553265) + + -- Hakan Ardo Sat, 31 Oct 2009 11:52:10 +0100 + +avr-libc (1:1.6.2.cvs20080610-2) unstable; urgency=low + + * Added build-depends on texlive-extra-utils (closes: #493454) + + -- Hakan Ardo Sun, 10 Aug 2008 09:59:16 +0200 + +avr-libc (1:1.6.2.cvs20080610-1) unstable; urgency=low + + * New upstream release: WinAVR-20080610 + + -- Hakan Ardo Sat, 19 Jul 2008 11:18:39 +0200 + +avr-libc (1:1.6.2-2) unstable; urgency=low + + * Recompiled with new gcc to add support for avr6 + * Moved /usr/avr to /usr/lib/avr (closes: #486844) + * pdf manual index now has pagenumbers (closes: #486219) + + -- Hakan Ardo Wed, 02 Jul 2008 13:53:45 +0200 + +avr-libc (1:1.6.2-1) unstable; urgency=low + + * New upstream release + + -- Hakan Ardo Fri, 04 Apr 2008 17:05:32 +0200 + +avr-libc (1:1.6.1-1) unstable; urgency=low + + * New upstream release (closes: #464622) + + -- Hakan Ardo Fri, 08 Feb 2008 14:58:42 +0100 + +avr-libc (1:1.4.7-1) unstable; urgency=low + + * New upstream release (closes: #410831, #420163, #421088, #452199, #394231) + * Replaced tetex packages with texlive in Build-Depends (closes: + #427266) + * Now ignores returnstatus of pdflatex when generating docs to prevent + the build processing from halting on latex warnings (closes: + #427266) + + -- Hakan Ardo Sat, 29 Dec 2007 16:20:03 +0100 + +avr-libc (1:1.4.6-1) unstable; urgency=low + + * New upstream release + + -- Hakan Ardo Thu, 9 Aug 2007 11:28:01 +0200 + +avr-libc (1:1.4.5-3) unstable; urgency=low + + * Recompiled with new gcc/binutils + * Fixed build-depends (closes: #420060) + + -- Hakan Ardo Sun, 22 Apr 2007 17:52:23 +0200 + +avr-libc (1:1.4.5-2) unstable; urgency=low + + * Convertion to debheler fixed (closes: #398220) + * Reference to /usr/share/common-licenses in copyright file + + -- Hakan Ardo Wed, 15 Nov 2006 21:12:47 +0100 + +avr-libc (1:1.4.5-1) unstable; urgency=low + + * New upstream release + * Converted from debmake to debhelper (closes: #373000) + + -- Hakan Ardo Wed, 1 Nov 2006 07:32:23 +0100 + +avr-libc (1:1.4.4-2) unstable; urgency=low + + * Recompiled with gcc-4.1 + + -- Hakan Ardo Mon, 1 May 2006 12:03:39 +0200 + +avr-libc (1:1.4.4-1) unstable; urgency=low + + * New upstream release (closes: #355631, #360685) + + -- Hakan Ardo Mon, 24 Apr 2006 20:43:52 +0200 + +avr-libc (1:1.4.3-1) unstable; urgency=low + + * New upstream release (closes: #350536,#299881). Older versions of avr-libc + are avalible as avr-libc-1.2 and avr-libc-1.0. + + -- Hakan Ardo Sun, 5 Feb 2006 11:29:51 +0100 + +avr-libc (1:1.2.3-3) unstable; urgency=low + + * Added build depends on netpbm + * Added build depends on tetex-extra + + -- Hakan Ardo Sat, 19 Mar 2005 11:16:14 +0100 + +avr-libc (1:1.2.3-2) unstable; urgency=low + + * Added gs to Build-Depends + + -- Hakan Ardo Wed, 2 Mar 2005 07:05:20 +0100 + +avr-libc (1:1.2.3-1) unstable; urgency=low + + * Upstream release + + -- Hakan Ardo Sun, 27 Feb 2005 10:19:36 +0100 + +avr-libc (1:1.2.0-1) unstable; urgency=low + + * Upstream release + + -- Hakan Ardo Sun, 2 Jan 2005 15:31:06 +0100 + +avr-libc (1:1.0.5-1) unstable; urgency=low + + * New upstream release + + -- Hakan Ardo Sun, 26 Dec 2004 12:58:53 +0100 + +avr-libc (1:1.0.4-1) unstable; urgency=low + + * Upstream update + + -- Hakan Ardo Wed, 11 Aug 2004 17:48:58 +0200 + +avr-libc (1:1.0.3-1) unstable; urgency=low + + * Upstream update + + -- Hakan Ardo Mon, 29 Mar 2004 15:08:19 +0200 + +avr-libc (20030512cvs-1) unstable; urgency=low + + * Updated to 20030512 + + -- Hakan Ardo Sat, 24 May 2003 13:39:43 +0200 + +avr-libc (20020203-4) unstable; urgency=low + + * Enabled crtm8.o and crtm128.o (closes: #160290) + * Secured __port_cbi_sbi_ok macro with parens (closes: #182898) + * LICENSE file now included (closes: #182899) + + -- Hakan Ardo Sat, 15 Mar 2003 10:09:49 +0100 + +avr-libc (20020203-3) unstable; urgency=low + + * Added avr link in include dir (closes: #173755) + * Documents and examples now included (closes: #160298) + * Moved around )s in iomacros.h (closes: #162030, #174505) + + -- Hakan Ardo Wed, 26 Feb 2003 18:31:28 +0100 + +avr-libc (20020203-2) unstable; urgency=low + + * Support for the mega AVRs now restored (avr3,avr4 and avr5) + + -- Hakan Ardo Mon, 15 Apr 2002 14:53:38 +0200 + +avr-libc (20020203-1) unstable; urgency=low + + * New upstream release (closes: #139033) + + -- Hakan Ardo Sat, 30 Mar 2002 10:23:12 +0100 + +avr-libc (20010708-4) unstable; urgency=low + + * Updated Build-Depend on gcc to reflect version dependency + (close: #133366). + * Changed arch to all (closes: #134443) + + -- Hakan Ardo Mon, 11 Mar 2002 15:56:30 +0100 + +avr-libc (20010708-3) unstable; urgency=low + + * Recompiled with new avr-gcc instead oc avr-linux-gcc + + -- Hakan Ardo Sat, 9 Feb 2002 16:10:00 +0100 + +avr-libc (20010708-2) unstable; urgency=low + + * Fixed some spell errors (Bug #100109) + * Fixed clean target not to craete dirs (Bug #107089) + + -- Hakan Ardo Sat, 9 Feb 2002 16:09:35 +0100 + +avr-libc (20010708-1) unstable; urgency=low + + * New upstream release + + -- Hakan Ardo Sat, 14 Jul 2001 12:46:11 +0200 + +avr-libc (20010331-1) unstable; urgency=low + + * New upstream release. + * Added Build-Depends + + -- Hakan Ardo Sat, 7 Apr 2001 19:15:22 +0200 + +avr-libc (20000514-2) unstable; urgency=low + + * Moved to main + + -- Hakan Ardo Sun, 29 Oct 2000 13:11:28 +0100 + +avr-libc (20000514-1) unstable; urgency=low + + * Initial Release. + + -- Hakan Ardo Wed, 20 Sep 2000 22:08:40 +0200 + +Local variables: +mode: debian-changelog +End: --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/compat +++ avr-libc-2.0.0+Atmel3.6.1/debian/compat @@ -0,0 +1 @@ +5 --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/control +++ avr-libc-2.0.0+Atmel3.6.1/debian/control @@ -0,0 +1,16 @@ +Source: avr-libc +Section: otherosfs +Priority: optional +Maintainer: Hakan Ardo +Standards-Version: 3.9.5 +Build-Depends: gcc-avr (>=5.4.0+Atmel3.6.1-1), binutils-avr (>=2.26.20160125+Atmel3.6.1-1), debhelper (>=5), doxygen-latex (>=1.8.7), doxygen (>=1.8.7), transfig, ghostscript, netpbm, x11-common, autotools-dev, autoconf, automake1.11, unzip +Vcs-Browser: https://salsa.debian.org/debian/avr-libc +Vcs-Git: https://salsa.debian.org/debian/avr-libc.git + +Package: avr-libc +Architecture: all +Depends: ${shlibs:Depends}, ${misc:Depends}, gcc-avr (>=5.4.0+Atmel3.6.1-1), binutils-avr (>=2.26.20160125+Atmel3.6.1-1) +Description: Standard C library for Atmel AVR development + Standard library used to the development of C programs for the + Atmel AVR micro controllers. This package contains static + libraries as well as the header files needed. --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/copyright +++ avr-libc-2.0.0+Atmel3.6.1/debian/copyright @@ -0,0 +1,77 @@ +This package was debianized by Hakan Ardo hakan@debian.org on +Wed, 20 Sep 2000 22:08:40 +0200. + +It was downloaded from: + + http://savannah.nongnu.org/download/avr-libc/ + +Copyright: + +The contents of avr-libc are licensed with a Modified BSD License. + +All of this is supposed to be Free Software, Open Source, DFSG-free, +GPL-compatible, and OK to use in both free and proprietary applications. + +See the license information in the individual source files for details. + +Additions and corrections to this file are welcome. + +Both the BSD and GPL licens is available in /usr/share/common-licenses. + +******************************************************************************* +Portions of avr-libc are Copyright (c) 1999-2004 +Keith Gudger, +Steinar Haugen, +Peter Jansen, +Reinhard Jessich, +Magnus Johansson, +Artur Lipowski, +Marek Michalkiewicz, +Colin O'Flynn, +Bob Paddock, +Reiner Patommel, +Michael Rickman, +Theodore A. Roth, +Juergen Schilling, +Philip Soeberg, +Nils Kristian Strom, +Michael Stumpf, +Stefan Swanepoel, +Eric B. Weddington, +Joerg Wunsch, +The Regents of the University of California. +All rights reserved. + +Portions of avr-libc documentation Copyright (c) 1990, 1991, 1993, 1994 +The Regents of the University of California. +All rights reserved. + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +******************************************************************************* --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/docs +++ avr-libc-2.0.0+Atmel3.6.1/debian/docs @@ -0,0 +1 @@ +libc/avr-libc/README --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/ignore_latext_exit_code.patch +++ avr-libc-2.0.0+Atmel3.6.1/debian/ignore_latext_exit_code.patch @@ -0,0 +1,19 @@ +*** avr-libc/doc/api/Makefile.am.org 2014-06-04 12:52:19.029957750 +0200 +--- avr-libc/doc/api/Makefile.am 2014-06-04 12:52:32.273985630 +0200 +*************** +*** 227,233 **** + dox-pdf: $(USER_MANUAL).pdf + + $(USER_MANUAL).pdf: latex_src/refman.tex +! cd latex_src && ${MAKE} refman.pdf + cp latex_src/refman.pdf $(USER_MANUAL).pdf + + # Install rules for the various documentation parts. The actual +--- 227,233 ---- + dox-pdf: $(USER_MANUAL).pdf + + $(USER_MANUAL).pdf: latex_src/refman.tex +! -cd latex_src && ${MAKE} refman.pdf + cp latex_src/refman.pdf $(USER_MANUAL).pdf + + # Install rules for the various documentation parts. The actual --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/lintian_overrides +++ avr-libc-2.0.0+Atmel3.6.1/debian/lintian_overrides @@ -0,0 +1,2 @@ +avr-libc: arch-independent-package-contains-binary-or-object + --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/rules +++ avr-libc-2.0.0+Atmel3.6.1/debian/rules @@ -0,0 +1,67 @@ +#!/usr/bin/make -f +# Made with the aid of debmake, by Christoph Lameter, +# based on the sample debian/rules file for GNU hello by Ian Jackson. + +package=avr-libc + +SRC=libc/avr-libc + +build: build-stamp +build-stamp: + $(checkdir) + cd $(SRC) && ./bootstrap + cd $(SRC) && ./configure --build=`./config.guess` --host=avr \ + --prefix=/usr/lib --enable-device-lib \ + --disable-versioned-doc --enable-doc \ + --disable-ps-doc --datadir=/usr/share --bindir=/usr/bin \ + --mandir=/usr/share/man + + cd $(SRC) && make + touch build-stamp + +build-arch: build +build-indep: build + +clean: + $(checkdir) + -make -C $(SRC) distclean + -rm -rf debian/tmp debian/files* core debian/substvars + -rm build-stamp + -rm -r libc/avr-libc/avr + -dh_clean + +binary-indep: checkroot build + $(checkdir) + RGBDEF=/etc/X11/rgb.txt make -C $(SRC) install DESTDIR=`pwd`/debian/$(package) + cp $(SRC)/NEWS debian/$(package)/usr/share/doc/$(package)/changelog + install -d debian/$(package)/usr/share/lintian/overrides + cp debian/lintian_overrides debian/$(package)/usr/share/lintian/overrides/$(package) + mv debian/avr-libc/usr/lib/bin debian/avr-libc/usr/ + install -d debian/avr-libc/usr/share/man/man1 + cp debian/avr-man.1 debian/avr-libc/usr/share/man/man1 + cp debian/avr-man debian/avr-libc/usr/bin/ + + dh_installchangelogs + dh_installdocs + dh_installman + dh_compress + dh_fixperms + dh_installdeb + + dh_md5sums + dh_gencontrol + dh_builddeb + +binary-arch: checkroot build + +define checkdir + test -f debian/rules +endef + +binary: binary-indep binary-arch + +checkroot: + $(checkdir) + test root = "`whoami`" + +.PHONY: binary binary-arch binary-indep clean checkroot --- avr-libc-2.0.0+Atmel3.6.1.orig/debian/watch +++ avr-libc-2.0.0+Atmel3.6.1/debian/watch @@ -0,0 +1,3 @@ +version=3 +opts=dversionmangle=s/^.*\+Atmel// \ + http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU-Toolchain/ (\d+\.\d+\.\d+)/ --- avr-libc-2.0.0+Atmel3.6.1.orig/import_upstream.sh +++ avr-libc-2.0.0+Atmel3.6.1/import_upstream.sh @@ -0,0 +1,47 @@ +#!/bin/bash + +if [ $# -ne 3 ]; then + echo Usage: $0 '' '' '' + echo Exmpl: $0 avr-libc.tar.bz2 avr8-headers.zip 2.0.0+Atmel3.6.0 + exit -1 +fi + +VER=$3 + +set -x +set -e + +git checkout upstream +rm -Rf libc avr +tar xf $1 +unzip $2 +git add libc avr +git commit -m "Import upstream version $VER" +git tag upstream/$VER +git push +git push --tags + +git checkout master +git merge --no-commit upstream || true +#sed -i -s 's/^MAN_EXTENSION.*/MAN_EXTENSION = .3avr/' libc/avr-libc/doc/api/doxygen.config.in +#echo 'MAN_SUBDIR = man3' >> libc/avr-libc/doc/api/doxygen.config.in +#sed -i -s 's/man\/man3\/\*.3/man\/man3\/\*.3avr/' libc/avr-libc/doc/api/Makefile.am +mv avr/*.h libc/avr-libc/include/avr/ +git add libc +git rm -r avr +git commit -m "Merge patched upstream version $VER" + +dch -v 1:$VER-1 New upstream release +dch -r ok +git add debian/changelog + +vim debian/control +git add debian/control + +git commit -m 'Release message in changelog and new versioned deps' + +git tag "debian/$VER-1" +git push +git push --tags + +gbp buildpackage --git-pbuilder --git-upstream-tree=branch --git-upstream-branch=upstream --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/Makefile.in +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/Makefile.in @@ -0,0 +1,854 @@ +# Makefile.in generated by automake 1.15 from Makefile.am. +# @configure_input@ + +# Copyright (C) 1994-2014 Free Software Foundation, Inc. + +# This Makefile.in is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +# PARTICULAR PURPOSE. + +@SET_MAKE@ + +# Copyright (c) 2004,2005 Theodore A. Roth +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of the copyright holders nor the names of +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. 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Yes, it's still used +# in the wild :-( We should find a proper way to deprecate it ... +AC_SUBST([AMTAR], ['$${TAR-tar}']) + +# We'll loop over all known methods to create a tar archive until one works. +_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' + +m4_if([$1], [v7], + [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'], + + [m4_case([$1], + [ustar], + [# The POSIX 1988 'ustar' format is defined with fixed-size fields. + # There is notably a 21 bits limit for the UID and the GID. In fact, + # the 'pax' utility can hang on bigger UID/GID (see automake bug#8343 + # and bug#13588). + am_max_uid=2097151 # 2^21 - 1 + am_max_gid=$am_max_uid + # The $UID and $GID variables are not portable, so we need to resort + # to the POSIX-mandated id(1) utility. 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We do so because we + # need to set the values for the 'am__tar' and 'am__untar' variables. + _am_tools=${am_cv_prog_tar_$1-$_am_tools} + + for _am_tool in $_am_tools; do + case $_am_tool in + gnutar) + for _am_tar in tar gnutar gtar; do + AM_RUN_LOG([$_am_tar --version]) && break + done + am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' + am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' + am__untar="$_am_tar -xf -" + ;; + plaintar) + # Must skip GNU tar: if it does not support --format= it doesn't create + # ustar tarball either. + (tar --version) >/dev/null 2>&1 && continue + am__tar='tar chf - "$$tardir"' + am__tar_='tar chf - "$tardir"' + am__untar='tar xf -' + ;; + pax) + am__tar='pax -L -x $1 -w "$$tardir"' + am__tar_='pax -L -x $1 -w "$tardir"' + am__untar='pax -r' + ;; + cpio) + am__tar='find "$$tardir" -print | cpio -o -H $1 -L' + am__tar_='find "$tardir" -print | cpio -o -H $1 -L' + am__untar='cpio -i -H $1 -d' + ;; + none) + am__tar=false + am__tar_=false + am__untar=false + ;; + esac + + # If the value was cached, stop now. We just wanted to have am__tar + # and am__untar set. + test -n "${am_cv_prog_tar_$1}" && break + + # tar/untar a dummy directory, and stop if the command works. + rm -rf conftest.dir + mkdir conftest.dir + echo GrepMe > conftest.dir/file + AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) + rm -rf conftest.dir + if test -s conftest.tar; then + AM_RUN_LOG([$am__untar /dev/null 2>&1 && break + fi + done + rm -rf conftest.dir + + AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) + AC_MSG_RESULT([$am_cv_prog_tar_$1])]) + +AC_SUBST([am__tar]) +AC_SUBST([am__untar]) +]) # _AM_PROG_TAR + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/compile +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/compile @@ -0,0 +1,347 @@ +#! /bin/sh +# Wrapper for compilers which do not understand '-c -o'. + +scriptversion=2012-10-14.11; # UTC + +# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# Written by Tom Tromey . +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# This file is maintained in Automake, please report +# bugs to or send patches to +# . + +nl=' +' + +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent tools from complaining about whitespace usage. +IFS=" "" $nl" + +file_conv= + +# func_file_conv build_file lazy +# Convert a $build file to $host form and store it in $file +# Currently only supports Windows hosts. If the determined conversion +# type is listed in (the comma separated) LAZY, no conversion will +# take place. +func_file_conv () +{ + file=$1 + case $file in + / | /[!/]*) # absolute file, and not a UNC file + if test -z "$file_conv"; then + # lazily determine how to convert abs files + case `uname -s` in + MINGW*) + file_conv=mingw + ;; + CYGWIN*) + file_conv=cygwin + ;; + *) + file_conv=wine + ;; + esac + fi + case $file_conv/,$2, in + *,$file_conv,*) + ;; + mingw/*) + file=`cmd //C echo "$file " | sed -e 's/"\(.*\) " *$/\1/'` + ;; + cygwin/*) + file=`cygpath -m "$file" || echo "$file"` + ;; + wine/*) + file=`winepath -w "$file" || echo "$file"` + ;; + esac + ;; + esac +} + +# func_cl_dashL linkdir +# Make cl look for libraries in LINKDIR +func_cl_dashL () +{ + func_file_conv "$1" + if test -z "$lib_path"; then + lib_path=$file + else + lib_path="$lib_path;$file" + fi + linker_opts="$linker_opts -LIBPATH:$file" +} + +# func_cl_dashl library +# Do a library search-path lookup for cl +func_cl_dashl () +{ + lib=$1 + found=no + save_IFS=$IFS + IFS=';' + for dir in $lib_path $LIB + do + IFS=$save_IFS + if $shared && test -f "$dir/$lib.dll.lib"; then + found=yes + lib=$dir/$lib.dll.lib + break + fi + if test -f "$dir/$lib.lib"; then + found=yes + lib=$dir/$lib.lib + break + fi + if test -f "$dir/lib$lib.a"; then + found=yes + lib=$dir/lib$lib.a + break + fi + done + IFS=$save_IFS + + if test "$found" != yes; then + lib=$lib.lib + fi +} + +# func_cl_wrapper cl arg... +# Adjust compile command to suit cl +func_cl_wrapper () +{ + # Assume a capable shell + lib_path= + shared=: + linker_opts= + for arg + do + if test -n "$eat"; then + eat= + else + case $1 in + -o) + # configure might choose to run compile as 'compile cc -o foo foo.c'. + eat=1 + case $2 in + *.o | *.[oO][bB][jJ]) + func_file_conv "$2" + set x "$@" -Fo"$file" + shift + ;; + *) + func_file_conv "$2" + set x "$@" -Fe"$file" + shift + ;; + esac + ;; + -I) + eat=1 + func_file_conv "$2" mingw + set x "$@" -I"$file" + shift + ;; + -I*) + func_file_conv "${1#-I}" mingw + set x "$@" -I"$file" + shift + ;; + -l) + eat=1 + func_cl_dashl "$2" + set x "$@" "$lib" + shift + ;; + -l*) + func_cl_dashl "${1#-l}" + set x "$@" "$lib" + shift + ;; + -L) + eat=1 + func_cl_dashL "$2" + ;; + -L*) + func_cl_dashL "${1#-L}" + ;; + -static) + shared=false + ;; + -Wl,*) + arg=${1#-Wl,} + save_ifs="$IFS"; IFS=',' + for flag in $arg; do + IFS="$save_ifs" + linker_opts="$linker_opts $flag" + done + IFS="$save_ifs" + ;; + -Xlinker) + eat=1 + linker_opts="$linker_opts $2" + ;; + -*) + set x "$@" "$1" + shift + ;; + *.cc | *.CC | *.cxx | *.CXX | *.[cC]++) + func_file_conv "$1" + set x "$@" -Tp"$file" + shift + ;; + *.c | *.cpp | *.CPP | *.lib | *.LIB | *.Lib | *.OBJ | *.obj | *.[oO]) + func_file_conv "$1" mingw + set x "$@" "$file" + shift + ;; + *) + set x "$@" "$1" + shift + ;; + esac + fi + shift + done + if test -n "$linker_opts"; then + linker_opts="-link$linker_opts" + fi + exec "$@" $linker_opts + exit 1 +} + +eat= + +case $1 in + '') + echo "$0: No command. Try '$0 --help' for more information." 1>&2 + exit 1; + ;; + -h | --h*) + cat <<\EOF +Usage: compile [--help] [--version] PROGRAM [ARGS] + +Wrapper for compilers which do not understand '-c -o'. +Remove '-o dest.o' from ARGS, run PROGRAM with the remaining +arguments, and rename the output as expected. + +If you are trying to build a whole package this is not the +right script to run: please start by reading the file 'INSTALL'. + +Report bugs to . +EOF + exit $? + ;; + -v | --v*) + echo "compile $scriptversion" + exit $? + ;; + cl | *[/\\]cl | cl.exe | *[/\\]cl.exe ) + func_cl_wrapper "$@" # Doesn't return... + ;; +esac + +ofile= +cfile= + +for arg +do + if test -n "$eat"; then + eat= + else + case $1 in + -o) + # configure might choose to run compile as 'compile cc -o foo foo.c'. + # So we strip '-o arg' only if arg is an object. + eat=1 + case $2 in + *.o | *.obj) + ofile=$2 + ;; + *) + set x "$@" -o "$2" + shift + ;; + esac + ;; + *.c) + cfile=$1 + set x "$@" "$1" + shift + ;; + *) + set x "$@" "$1" + shift + ;; + esac + fi + shift +done + +if test -z "$ofile" || test -z "$cfile"; then + # If no '-o' option was seen then we might have been invoked from a + # pattern rule where we don't need one. That is ok -- this is a + # normal compilation that the losing compiler can handle. If no + # '.c' file was seen then we are probably linking. That is also + # ok. + exec "$@" +fi + +# Name of file we expect compiler to create. +cofile=`echo "$cfile" | sed 's|^.*[\\/]||; s|^[a-zA-Z]:||; s/\.c$/.o/'` + +# Create the lock directory. +# Note: use '[/\\:.-]' here to ensure that we don't use the same name +# that we are using for the .o file. Also, base the name on the expected +# object file name, since that is what matters with a parallel build. +lockdir=`echo "$cofile" | sed -e 's|[/\\:.-]|_|g'`.d +while true; do + if mkdir "$lockdir" >/dev/null 2>&1; then + break + fi + sleep 1 +done +# FIXME: race condition here if user kills between mkdir and trap. +trap "rmdir '$lockdir'; exit 1" 1 2 15 + +# Run the compile. +"$@" +ret=$? + +if test -f "$cofile"; then + test "$cofile" = "$ofile" || mv "$cofile" "$ofile" +elif test -f "${cofile}bj"; then + test "${cofile}bj" = "$ofile" || mv "${cofile}bj" "$ofile" +fi + +rmdir "$lockdir" +exit $ret + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/config.guess +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/config.guess @@ -0,0 +1,1462 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright 1992-2016 Free Software Foundation, Inc. + +timestamp='2016-10-02' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see . +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). +# +# Originally written by Per Bothner; maintained since 2000 by Ben Elliston. +# +# You can get the latest version of this script from: +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess +# +# Please send patches to . + + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright 1992-2016 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +trap 'exit 1' 1 2 15 + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# Portable tmp directory creation inspired by the Autoconf team. + +set_cc_for_build=' +trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; +trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; +: ${TMPDIR=/tmp} ; + { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || + { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || + { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || + { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; +dummy=$tmp/dummy ; +tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; +case $CC_FOR_BUILD,$HOST_CC,$CC in + ,,) echo "int x;" > $dummy.c ; + for c in cc gcc c89 c99 ; do + if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then + CC_FOR_BUILD="$c"; break ; + fi ; + done ; + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found ; + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; +esac ; set_cc_for_build= ;' + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if (test -f /.attbin/uname) >/dev/null 2>&1 ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown +UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown +UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown +UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + +case "${UNAME_SYSTEM}" in +Linux|GNU|GNU/*) + # If the system lacks a compiler, then just pick glibc. + # We could probably try harder. + LIBC=gnu + + eval $set_cc_for_build + cat <<-EOF > $dummy.c + #include + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #else + LIBC=gnu + #endif + EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` + ;; +esac + +# Note: order is significant - the case branches are not exclusive. + +case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=`(uname -p 2>/dev/null || \ + /sbin/$sysctl 2>/dev/null || \ + /usr/sbin/$sysctl 2>/dev/null || \ + echo unknown)` + case "${UNAME_MACHINE_ARCH}" in + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + sh5el) machine=sh5le-unknown ;; + earmv*) + arch=`echo ${UNAME_MACHINE_ARCH} | sed -e 's,^e\(armv[0-9]\).*$,\1,'` + endian=`echo ${UNAME_MACHINE_ARCH} | sed -ne 's,^.*\(eb\)$,\1,p'` + machine=${arch}${endian}-unknown + ;; + *) machine=${UNAME_MACHINE_ARCH}-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently (or will in the future) and ABI. + case "${UNAME_MACHINE_ARCH}" in + earm*) + os=netbsdelf + ;; + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ELF__ + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # Determine ABI tags. + case "${UNAME_MACHINE_ARCH}" in + earm*) + expr='s/^earmv[0-9]/-eabi/;s/eb$//' + abi=`echo ${UNAME_MACHINE_ARCH} | sed -e "$expr"` + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "${UNAME_VERSION}" in + Debian*) + release='-gnu' + ;; + *) + release=`echo ${UNAME_RELEASE} | sed -e 's/[-_].*//' | cut -d. -f1,2` + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}${abi}" + exit ;; + *:Bitrig:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/Bitrig.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-bitrig${UNAME_RELEASE} + exit ;; + *:OpenBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} + exit ;; + *:LibertyBSD:*:*) + UNAME_MACHINE_ARCH=`arch | sed 's/^.*BSD\.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-libertybsd${UNAME_RELEASE} + exit ;; + *:ekkoBSD:*:*) + echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} + exit ;; + *:SolidBSD:*:*) + echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE} + exit ;; + macppc:MirBSD:*:*) + echo powerpc-unknown-mirbsd${UNAME_RELEASE} + exit ;; + *:MirBSD:*:*) + echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} + exit ;; + *:Sortix:*:*) + echo ${UNAME_MACHINE}-unknown-sortix + exit ;; + alpha:OSF1:*:*) + case $UNAME_RELEASE in + *4.0) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + ;; + *5.*) + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` + ;; + esac + # According to Compaq, /usr/sbin/psrinfo has been available on + # OSF/1 and Tru64 systems produced since 1995. I hope that + # covers most systems running today. This code pipes the CPU + # types through head -n 1, so we only detect the type of CPU 0. + ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` + case "$ALPHA_CPU_TYPE" in + "EV4 (21064)") + UNAME_MACHINE=alpha ;; + "EV4.5 (21064)") + UNAME_MACHINE=alpha ;; + "LCA4 (21066/21068)") + UNAME_MACHINE=alpha ;; + "EV5 (21164)") + UNAME_MACHINE=alphaev5 ;; + "EV5.6 (21164A)") + UNAME_MACHINE=alphaev56 ;; + "EV5.6 (21164PC)") + UNAME_MACHINE=alphapca56 ;; + "EV5.7 (21164PC)") + UNAME_MACHINE=alphapca57 ;; + "EV6 (21264)") + UNAME_MACHINE=alphaev6 ;; + "EV6.7 (21264A)") + UNAME_MACHINE=alphaev67 ;; + "EV6.8CB (21264C)") + UNAME_MACHINE=alphaev68 ;; + "EV6.8AL (21264B)") + UNAME_MACHINE=alphaev68 ;; + "EV6.8CX (21264D)") + UNAME_MACHINE=alphaev68 ;; + "EV6.9A (21264/EV69A)") + UNAME_MACHINE=alphaev69 ;; + "EV7 (21364)") + UNAME_MACHINE=alphaev7 ;; + "EV7.9 (21364A)") + UNAME_MACHINE=alphaev79 ;; + esac + # A Pn.n version is a patched version. + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` + # Reset EXIT trap before exiting to avoid spurious non-zero exit code. + exitcode=$? + trap '' 0 + exit $exitcode ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead + # of the specific Alpha model? + echo alpha-pc-interix + exit ;; + 21064:Windows_NT:50:3) + echo alpha-dec-winnt3.5 + exit ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit ;; + *:[Aa]miga[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-amigaos + exit ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-morphos + exit ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit ;; + *:z/VM:*:*) + echo s390-ibm-zvmoe + exit ;; + *:OS400:*:*) + echo powerpc-ibm-os400 + exit ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit ;; + arm*:riscos:*:*|arm*:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit ;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "`(/bin/universe) 2>/dev/null`" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit ;; + DRS?6000:unix:4.0:6*) + echo sparc-icl-nx6 + exit ;; + DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7; exit ;; + esac ;; + s390x:SunOS:*:*) + echo ${UNAME_MACHINE}-ibm-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*) + echo i386-pc-auroraux${UNAME_RELEASE} + exit ;; + i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) + eval $set_cc_for_build + SUN_ARCH=i386 + # If there is a compiler, see if it is configured for 64-bit objects. + # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. + # This test works for both compilers. + if [ "$CC_FOR_BUILD" != no_compiler_found ]; then + if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + SUN_ARCH=x86_64 + fi + fi + echo ${SUN_ARCH}-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + sun4*:SunOS:*:*) + case "`/usr/bin/arch -k`" in + Series*|S4*) + UNAME_RELEASE=`uname -v` + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` + exit ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos${UNAME_RELEASE} + exit ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` + test "x${UNAME_RELEASE}" = x && UNAME_RELEASE=3 + case "`/bin/arch`" in + sun3) + echo m68k-sun-sunos${UNAME_RELEASE} + ;; + sun4) + echo sparc-sun-sunos${UNAME_RELEASE} + ;; + esac + exit ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos${UNAME_RELEASE} + exit ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint${UNAME_RELEASE} + exit ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint${UNAME_RELEASE} + exit ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint${UNAME_RELEASE} + exit ;; + m68k:machten:*:*) + echo m68k-apple-machten${UNAME_RELEASE} + exit ;; + powerpc:machten:*:*) + echo powerpc-apple-machten${UNAME_RELEASE} + exit ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix${UNAME_RELEASE} + exit ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix${UNAME_RELEASE} + exit ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix${UNAME_RELEASE} + exit ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c +#ifdef __cplusplus +#include /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && + dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && + SYSTEM_NAME=`$dummy $dummyarg` && + { echo "$SYSTEM_NAME"; exit; } + echo mips-mips-riscos${UNAME_RELEASE} + exit ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ + [ ${TARGET_BINARY_INTERFACE}x = x ] + then + echo m88k-dg-dgux${UNAME_RELEASE} + else + echo m88k-dg-dguxbcs${UNAME_RELEASE} + fi + else + echo i586-dg-dgux${UNAME_RELEASE} + fi + exit ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit ;; + *:IRIX*:*:*) + echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` + exit ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit ;; + ia64:AIX:*:*) + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} + exit ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` + then + echo "$SYSTEM_NAME" + else + echo rs6000-ibm-aix3.2.5 + fi + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit ;; + *:AIX:*:[4567]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if [ -x /usr/bin/lslpp ] ; then + IBM_REV=`/usr/bin/lslpp -Lqc bos.rte.libc | + awk -F: '{ print $3 }' | sed s/[0-9]*$/0/` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${IBM_ARCH}-ibm-aix${IBM_REV} + exit ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit ;; + ibmrt:4.4BSD:*|romp-ibm:BSD:*) + echo romp-ibm-bsd4.4 + exit ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to + exit ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + case "${UNAME_MACHINE}" in + 9000/31? ) HP_ARCH=m68000 ;; + 9000/[34]?? ) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` + sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` + case "${sc_cpu_version}" in + 523) HP_ARCH=hppa1.0 ;; # CPU_PA_RISC1_0 + 528) HP_ARCH=hppa1.1 ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "${sc_kernel_bits}" in + 32) HP_ARCH=hppa2.0n ;; + 64) HP_ARCH=hppa2.0w ;; + '') HP_ARCH=hppa2.0 ;; # HP-UX 10.20 + esac ;; + esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + + #define _HPUX_SOURCE + #include + #include + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS="" $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + test -z "$HP_ARCH" && HP_ARCH=hppa + fi ;; + esac + if [ ${HP_ARCH} = hppa2.0w ] + then + eval $set_cc_for_build + + # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating + # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler + # generating 64-bit code. GNU and HP use different nomenclature: + # + # $ CC_FOR_BUILD=cc ./config.guess + # => hppa2.0w-hp-hpux11.23 + # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | + grep -q __LP64__ + then + HP_ARCH=hppa2.0w + else + HP_ARCH=hppa64 + fi + fi + echo ${HP_ARCH}-hp-hpux${HPUX_REV} + exit ;; + ia64:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + echo ia64-hp-hpux${HPUX_REV} + exit ;; + 3050*:HI-UX:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } + echo unknown-hitachi-hiuxwe2 + exit ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) + echo hppa1.1-hp-bsd + exit ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) + echo hppa1.1-hp-osf + exit ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit ;; + i*86:OSF1:*:*) + if [ -x /usr/sbin/sysversion ] ; then + echo ${UNAME_MACHINE}-unknown-osf1mk + else + echo ${UNAME_MACHINE}-unknown-osf1 + fi + exit ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*[A-Z]90:*:*:*) + echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + *:UNICOS/mp:*:*) + echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz` + FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + 5000:UNIX_System_V:4.*:*) + FUJITSU_SYS=`uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/ /_/'` + echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} + exit ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:BSD/OS:*:*) + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit ;; + *:FreeBSD:*:*) + UNAME_PROCESSOR=`/usr/bin/uname -p` + case ${UNAME_PROCESSOR} in + amd64) + echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + *) + echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + esac + exit ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit ;; + *:MINGW64*:*) + echo ${UNAME_MACHINE}-pc-mingw64 + exit ;; + *:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit ;; + *:MSYS*:*) + echo ${UNAME_MACHINE}-pc-msys + exit ;; + i*:windows32*:*) + # uname -m includes "-pc" on this system. + echo ${UNAME_MACHINE}-mingw32 + exit ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit ;; + *:Interix*:*) + case ${UNAME_MACHINE} in + x86) + echo i586-pc-interix${UNAME_RELEASE} + exit ;; + authenticamd | genuineintel | EM64T) + echo x86_64-unknown-interix${UNAME_RELEASE} + exit ;; + IA64) + echo ia64-unknown-interix${UNAME_RELEASE} + exit ;; + esac ;; + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit ;; + 8664:Windows_NT:*) + echo x86_64-pc-mks + exit ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we + # UNAME_MACHINE based on the output of uname instead of i386? + echo i586-pc-interix + exit ;; + i*:UWIN*:*) + echo ${UNAME_MACHINE}-pc-uwin + exit ;; + amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) + echo x86_64-unknown-cygwin + exit ;; + p*:CYGWIN*:*) + echo powerpcle-unknown-cygwin + exit ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit ;; + *:GNU:*:*) + # the GNU system + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-${LIBC}`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit ;; + *:GNU/*:*:*) + # other systems with GNU libc and userland + echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr "[:upper:]" "[:lower:]"``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-${LIBC} + exit ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit ;; + aarch64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + aarch64_be:Linux:*:*) + UNAME_MACHINE=aarch64_be + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep -q ld.so.1 + if test "$?" = 0 ; then LIBC=gnulibc1 ; fi + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arc:Linux:*:* | arceb:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + arm*:Linux:*:*) + eval $set_cc_for_build + if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_EABI__ + then + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + else + if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep -q __ARM_PCS_VFP + then + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabi + else + echo ${UNAME_MACHINE}-unknown-linux-${LIBC}eabihf + fi + fi + exit ;; + avr32*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + cris:Linux:*:*) + echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + crisv32:Linux:*:*) + echo ${UNAME_MACHINE}-axis-linux-${LIBC} + exit ;; + e2k:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + frv:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + hexagon:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:Linux:*:*) + echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + ia64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + k1om:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m32r*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + m68*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + mips:Linux:*:* | mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef ${UNAME_MACHINE} + #undef ${UNAME_MACHINE}el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=${UNAME_MACHINE}el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=${UNAME_MACHINE} + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } + ;; + mips64el:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + openrisc*:Linux:*:*) + echo or1k-unknown-linux-${LIBC} + exit ;; + or32:Linux:*:* | or1k*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + padre:Linux:*:*) + echo sparc-unknown-linux-${LIBC} + exit ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-${LIBC} + exit ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in + PA7*) echo hppa1.1-unknown-linux-${LIBC} ;; + PA8*) echo hppa2.0-unknown-linux-${LIBC} ;; + *) echo hppa-unknown-linux-${LIBC} ;; + esac + exit ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-${LIBC} + exit ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-${LIBC} + exit ;; + ppc64le:Linux:*:*) + echo powerpc64le-unknown-linux-${LIBC} + exit ;; + ppcle:Linux:*:*) + echo powerpcle-unknown-linux-${LIBC} + exit ;; + riscv32:Linux:*:* | riscv64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo ${UNAME_MACHINE}-ibm-linux-${LIBC} + exit ;; + sh64*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sh*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + tile*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + vax:Linux:*:*) + echo ${UNAME_MACHINE}-dec-linux-${LIBC} + exit ;; + x86_64:Linux:*:*) + echo ${UNAME_MACHINE}-pc-linux-${LIBC} + exit ;; + xtensa*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo ${UNAME_MACHINE}-pc-os2-emx + exit ;; + i*86:XTS-300:*:STOP) + echo ${UNAME_MACHINE}-unknown-stop + exit ;; + i*86:atheos:*:*) + echo ${UNAME_MACHINE}-unknown-atheos + exit ;; + i*86:syllable:*:*) + echo ${UNAME_MACHINE}-pc-syllable + exit ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit ;; + i*86:*DOS:*:*) + echo ${UNAME_MACHINE}-pc-msdosdjgpp + exit ;; + i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) + UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} + else + echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} + fi + exit ;; + i*86:*:5:[678]*) + # UnixWare 7.x, OpenUNIX and OpenServer 6. + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} + exit ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then + UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo ${UNAME_MACHINE}-pc-sco$UNAME_REL + else + echo ${UNAME_MACHINE}-pc-sysv32 + fi + exit ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i586. + # Note: whatever this is, it MUST be the same as what config.sub + # prints for the "djgpp" host, or else GDB configure will decide that + # this is a cross-build. + echo i586-pc-msdosdjgpp + exit ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 + fi + exit ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit ;; + M68*:*:R3V[5678]*:*) + test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; + 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4; exit; } ;; + NCR*:*:4.2:* | MPRAS*:*:4.2:*) + OS_REL='.3' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } + /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos${UNAME_RELEASE} + exit ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv${UNAME_RELEASE} + exit ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=`(uname -p) 2>/dev/null` + echo ${UNAME_MACHINE}-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says + echo i586-unisys-sysv4 + exit ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit ;; + i*86:VOS:*:*) + # From Paul.Green@stratus.com. + echo ${UNAME_MACHINE}-stratus-vos + exit ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux${UNAME_RELEASE} + exit ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then + echo mips-nec-sysv${UNAME_RELEASE} + else + echo mips-unknown-sysv${UNAME_RELEASE} + fi + exit ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit ;; + BePC:Haiku:*:*) # Haiku running on Intel PC compatible. + echo i586-pc-haiku + exit ;; + x86_64:Haiku:*:*) + echo x86_64-unknown-haiku + exit ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux${UNAME_RELEASE} + exit ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux${UNAME_RELEASE} + exit ;; + SX-7:SUPER-UX:*:*) + echo sx7-nec-superux${UNAME_RELEASE} + exit ;; + SX-8:SUPER-UX:*:*) + echo sx8-nec-superux${UNAME_RELEASE} + exit ;; + SX-8R:SUPER-UX:*:*) + echo sx8r-nec-superux${UNAME_RELEASE} + exit ;; + SX-ACE:SUPER-UX:*:*) + echo sxace-nec-superux${UNAME_RELEASE} + exit ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Rhapsody:*:*) + echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} + exit ;; + *:Darwin:*:*) + UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown + eval $set_cc_for_build + if test "$UNAME_PROCESSOR" = unknown ; then + UNAME_PROCESSOR=powerpc + fi + if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then + if [ "$CC_FOR_BUILD" != no_compiler_found ]; then + if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + case $UNAME_PROCESSOR in + i386) UNAME_PROCESSOR=x86_64 ;; + powerpc) UNAME_PROCESSOR=powerpc64 ;; + esac + fi + fi + elif test "$UNAME_PROCESSOR" = i386 ; then + # Avoid executing cc on OS X 10.9, as it ships with a stub + # that puts up a graphical alert prompting to install + # developer tools. Any system running Mac OS X 10.7 or + # later (Darwin 11 and later) is required to have a 64-bit + # processor. This is not true of the ARM version of Darwin + # that Apple uses in portable devices. + UNAME_PROCESSOR=x86_64 + fi + echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} + exit ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=`uname -p` + if test "$UNAME_PROCESSOR" = x86; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} + exit ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit ;; + NEO-?:NONSTOP_KERNEL:*:*) + echo neo-tandem-nsk${UNAME_RELEASE} + exit ;; + NSE-*:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; + NSR-?:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk${UNAME_RELEASE} + exit ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit ;; + DS/*:UNIX_System_V:*:*) + echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} + exit ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + if test "$cputype" = 386; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo ${UNAME_MACHINE}-unknown-plan9 + exit ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit ;; + SEI:*:*:SEIUX) + echo mips-sei-seiux${UNAME_RELEASE} + exit ;; + *:DragonFly:*:*) + echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` + exit ;; + *:*VMS:*:*) + UNAME_MACHINE=`(uname -p) 2>/dev/null` + case "${UNAME_MACHINE}" in + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; + V*) echo vax-dec-vms ; exit ;; + esac ;; + *:XENIX:*:SysV) + echo i386-pc-xenix + exit ;; + i*86:skyos:*:*) + echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE} | sed -e 's/ .*$//'` + exit ;; + i*86:rdos:*:*) + echo ${UNAME_MACHINE}-pc-rdos + exit ;; + i*86:AROS:*:*) + echo ${UNAME_MACHINE}-pc-aros + exit ;; + x86_64:VMkernel:*:*) + echo ${UNAME_MACHINE}-unknown-esx + exit ;; + amd64:Isilon\ OneFS:*:*) + echo x86_64-unknown-onefs + exit ;; +esac + +cat >&2 </dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null` + +hostinfo = `(hostinfo) 2>/dev/null` +/bin/universe = `(/bin/universe) 2>/dev/null` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` +/bin/arch = `(/bin/arch) 2>/dev/null` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` + +UNAME_MACHINE = ${UNAME_MACHINE} +UNAME_RELEASE = ${UNAME_RELEASE} +UNAME_SYSTEM = ${UNAME_SYSTEM} +UNAME_VERSION = ${UNAME_VERSION} +EOF + +exit 1 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/config.h.in +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/config.h.in @@ -0,0 +1,25 @@ +/* config.h.in. Generated from configure.ac by autoheader. */ + +/* Name of package */ +#undef PACKAGE + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the home page for this package. */ +#undef PACKAGE_URL + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION + +/* Version number of package */ +#undef VERSION --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/config.sub +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/config.sub @@ -0,0 +1,1825 @@ +#! /bin/sh +# Configuration validation subroutine script. +# Copyright 1992-2016 Free Software Foundation, Inc. + +timestamp='2016-11-04' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see . +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that +# program. This Exception is an additional permission under section 7 +# of the GNU General Public License, version 3 ("GPLv3"). + + +# Please send patches to . +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# You can get the latest version of this script from: +# http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS + +Canonicalize a configuration name. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.sub ($timestamp) + +Copyright 1992-2016 Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit ;; + --version | -v ) + echo "$version" ; exit ;; + --help | --h* | -h ) + echo "$usage"; exit ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo $1 + exit ;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \ + linux-musl* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \ + knetbsd*-gnu* | netbsd*-gnu* | netbsd*-eabi* | \ + kopensolaris*-gnu* | cloudabi*-eabi* | \ + storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + android-linux) + os=-linux-android + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`-unknown + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple | -axis | -knuth | -cray | -microblaze*) + os= + basic_machine=$1 + ;; + -bluegene*) + os=-cnk + ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 + ;; + -scout) + ;; + -wrs) + os=-vxworks + basic_machine=$1 + ;; + -chorusos*) + os=-chorusos + basic_machine=$1 + ;; + -chorusrdb) + os=-chorusrdb + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco6) + os=-sco5v6 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco5v6*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -udk*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*178) + os=-lynxos178 + ;; + -lynx*5) + os=-lynxos5 + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; + -mint | -mint[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ + | aarch64 | aarch64_be \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ + | arc | arceb \ + | arm | arm[bl]e | arme[lb] | armv[2-8] | armv[3-8][lb] | armv7[arm] \ + | avr | avr32 \ + | ba \ + | be32 | be64 \ + | bfin \ + | c4x | c8051 | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | e2k | epiphany \ + | fido | fr30 | frv | ft32 \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | hexagon \ + | i370 | i860 | i960 | ia64 \ + | ip2k | iq2000 \ + | k1om \ + | le32 | le64 \ + | lm32 \ + | m32c | m32r | m32rle | m68000 | m68k | m88k \ + | maxq | mb | microblaze | microblazeel | mcore | mep | metag \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ + | mips64octeon | mips64octeonel \ + | mips64orion | mips64orionel \ + | mips64r5900 | mips64r5900el \ + | mips64vr | mips64vrel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mips64vr5900 | mips64vr5900el \ + | mipsisa32 | mipsisa32el \ + | mipsisa32r2 | mipsisa32r2el \ + | mipsisa32r6 | mipsisa32r6el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64r6 | mipsisa64r6el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipsr5900 | mipsr5900el \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | moxie \ + | mt \ + | msp430 \ + | nds32 | nds32le | nds32be \ + | nios | nios2 | nios2eb | nios2el \ + | ns16k | ns32k \ + | open8 | or1k | or1knd | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle \ + | pru \ + | pyramid \ + | riscv32 | riscv64 \ + | rl78 | rx \ + | score \ + | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ + | spu \ + | tahoe | tic4x | tic54x | tic55x | tic6x | tic80 | tron \ + | ubicom32 \ + | v850 | v850e | v850e1 | v850e2 | v850es | v850e2v3 \ + | visium \ + | we32k \ + | x86 | xc16x | xstormy16 | xtensa \ + | z8k | z80) + basic_machine=$basic_machine-unknown + ;; + c54x) + basic_machine=tic54x-unknown + ;; + c55x) + basic_machine=tic55x-unknown + ;; + c6x) + basic_machine=tic6x-unknown + ;; + leon|leon[3-9]) + basic_machine=sparc-$basic_machine + ;; + m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x | nvptx | picochip) + basic_machine=$basic_machine-unknown + os=-none + ;; + m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) + ;; + ms1) + basic_machine=mt-unknown + ;; + + strongarm | thumb | xscale) + basic_machine=arm-unknown + ;; + xgate) + basic_machine=$basic_machine-unknown + os=-none + ;; + xscaleeb) + basic_machine=armeb-unknown + ;; + + xscaleel) + basic_machine=armel-unknown + ;; + + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ + | aarch64-* | aarch64_be-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* | arceb-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* | avr32-* \ + | ba-* \ + | be32-* | be64-* \ + | bfin-* | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* \ + | c8051-* | clipper-* | craynv-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | e2k-* | elxsi-* \ + | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ + | hexagon-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* | iq2000-* \ + | k1om-* \ + | le32-* | le64-* \ + | lm32-* \ + | m32c-* | m32r-* | m32rle-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ + | microblaze-* | microblazeel-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ + | mips64octeon-* | mips64octeonel-* \ + | mips64orion-* | mips64orionel-* \ + | mips64r5900-* | mips64r5900el-* \ + | mips64vr-* | mips64vrel-* \ + | mips64vr4100-* | mips64vr4100el-* \ + | mips64vr4300-* | mips64vr4300el-* \ + | mips64vr5000-* | mips64vr5000el-* \ + | mips64vr5900-* | mips64vr5900el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa32r2-* | mipsisa32r2el-* \ + | mipsisa32r6-* | mipsisa32r6el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64r2-* | mipsisa64r2el-* \ + | mipsisa64r6-* | mipsisa64r6el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ + | mipsr5900-* | mipsr5900el-* \ + | mipstx39-* | mipstx39el-* \ + | mmix-* \ + | mt-* \ + | msp430-* \ + | nds32-* | nds32le-* | nds32be-* \ + | nios-* | nios2-* | nios2eb-* | nios2el-* \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | open8-* \ + | or1k*-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ + | pru-* \ + | pyramid-* \ + | riscv32-* | riscv64-* \ + | rl78-* | romp-* | rs6000-* | rx-* \ + | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ + | sparclite-* \ + | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx*-* \ + | tahoe-* \ + | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ + | tile*-* \ + | tron-* \ + | ubicom32-* \ + | v850-* | v850e-* | v850e1-* | v850es-* | v850e2-* | v850e2v3-* \ + | vax-* \ + | visium-* \ + | we32k-* \ + | x86-* | x86_64-* | xc16x-* | xps100-* \ + | xstormy16-* | xtensa*-* \ + | ymp-* \ + | z8k-* | z80-*) + ;; + # Recognize the basic CPU types without company name, with glob match. + xtensa*) + basic_machine=$basic_machine-unknown + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 386bsd) + basic_machine=i386-unknown + os=-bsd + ;; + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + a29khif) + basic_machine=a29k-amd + os=-udi + ;; + abacus) + basic_machine=abacus-unknown + ;; + adobe68k) + basic_machine=m68010-adobe + os=-scout + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amd64) + basic_machine=x86_64-pc + ;; + amd64-*) + basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-unknown + ;; + amigaos | amigados) + basic_machine=m68k-unknown + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + os=-bsd + ;; + aros) + basic_machine=i386-pc + os=-aros + ;; + asmjs) + basic_machine=asmjs-unknown + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + blackfin) + basic_machine=bfin-unknown + os=-linux + ;; + blackfin-*) + basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + bluegene*) + basic_machine=powerpc-ibm + os=-cnk + ;; + c54x-*) + basic_machine=tic54x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c55x-*) + basic_machine=tic55x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c6x-*) + basic_machine=tic6x-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; + cegcc) + basic_machine=arm-unknown + os=-cegcc + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | j90) + basic_machine=j90-cray + os=-unicos + ;; + craynv) + basic_machine=craynv-cray + os=-unicosmp + ;; + cr16 | cr16-*) + basic_machine=cr16-unknown + os=-elf + ;; + crds | unos) + basic_machine=m68k-crds + ;; + crisv32 | crisv32-* | etraxfs*) + basic_machine=crisv32-axis + ;; + cris | cris-* | etrax*) + basic_machine=cris-axis + ;; + crx) + basic_machine=crx-unknown + os=-elf + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + decsystem10* | dec10*) + basic_machine=pdp10-dec + os=-tops10 + ;; + decsystem20* | dec20*) + basic_machine=pdp10-dec + os=-tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dicos) + basic_machine=i686-pc + os=-dicos + ;; + djgpp) + basic_machine=i586-pc + os=-msdosdjgpp + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + e500v[12]) + basic_machine=powerpc-unknown + os=$os"spe" + ;; + e500v[12]-*) + basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + os=$os"spe" + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + os=-ose + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + go32) + basic_machine=i386-pc + os=-go32 + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + h8300xray) + basic_machine=h8300-hitachi + os=-xray + ;; + h8500hms) + basic_machine=h8500-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + hppaosf) + basic_machine=hppa1.1-hp + os=-osf + ;; + hppro) + basic_machine=hppa1.1-hp + os=-proelf + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i*86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i*86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i*86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + i386mach) + basic_machine=i386-mach + os=-mach + ;; + i386-vsta | vsta) + basic_machine=i386-unknown + os=-vsta + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + leon-*|leon[3-9]-*) + basic_machine=sparc-`echo $basic_machine | sed 's/-.*//'` + ;; + m68knommu) + basic_machine=m68k-unknown + os=-linux + ;; + m68knommu-*) + basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + microblaze*) + basic_machine=microblaze-xilinx + ;; + mingw64) + basic_machine=x86_64-pc + os=-mingw64 + ;; + mingw32) + basic_machine=i686-pc + os=-mingw32 + ;; + mingw32ce) + basic_machine=arm-unknown + os=-mingw32ce + ;; + miniframe) + basic_machine=m68000-convergent + ;; + *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + monitor) + basic_machine=m68k-rom68k + os=-coff + ;; + morphos) + basic_machine=powerpc-unknown + os=-morphos + ;; + moxiebox) + basic_machine=moxie-unknown + os=-moxiebox + ;; + msdos) + basic_machine=i386-pc + os=-msdos + ;; + ms1-*) + basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` + ;; + msys) + basic_machine=i686-pc + os=-msys + ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; + nacl) + basic_machine=le32-unknown + os=-nacl + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + netbsd386) + basic_machine=i386-unknown + os=-netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + os=-linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + necv70) + basic_machine=v70-nec + os=-sysv + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + mon960) + basic_machine=i960-intel + os=-mon960 + ;; + nonstopux) + basic_machine=mips-compaq + os=-nonstopux + ;; + np1) + basic_machine=np1-gould + ;; + neo-tandem) + basic_machine=neo-tandem + ;; + nse-tandem) + basic_machine=nse-tandem + ;; + nsr-tandem) + basic_machine=nsr-tandem + ;; + op50n-* | op60c-*) + basic_machine=hppa1.1-oki + os=-proelf + ;; + openrisc | openrisc-*) + basic_machine=or32-unknown + ;; + os400) + basic_machine=powerpc-ibm + os=-os400 + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + os=-ose + ;; + os68k) + basic_machine=m68k-none + os=-os68k + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + parisc) + basic_machine=hppa-unknown + os=-linux + ;; + parisc-*) + basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'` + os=-linux + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pc98) + basic_machine=i386-pc + ;; + pc98-*) + basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium | p5 | k5 | k6 | nexgen | viac3) + basic_machine=i586-pc + ;; + pentiumpro | p6 | 6x86 | athlon | athlon_*) + basic_machine=i686-pc + ;; + pentiumii | pentium2 | pentiumiii | pentium3) + basic_machine=i686-pc + ;; + pentium4) + basic_machine=i786-pc + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentium4-*) + basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=power-ibm + ;; + ppc | ppcbe) basic_machine=powerpc-unknown + ;; + ppc-* | ppcbe-*) + basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64) basic_machine=powerpc64-unknown + ;; + ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64le | powerpc64little) + basic_machine=powerpc64le-unknown + ;; + ppc64le-* | powerpc64little-*) + basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + pw32) + basic_machine=i586-unknown + os=-pw32 + ;; + rdos | rdos64) + basic_machine=x86_64-pc + os=-rdos + ;; + rdos32) + basic_machine=i386-pc + os=-rdos + ;; + rom68k) + basic_machine=m68k-rom68k + os=-coff + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + s390 | s390-*) + basic_machine=s390-ibm + ;; + s390x | s390x-*) + basic_machine=s390x-ibm + ;; + sa29200) + basic_machine=a29k-amd + os=-udi + ;; + sb1) + basic_machine=mipsisa64sb1-unknown + ;; + sb1el) + basic_machine=mipsisa64sb1el-unknown + ;; + sde) + basic_machine=mipsisa32-sde + os=-elf + ;; + sei) + basic_machine=mips-sei + os=-seiux + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sh5el) + basic_machine=sh5le-unknown + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparclite-wrs | simso-wrs) + basic_machine=sparclite-wrs + os=-vxworks + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + st2000) + basic_machine=m68k-tandem + ;; + stratus) + basic_machine=i860-stratus + os=-sysv4 + ;; + strongarm-* | thumb-*) + basic_machine=arm-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + sv1) + basic_machine=sv1-cray + os=-unicos + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + t3e) + basic_machine=alphaev5-cray + os=-unicos + ;; + t90) + basic_machine=t90-cray + os=-unicos + ;; + tile*) + basic_machine=$basic_machine-unknown + os=-linux-gnu + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + toad1) + basic_machine=pdp10-xkl + os=-tops20 + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + tpf) + basic_machine=s390x-ibm + os=-tpf + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + os=-none + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + w65*) + basic_machine=w65-wdc + os=-none + ;; + w89k-*) + basic_machine=hppa1.1-winbond + os=-proelf + ;; + xbox) + basic_machine=i686-pc + os=-mingw32 + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + xscale-* | xscalee[bl]-*) + basic_machine=`echo $basic_machine | sed 's/^xscale/arm/'` + ;; + ymp) + basic_machine=ymp-cray + os=-unicos + ;; + z8k-*-coff) + basic_machine=z8k-unknown + os=-sim + ;; + z80-*-coff) + basic_machine=z80-unknown + os=-sim + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + w89k) + basic_machine=hppa1.1-winbond + ;; + op50n) + basic_machine=hppa1.1-oki + ;; + op60c) + basic_machine=hppa1.1-oki + ;; + romp) + basic_machine=romp-ibm + ;; + mmix) + basic_machine=mmix-knuth + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp10) + # there are many clones, so DEC is not a safe bet + basic_machine=pdp10-unknown + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sh[1234] | sh[24]a | sh[24]aeb | sh[34]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + mac | mpw | mac-mpw) + basic_machine=m68k-apple + ;; + pmac | pmac-mpw) + basic_machine=powerpc-apple + ;; + *-unknown) + # Make sure to match an already-canonicalized machine name. + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -auroraux) + os=-auroraux + ;; + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -cnk* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -auroraux* | -solaris* \ + | -sym* | -kopensolaris* | -plan9* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* | -aros* | -cloudabi* | -sortix* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ + | -bitrig* | -openbsd* | -solidbsd* | -libertybsd* \ + | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ + | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* | -cegcc* \ + | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -midipix* | -mingw32* | -mingw64* | -linux-gnu* | -linux-android* \ + | -linux-newlib* | -linux-musl* | -linux-uclibc* \ + | -uxpv* | -beos* | -mpeix* | -udk* | -moxiebox* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ + | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ + | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* \ + | -onefs* | -tirtos* | -phoenix* | -fuchsia*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) + case $basic_machine in + x86-* | i*86-*) + ;; + *) + os=-nto$os + ;; + esac + ;; + -nto-qnx*) + ;; + -nto*) + os=`echo $os | sed -e 's|nto|nto-qnx|'` + ;; + -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ + | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) + ;; + -mac*) + os=`echo $os | sed -e 's|mac|macos|'` + ;; + -linux-dietlibc) + os=-linux-dietlibc + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -opened*) + os=-openedition + ;; + -os400*) + os=-os400 + ;; + -wince*) + os=-wince + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -atheos*) + os=-atheos + ;; + -syllable*) + os=-syllable + ;; + -386bsd) + os=-bsd + ;; + -ctix* | -uts*) + os=-sysv + ;; + -nova*) + os=-rtmk-nova + ;; + -ns2 ) + os=-nextstep2 + ;; + -nsk*) + os=-nsk + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -tpf*) + os=-tpf + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -ose*) + os=-ose + ;; + -es1800*) + os=-ose + ;; + -xenix) + os=-xenix + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + os=-mint + ;; + -aros*) + os=-aros + ;; + -zvmoe) + os=-zvmoe + ;; + -dicos*) + os=-dicos + ;; + -nacl*) + ;; + -ios) + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + score-*) + os=-elf + ;; + spu-*) + os=-elf + ;; + *-acorn) + os=-riscix1.2 + ;; + arm*-rebel) + os=-linux + ;; + arm*-semi) + os=-aout + ;; + c4x-* | tic4x-*) + os=-coff + ;; + c8051-*) + os=-elf + ;; + hexagon-*) + os=-elf + ;; + tic54x-*) + os=-coff + ;; + tic55x-*) + os=-coff + ;; + tic6x-*) + os=-coff + ;; + # This must come before the *-dec entry. + pdp10-*) + os=-tops20 + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + ;; + m68*-cisco) + os=-aout + ;; + mep-*) + os=-elf + ;; + mips*-cisco) + os=-elf + ;; + mips*-*) + os=-elf + ;; + or32-*) + os=-coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-be) + os=-beos + ;; + *-haiku) + os=-haiku + ;; + *-ibm) + os=-aix + ;; + *-knuth) + os=-mmixware + ;; + *-wec) + os=-proelf + ;; + *-winbond) + os=-proelf + ;; + *-oki) + os=-proelf + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=-uxpv + ;; + *-rom68k) + os=-coff + ;; + *-*bug) + os=-coff + ;; + *-apple) + os=-macos + ;; + *-atari*) + os=-mint + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -cnk*|-aix*) + vendor=ibm + ;; + -beos*) + vendor=be + ;; + -hpux*) + vendor=hp + ;; + -mpeix*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs* | -opened*) + vendor=ibm + ;; + -os400*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -tpf*) + vendor=ibm + ;; + -vxsim* | -vxworks* | -windiss*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -hms*) + vendor=hitachi + ;; + -mpw* | -macos*) + vendor=apple + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + vendor=atari + ;; + -vos*) + vendor=stratus + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os +exit + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/configure +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/configure @@ -0,0 +1,17418 @@ +#! /bin/sh +# From configure.ac Revision. +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.69 for avr-libc 2.0.0. +# +# Report bugs to . +# +# +# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. +# +# +# This configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +as_myself= +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + +# Use a proper internal environment variable to ensure we don't fall + # into an infinite loop, continuously re-executing ourselves. + if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then + _as_can_reexec=no; export _as_can_reexec; + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +as_fn_exit 255 + fi + # We don't want this to propagate to other subprocesses. + { _as_can_reexec=; unset _as_can_reexec;} +if test "x$CONFIG_SHELL" = x; then + as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which + # is contrary to our usage. Disable this feature. + alias -g '\${1+\"\$@\"}'='\"\$@\"' + setopt NO_GLOB_SUBST +else + case \`(set -o) 2>/dev/null\` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi +" + as_required="as_fn_return () { (exit \$1); } +as_fn_success () { as_fn_return 0; } +as_fn_failure () { as_fn_return 1; } +as_fn_ret_success () { return 0; } +as_fn_ret_failure () { return 1; } + +exitcode=0 +as_fn_success || { exitcode=1; echo as_fn_success failed.; } +as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } +as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } +as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } +if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : + +else + exitcode=1; echo positional parameters were not saved. +fi +test x\$exitcode = x0 || exit 1 +test -x / || exit 1" + as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO + as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO + eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && + test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1" + if (eval "$as_required") 2>/dev/null; then : + as_have_required=yes +else + as_have_required=no +fi + if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : + +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +as_found=false +for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + as_found=: + case $as_dir in #( + /*) + for as_base in sh bash ksh sh5; do + # Try only shells that exist, to save several forks. + as_shell=$as_dir/$as_base + if { test -f "$as_shell" || test -f "$as_shell.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : + CONFIG_SHELL=$as_shell as_have_required=yes + if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : + break 2 +fi +fi + done;; + esac + as_found=false +done +$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && + { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : + CONFIG_SHELL=$SHELL as_have_required=yes +fi; } +IFS=$as_save_IFS + + + if test "x$CONFIG_SHELL" != x; then : + export CONFIG_SHELL + # We cannot yet assume a decent shell, so we have to provide a +# neutralization value for shells without unset; and this also +# works around shells that cannot unset nonexistent variables. +# Preserve -v and -x to the replacement shell. +BASH_ENV=/dev/null +ENV=/dev/null +(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV +case $- in # (((( + *v*x* | *x*v* ) as_opts=-vx ;; + *v* ) as_opts=-v ;; + *x* ) as_opts=-x ;; + * ) as_opts= ;; +esac +exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} +# Admittedly, this is quite paranoid, since all the known shells bail +# out after a failed `exec'. +$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 +exit 255 +fi + + if test x$as_have_required = xno; then : + $as_echo "$0: This script requires a shell more modern than all" + $as_echo "$0: the shells that I found on your system." + if test x${ZSH_VERSION+set} = xset ; then + $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" + $as_echo "$0: be upgraded to zsh 4.3.4 or later." + else + $as_echo "$0: Please tell bug-autoconf@gnu.org and +$0: avr-libc-dev@nongnu.org about your system, including +$0: any error possibly output before this message. Then +$0: install a modern shell, or manually run the script +$0: under such a shell if you do have one." + fi + exit 1 +fi +fi +fi +SHELL=${CONFIG_SHELL-/bin/sh} +export SHELL +# Unset more variables known to interfere with behavior of common tools. +CLICOLOR_FORCE= GREP_OPTIONS= +unset CLICOLOR_FORCE GREP_OPTIONS + +## --------------------- ## +## M4sh Shell Functions. ## +## --------------------- ## +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" + + +} # as_fn_mkdir_p + +# as_fn_executable_p FILE +# ----------------------- +# Test if FILE is an executable regular file. +as_fn_executable_p () +{ + test -f "$1" && test -x "$1" +} # as_fn_executable_p +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +# as_fn_error STATUS ERROR [LINENO LOG_FD] +# ---------------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with STATUS, using 1 if that was 0. +as_fn_error () +{ + as_status=$1; test $as_status -eq 0 && as_status=1 + if test "$4"; then + as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + fi + $as_echo "$as_me: error: $2" >&2 + as_fn_exit $as_status +} # as_fn_error + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + + + as_lineno_1=$LINENO as_lineno_1a=$LINENO + as_lineno_2=$LINENO as_lineno_2a=$LINENO + eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && + test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { + # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) + sed -n ' + p + /[$]LINENO/= + ' <$as_myself | + sed ' + s/[$]LINENO.*/&-/ + t lineno + b + :lineno + N + :loop + s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ + t loop + s/-\n.*// + ' >$as_me.lineno && + chmod +x "$as_me.lineno" || + { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } + + # If we had to re-execute with $CONFIG_SHELL, we're ensured to have + # already done that, so ensure we don't try to do so again and fall + # in an infinite loop. This has already happened in practice. + _as_can_reexec=no; export _as_can_reexec + # Don't try to exec as it changes $[0], causing all sort of problems + # (the dirname of $[0] is not the place where we might find the + # original and so on. Autoconf is especially sensitive to this). + . "./$as_me.lineno" + # Exit status is that of the last command. + exit +} + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -pR'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -pR' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -pR' + fi +else + as_ln_s='cp -pR' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + +as_test_x='test -x' +as_executable_p=as_fn_executable_p + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + +as_awk_strverscmp=' + # Use only awk features that work with 7th edition Unix awk (1978). + # My, what an old awk you have, Mr. Solaris! + END { + while (length(v1) && length(v2)) { + # Set d1 to be the next thing to compare from v1, and likewise for d2. + # Normally this is a single character, but if v1 and v2 contain digits, + # compare them as integers and fractions as strverscmp does. + if (v1 ~ /^[0-9]/ && v2 ~ /^[0-9]/) { + # Split v1 and v2 into their leading digit string components d1 and d2, + # and advance v1 and v2 past the leading digit strings. + for (len1 = 1; substr(v1, len1 + 1) ~ /^[0-9]/; len1++) continue + for (len2 = 1; substr(v2, len2 + 1) ~ /^[0-9]/; len2++) continue + d1 = substr(v1, 1, len1); v1 = substr(v1, len1 + 1) + d2 = substr(v2, 1, len2); v2 = substr(v2, len2 + 1) + if (d1 ~ /^0/) { + if (d2 ~ /^0/) { + # Compare two fractions. + while (d1 ~ /^0/ && d2 ~ /^0/) { + d1 = substr(d1, 2); len1-- + d2 = substr(d2, 2); len2-- + } + if (len1 != len2 && ! (len1 && len2 && substr(d1, 1, 1) == substr(d2, 1, 1))) { + # The two components differ in length, and the common prefix + # contains only leading zeros. Consider the longer to be less. + d1 = -len1 + d2 = -len2 + } else { + # Otherwise, compare as strings. + d1 = "x" d1 + d2 = "x" d2 + } + } else { + # A fraction is less than an integer. + exit 1 + } + } else { + if (d2 ~ /^0/) { + # An integer is greater than a fraction. + exit 2 + } else { + # Compare two integers. + d1 += 0 + d2 += 0 + } + } + } else { + # The normal case, without worrying about digits. + d1 = substr(v1, 1, 1); v1 = substr(v1, 2) + d2 = substr(v2, 1, 1); v2 = substr(v2, 2) + } + if (d1 < d2) exit 1 + if (d1 > d2) exit 2 + } + # Beware Solaris /usr/xgp4/bin/awk (at least through Solaris 10), + # which mishandles some comparisons of empty strings to integers. + if (length(v2)) exit 1 + if (length(v1)) exit 2 + } +' + +test -n "$DJDIR" || exec 7<&0 &1 + +# Name of the host. +# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, +# so uname gets run too. +ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` + +# +# Initializations. +# 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It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + + done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5 +$as_echo_n "checking whether build environment is sane... " >&6; } +# Reject unsafe characters in $srcdir or the absolute working directory +# name. Accept space and tab only in the latter. +am_lf=' +' +case `pwd` in + *[\\\"\#\$\&\'\`$am_lf]*) + as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5;; +esac +case $srcdir in + *[\\\"\#\$\&\'\`$am_lf\ \ ]*) + as_fn_error $? "unsafe srcdir value: '$srcdir'" "$LINENO" 5;; +esac + +# Do 'set' in a subshell so we don't clobber the current shell's +# arguments. Must try -L first in case configure is actually a +# symlink; some systems play weird games with the mod time of symlinks +# (eg FreeBSD returns the mod time of the symlink's containing +# directory). +if ( + am_has_slept=no + for am_try in 1 2; do + echo "timestamp, slept: $am_has_slept" > conftest.file + set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` + if test "$*" = "X"; then + # -L didn't work. + set X `ls -t "$srcdir/configure" conftest.file` + fi + if test "$*" != "X $srcdir/configure conftest.file" \ + && test "$*" != "X conftest.file $srcdir/configure"; then + + # If neither matched, then we have a broken ls. This can happen + # if, for instance, CONFIG_SHELL is bash and it inherits a + # broken ls alias from the environment. This has actually + # happened. Such a system could not be considered "sane". + as_fn_error $? "ls -t appears to fail. Make sure there is not a broken + alias in your environment" "$LINENO" 5 + fi + if test "$2" = conftest.file || test $am_try -eq 2; then + break + fi + # Just in case. + sleep 1 + am_has_slept=yes + done + test "$2" = conftest.file + ) +then + # Ok. + : +else + as_fn_error $? "newly created file is older than distributed files! +Check your system clock" "$LINENO" 5 +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +# If we didn't sleep, we still need to ensure time stamps of config.status and +# generated files are strictly newer. +am_sleep_pid= +if grep 'slept: no' conftest.file >/dev/null 2>&1; then + ( sleep 1 ) & + am_sleep_pid=$! +fi + +rm -f conftest.file + +test "$program_prefix" != NONE && + program_transform_name="s&^&$program_prefix&;$program_transform_name" +# Use a double $ so make ignores it. +test "$program_suffix" != NONE && + program_transform_name="s&\$&$program_suffix&;$program_transform_name" +# Double any \ or $. +# By default was `s,x,x', remove it if useless. +ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' +program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` + +# Expand $ac_aux_dir to an absolute path. +am_aux_dir=`cd "$ac_aux_dir" && pwd` + +if test x"${MISSING+set}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; + *) + MISSING="\${SHELL} $am_aux_dir/missing" ;; + esac +fi +# Use eval to expand $SHELL +if eval "$MISSING --is-lightweight"; then + am_missing_run="$MISSING " +else + am_missing_run= + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: 'missing' script is too old or missing" >&5 +$as_echo "$as_me: WARNING: 'missing' script is too old or missing" >&2;} +fi + +if test x"${install_sh+set}" != xset; then + case $am_aux_dir in + *\ * | *\ *) + install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; + *) + install_sh="\${SHELL} $am_aux_dir/install-sh" + esac +fi + +# Installed binaries are usually stripped using 'strip' when the user +# run "make install-strip". However 'strip' might not be the right +# tool to use in cross-compilation environments, therefore Automake +# will honor the 'STRIP' environment variable to overrule this program. +if test "$cross_compiling" != no; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. +set dummy ${ac_tool_prefix}strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$STRIP"; then + ac_cv_prog_STRIP="$STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_STRIP="${ac_tool_prefix}strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +STRIP=$ac_cv_prog_STRIP +if test -n "$STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 +$as_echo "$STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_STRIP"; then + ac_ct_STRIP=$STRIP + # Extract the first word of "strip", so it can be a program name with args. +set dummy strip; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_STRIP+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_STRIP"; then + ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_STRIP="strip" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP +if test -n "$ac_ct_STRIP"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 +$as_echo "$ac_ct_STRIP" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_STRIP" = x; then + STRIP=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + STRIP=$ac_ct_STRIP + fi +else + STRIP="$ac_cv_prog_STRIP" +fi + +fi +INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5 +$as_echo_n "checking for a thread-safe mkdir -p... " >&6; } +if test -z "$MKDIR_P"; then + if ${ac_cv_path_mkdir+:} false; then : + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/opt/sfw/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in mkdir gmkdir; do + for ac_exec_ext in '' $ac_executable_extensions; do + as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext" || continue + case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #( + 'mkdir (GNU coreutils) '* | \ + 'mkdir (coreutils) '* | \ + 'mkdir (fileutils) '4.1*) + ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext + break 3;; + esac + done + done + done +IFS=$as_save_IFS + +fi + + test -d ./--version && rmdir ./--version + if test "${ac_cv_path_mkdir+set}" = set; then + MKDIR_P="$ac_cv_path_mkdir -p" + else + # As a last resort, use the slow shell script. Don't cache a + # value for MKDIR_P within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + MKDIR_P="$ac_install_sh -d" + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5 +$as_echo "$MKDIR_P" >&6; } + +for ac_prog in gawk mawk nawk awk +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_AWK+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AWK"; then + ac_cv_prog_AWK="$AWK" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_AWK="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AWK=$ac_cv_prog_AWK +if test -n "$AWK"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 +$as_echo "$AWK" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$AWK" && break +done + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 +$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; } +set x ${MAKE-make} +ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` +if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat >conftest.make <<\_ACEOF +SHELL = /bin/sh +all: + @echo '@@@%%%=$(MAKE)=@@@%%%' +_ACEOF +# GNU make sometimes prints "make[1]: Entering ...", which would confuse us. +case `${MAKE-make} -f conftest.make 2>/dev/null` in + *@@@%%%=?*=@@@%%%*) + eval ac_cv_prog_make_${ac_make}_set=yes;; + *) + eval ac_cv_prog_make_${ac_make}_set=no;; +esac +rm -f conftest.make +fi +if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + SET_MAKE= +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + SET_MAKE="MAKE=${MAKE-make}" +fi + +rm -rf .tst 2>/dev/null +mkdir .tst 2>/dev/null +if test -d .tst; then + am__leading_dot=. +else + am__leading_dot=_ +fi +rmdir .tst 2>/dev/null + +# Check whether --enable-silent-rules was given. +if test "${enable_silent_rules+set}" = set; then : + enableval=$enable_silent_rules; +fi + +case $enable_silent_rules in # ((( + yes) AM_DEFAULT_VERBOSITY=0;; + no) AM_DEFAULT_VERBOSITY=1;; + *) AM_DEFAULT_VERBOSITY=1;; +esac +am_make=${MAKE-make} +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $am_make supports nested variables" >&5 +$as_echo_n "checking whether $am_make supports nested variables... " >&6; } +if ${am_cv_make_support_nested_variables+:} false; then : + $as_echo_n "(cached) " >&6 +else + if $as_echo 'TRUE=$(BAR$(V)) +BAR0=false +BAR1=true +V=1 +am__doit: + @$(TRUE) +.PHONY: am__doit' | $am_make -f - >/dev/null 2>&1; then + am_cv_make_support_nested_variables=yes +else + am_cv_make_support_nested_variables=no +fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_make_support_nested_variables" >&5 +$as_echo "$am_cv_make_support_nested_variables" >&6; } +if test $am_cv_make_support_nested_variables = yes; then + AM_V='$(V)' + AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' +else + AM_V=$AM_DEFAULT_VERBOSITY + AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY +fi +AM_BACKSLASH='\' + +if test "`cd $srcdir && pwd`" != "`pwd`"; then + # Use -I$(srcdir) only when $(srcdir) != ., so that make's output + # is not polluted with repeated "-I." + am__isrc=' -I$(srcdir)' + # test to see if srcdir already configured + if test -f $srcdir/config.status; then + as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 + fi +fi + +# test whether we have cygpath +if test -z "$CYGPATH_W"; then + if (cygpath --version) >/dev/null 2>/dev/null; then + CYGPATH_W='cygpath -w' + else + CYGPATH_W=echo + fi +fi + + +# Define the identity of the package. + PACKAGE='avr-libc' + VERSION='2.0.0' + + +cat >>confdefs.h <<_ACEOF +#define PACKAGE "$PACKAGE" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define VERSION "$VERSION" +_ACEOF + +# Some tools Automake needs. + +ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"} + + +AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"} + + +AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"} + + +AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} + + +MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} + +# For better backward compatibility. To be removed once Automake 1.9.x +# dies out for good. For more background, see: +# +# +mkdir_p='$(MKDIR_P)' + +# We need awk for the "check" target (and possibly the TAP driver). The +# system "awk" is bad on some platforms. +# Always define AMTAR for backward compatibility. Yes, it's still used +# in the wild :-( We should find a proper way to deprecate it ... +AMTAR='$${TAR-tar}' + + +# We'll loop over all known methods to create a tar archive until one works. +_am_tools='gnutar pax cpio none' + +am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -' + + + + + + +# POSIX will say in a future version that running "rm -f" with no argument +# is OK; and we want to be able to make that assumption in our Makefile +# recipes. So use an aggressive probe to check that the usage we want is +# actually supported "in the wild" to an acceptable degree. +# See automake bug#10828. +# To make any issue more visible, cause the running configure to be aborted +# by default if the 'rm' program in use doesn't match our expectations; the +# user can still override this though. +if rm -f && rm -fr && rm -rf; then : OK; else + cat >&2 <<'END' +Oops! + +Your 'rm' program seems unable to run without file operands specified +on the command line, even when the '-f' option is present. This is contrary +to the behaviour of most rm programs out there, and not conforming with +the upcoming POSIX standard: + +Please tell bug-automake@gnu.org about your system, including the value +of your $PATH and any error possibly output before this message. This +can help us improve future automake versions. + +END + if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then + echo 'Configuration will proceed anyway, since you have set the' >&2 + echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2 + echo >&2 + else + cat >&2 <<'END' +Aborting the configuration process, to ensure you take notice of the issue. + +You can download and install GNU coreutils to get an 'rm' implementation +that behaves properly: . + +If you want to complete the configuration process using your problematic +'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM +to "yes", and re-run configure. + +END + as_fn_error $? "Your 'rm' program is bad, sorry." "$LINENO" 5 + fi +fi + + +# We don't want touse the cflags from the environment since we need control +# of this when we're building the libs. +CFLAGS="" + + + + + +# Checks for programs. + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_CC+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "no acceptable C compiler found in \$PATH +See \`config.log' for more details" "$LINENO" 5; } + +# Provide some information about the compiler. +$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +for ac_option in --version -v -V -qversion; do + { { ac_try="$ac_compiler $ac_option >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_compiler $ac_option >&5") 2>conftest.err + ac_status=$? + if test -s conftest.err; then + sed '10a\ +... rest of stderr output deleted ... + 10q' conftest.err >conftest.er1 + cat conftest.er1 >&5 + fi + rm -f conftest.er1 conftest.err + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } +done + +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +if { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then + ac_no_link=no + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { { ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; then : + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi +if test -z "$ac_file"; then : + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error 77 "C compiler cannot create executables +See \`config.log' for more details" "$LINENO" 5; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details" "$LINENO" 5; } +fi +rm -f conftest conftest$ac_cv_exeext +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +int +main () +{ +FILE *f = fopen ("conftest.out", "w"); + return ferror (f) || fclose (f) != 0; + + ; + return 0; +} +_ACEOF +ac_clean_files="$ac_clean_files conftest.out" +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +if test "$cross_compiling" != yes; then + { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + if { ac_try='./conftest$ac_cv_exeext' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? "cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details" "$LINENO" 5; } + fi + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out +ac_clean_files=$ac_clean_files_save + +else + rm -f -r a.out a.exe b.out conftest.$ac_ext conftest.o conftest.obj conftest.dSYM + ac_no_link=yes + # Setting cross_compile will disable run tests; it will + # also disable AC_CHECK_FILE but that's generally + # correct if we can't link. + cross_compiling=yes + EXEEXT= + # Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +if test "$cross_compiling" != yes; then + { { ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; } + if { ac_try='./conftest$ac_cv_exeext' + { { case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" +$as_echo "$ac_try_echo"; } >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +as_fn_error $? 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" >&6; } +if ${ac_cv_prog_cc_c89+:} false; then : + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include +#include +struct stat; +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + if ac_fn_c_try_compile "$LINENO"; then : + ac_cv_prog_cc_c89=$ac_arg +fi +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac +if test "x$ac_cv_prog_cc_c89" != xno; then : + +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5 +$as_echo_n "checking whether $CC understands -c and -o together... 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For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CC_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + case " $depcc " in #( + *\ -arch\ *\ -arch\ *) am__universal=true ;; + esac + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CC_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CC_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } +CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then + am__fastdepCC_TRUE= + am__fastdepCC_FALSE='#' +else + am__fastdepCC_TRUE='#' + am__fastdepCC_FALSE= +fi + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}as", so it can be a program name with args. +set dummy ${ac_tool_prefix}as; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... 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" >&6; } +if ${ac_cv_prog_ac_ct_AS+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AS"; then + ac_cv_prog_ac_ct_AS="$ac_ct_AS" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_AS="as" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AS=$ac_cv_prog_ac_ct_AS +if test -n "$ac_ct_AS"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AS" >&5 +$as_echo "$ac_ct_AS" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AS" = x; then + AS="as" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AS=$ac_ct_AS + fi +else + AS="$ac_cv_prog_AS" +fi + +# By default we simply use the C compiler to build assembly code. + +test "${CCAS+set}" = set || CCAS=$CC +test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS + + + +depcc="$CCAS" am_compiler_list= + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 +$as_echo_n "checking dependency style of $depcc... " >&6; } +if ${am_cv_CCAS_dependencies_compiler_type+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then + # We make a subdir and do the tests there. Otherwise we can end up + # making bogus files that we don't know about and never remove. For + # instance it was reported that on HP-UX the gcc test will end up + # making a dummy file named 'D' -- because '-MD' means "put the output + # in D". + rm -rf conftest.dir + mkdir conftest.dir + # Copy depcomp to subdir because otherwise we won't find it if we're + # using a relative directory. + cp "$am_depcomp" conftest.dir + cd conftest.dir + # We will build objects and dependencies in a subdirectory because + # it helps to detect inapplicable dependency modes. For instance + # both Tru64's cc and ICC support -MD to output dependencies as a + # side effect of compilation, but ICC will put the dependencies in + # the current directory while Tru64 will put them in the object + # directory. + mkdir sub + + am_cv_CCAS_dependencies_compiler_type=none + if test "$am_compiler_list" = ""; then + am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` + fi + am__universal=false + + + for depmode in $am_compiler_list; do + # Setup a source with many dependencies, because some compilers + # like to wrap large dependency lists on column 80 (with \), and + # we should not choose a depcomp mode which is confused by this. + # + # We need to recreate these files for each test, as the compiler may + # overwrite some of them when testing with obscure command lines. + # This happens at least with the AIX C compiler. + : > sub/conftest.c + for i in 1 2 3 4 5 6; do + echo '#include "conftst'$i'.h"' >> sub/conftest.c + # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with + # Solaris 10 /bin/sh. + echo '/* dummy */' > sub/conftst$i.h + done + echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf + + # We check with '-c' and '-o' for the sake of the "dashmstdout" + # mode. It turns out that the SunPro C++ compiler does not properly + # handle '-M -o', and we need to detect this. Also, some Intel + # versions had trouble with output in subdirs. + am__obj=sub/conftest.${OBJEXT-o} + am__minus_obj="-o $am__obj" + case $depmode in + gcc) + # This depmode causes a compiler race in universal mode. + test "$am__universal" = false || continue + ;; + nosideeffect) + # After this tag, mechanisms are not by side-effect, so they'll + # only be used when explicitly requested. + if test "x$enable_dependency_tracking" = xyes; then + continue + else + break + fi + ;; + msvc7 | msvc7msys | msvisualcpp | msvcmsys) + # This compiler won't grok '-c -o', but also, the minuso test has + # not run yet. These depmodes are late enough in the game, and + # so weak that their functioning should not be impacted. + am__obj=conftest.${OBJEXT-o} + am__minus_obj= + ;; + none) break ;; + esac + if depmode=$depmode \ + source=sub/conftest.c object=$am__obj \ + depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ + $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ + >/dev/null 2>conftest.err && + grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && + grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && + grep $am__obj sub/conftest.Po > /dev/null 2>&1 && + ${MAKE-make} -s -f confmf > /dev/null 2>&1; then + # icc doesn't choke on unknown options, it will just issue warnings + # or remarks (even with -Werror). So we grep stderr for any message + # that says an option was ignored or not supported. + # When given -MP, icc 7.0 and 7.1 complain thusly: + # icc: Command line warning: ignoring option '-M'; no argument required + # The diagnosis changed in icc 8.0: + # icc: Command line remark: option '-MP' not supported + if (grep 'ignoring option' conftest.err || + grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else + am_cv_CCAS_dependencies_compiler_type=$depmode + break + fi + fi + done + + cd .. + rm -rf conftest.dir +else + am_cv_CCAS_dependencies_compiler_type=none +fi + +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CCAS_dependencies_compiler_type" >&5 +$as_echo "$am_cv_CCAS_dependencies_compiler_type" >&6; } +CCASDEPMODE=depmode=$am_cv_CCAS_dependencies_compiler_type + + if + test "x$enable_dependency_tracking" != xno \ + && test "$am_cv_CCAS_dependencies_compiler_type" = gcc3; then + am__fastdepCCAS_TRUE= + am__fastdepCCAS_FALSE='#' +else + am__fastdepCCAS_TRUE='#' + am__fastdepCCAS_FALSE= +fi + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. +set dummy ${ac_tool_prefix}ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$AR"; then + ac_cv_prog_AR="$AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_AR="${ac_tool_prefix}ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +AR=$ac_cv_prog_AR +if test -n "$AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_AR"; then + ac_ct_AR=$AR + # Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_prog_ac_ct_AR+:} false; then : + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_AR"; then + ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_prog_ac_ct_AR="ar" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + +fi +fi +ac_ct_AR=$ac_cv_prog_ac_ct_AR +if test -n "$ac_ct_AR"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 +$as_echo "$ac_ct_AR" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_AR" = x; then + AR="ar" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + AR=$ac_ct_AR + fi +else + AR="$ac_cv_prog_AR" +fi + + +# Make sure that we found the right avr cross-compiler. + +case "${CC}" in + *gcc*) + case "X`${CC} -dumpmachine`X" in + XavrX) ;; + *) as_fn_error $? "Wrong C compiler found; check the PATH!" "$LINENO" 5 ;; + esac + ;; + *) as_fn_error $? "Wrong C compiler found; check the PATH!" "$LINENO" 5 ;; +esac +case "${AS}" in + *avr*as*) ;; + *) as_fn_error $? "Wrong assembler found; check the PATH!" "$LINENO" 5 ;; +esac +case "${AR}" in + *avr*ar*) ;; + *) as_fn_error $? "Wrong archiver found; check the PATH!" "$LINENO" 5 ;; +esac +case "${RANLIB}" in + *avr*ranlib*) ;; + *) as_fn_error $? "Wrong ranlib found; check the PATH!" "$LINENO" 5 ;; +esac + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5 +$as_echo_n "checking whether ln -s works... " >&6; } +LN_S=$as_ln_s +if test "$LN_S" = "ln -s"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5 +$as_echo "no, using $LN_S" >&6; } +fi + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 +$as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; } +set x ${MAKE-make} +ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` +if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then : + $as_echo_n "(cached) " >&6 +else + cat >conftest.make <<\_ACEOF +SHELL = /bin/sh +all: + @echo '@@@%%%=$(MAKE)=@@@%%%' +_ACEOF +# GNU make sometimes prints "make[1]: Entering ...", which would confuse us. +case `${MAKE-make} -f conftest.make 2>/dev/null` in + *@@@%%%=?*=@@@%%%*) + eval ac_cv_prog_make_${ac_make}_set=yes;; + *) + eval ac_cv_prog_make_${ac_make}_set=no;; +esac +rm -f conftest.make +fi +if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + SET_MAKE= +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + SET_MAKE="MAKE=${MAKE-make}" +fi + + +GCC_VER=`${CC} -dumpversion` +as_arg_v1=${GCC_VER} +as_arg_v2="5.1.0" +awk "$as_awk_strverscmp" v1="$as_arg_v1" v2="$as_arg_v2" /dev/null +case $? in #( + 1) : + DEV_LIB="no" ;; #( + 0) : + DEV_LIB="yes" ;; #( + 2) : + DEV_LIB="yes" ;; #( + *) : + ;; +esac + if test "x${GCC_VER}" = "x5.1.0"; then + HAS_GCC_5_1_TRUE= + HAS_GCC_5_1_FALSE='#' +else + HAS_GCC_5_1_TRUE='#' + HAS_GCC_5_1_FALSE= +fi + + +# Check whether --enable-device-lib was given. +if test "${enable_device_lib+set}" = set; then : + enableval=$enable_device_lib; enable_device_lib=true +else + case "${DEV_LIB}" in + yes) enable_device_lib=true + { $as_echo "$as_me:${as_lineno-$LINENO}: Enabled device library" >&5 +$as_echo "$as_me: Enabled device library" >&6;} ;; + *) ;; + esac +fi + + + if test x$enable_device_lib = xtrue; then + HAS_DEV_LIB_TRUE= + HAS_DEV_LIB_FALSE='#' +else + HAS_DEV_LIB_TRUE='#' + HAS_DEV_LIB_FALSE= +fi + + + + +# Check whether --enable-doc was given. +if test "${enable_doc+set}" = set; then : + enableval=$enable_doc; case "${enableval}" in + yes) enable_doc=yes ;; + no) enable_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for global doc option" "$LINENO" 5 ;; + esac +else + enable_doc=no +fi +# Check whether --enable-html-doc was given. +if test "${enable_html_doc+set}" = set; then : + enableval=$enable_html_doc; case "${enableval}" in + yes) html_doc=yes ;; + no) html_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for html-doc option" "$LINENO" 5 ;; + esac +else + html_doc=yes +fi + +# Check whether --enable-xml-doc was given. +if test "${enable_xml_doc+set}" = set; then : + enableval=$enable_xml_doc; case "${enableval}" in + yes) xml_doc=yes ;; + no) xml_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for xml-doc option" "$LINENO" 5 ;; + esac +else + xml_doc=yes +fi + +# Check whether --enable-pdf-doc was given. +if test "${enable_pdf_doc+set}" = set; then : + enableval=$enable_pdf_doc; case "${enableval}" in + yes) pdf_doc=yes ;; + no) pdf_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for pdf-doc option" "$LINENO" 5 ;; + esac +else + pdf_doc=yes +fi + +# Check whether --enable-man-doc was given. +if test "${enable_man_doc+set}" = set; then : + enableval=$enable_man_doc; case "${enableval}" in + yes) man_doc=yes ;; + no) man_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for man-doc option" "$LINENO" 5 ;; + esac +else + man_doc=yes +fi + +# Check whether --enable-versioned-doc was given. +if test "${enable_versioned_doc+set}" = set; then : + enableval=$enable_versioned_doc; case "${enableval}" in + yes) versioned_doc=yes ;; + no) versioned_doc=no ;; + *) as_fn_error $? "bad value ${enableval} for versioned-doc option" "$LINENO" 5 ;; + esac +else + versioned_doc=yes +fi + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for doxygen" >&5 +$as_echo_n "checking for doxygen... " >&6; } +dox_ver=`doxygen --version 2>/dev/null` +if test "x$dox_ver" = "x"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +else + # FIXME: should also check for dox_ver >= 1.4.1 + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + if test "$pdf_doc" = "yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling PDF docs" >&5 +$as_echo "$as_me: Enabling PDF docs" >&6;} + TARGET_DOX_PDF=dox-pdf + INSTALL_DOX_PDF=install-dox-pdf + fi + if test "$html_doc" = "yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling HTML docs" >&5 +$as_echo "$as_me: Enabling HTML docs" >&6;} + TARGET_DOX_HTML=dox-html + INSTALL_DOX_HTML=install-dox-html + fi + if test "$xml_doc" = "yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling XML docs" >&5 +$as_echo "$as_me: Enabling XML docs" >&6;} + TARGET_DOX_XML=dox-xml + INSTALL_DOX_XML=install-dox-xml + fi + if test "$man_doc" = "yes"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: Enabling man pages" >&5 +$as_echo "$as_me: Enabling man pages" >&6;} + TARGET_DOX_HTML=dox-html + INSTALL_DOX_MAN=install-dox-man + fi +fi + + + + + + + + + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for pngtopnm" >&5 +$as_echo_n "checking for pngtopnm... " >&6; } +has_pngtopnm=`pngtopnm --version 2>&1 | grep -c -i Version` +if test "$has_pngtopnm" = "1"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + PNGTOPNM="pngtopnm" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + PNGTOPNM="cat" +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for pnmtopng" >&5 +$as_echo_n "checking for pnmtopng... " >&6; } +has_pnmtopng=`pnmtopng --version 2>&1 | grep -c -i Version` +if test "$has_pnmtopng" = "1"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 +$as_echo "yes" >&6; } + PNMTOPNG="pnmtopng" +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } + PNMTOPNG="cat" + PNGTOPNM="cat" +fi + + + + +if test "$versioned_doc" = "yes"; then + DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc-$(VERSION)' + AVR_LIBC_USER_MANUAL="avr-libc-user-manual-${VERSION}" +else + DOC_INST_DIR='${DESTDIR}${datadir}/doc/avr-libc' + AVR_LIBC_USER_MANUAL="avr-libc-user-manual" +fi + +if test "$enable_doc" = "yes"; then + DOCSDIR='api' +else + DOCSDIR='' +fi + + + + + +# Check whether --enable-debug-info was given. +if test "${enable_debug_info+set}" = set; then : + enableval=$enable_debug_info; case "${enableval}" in + yes|dwarf2|dwarf-2) debuginfo=dwarf2 ;; + no) debuginfo="" ;; + stabs) debuginfo=stabs ;; + dwarf4|dwarf-4) debuginfo=dwarf4 ;; + dwarf) debuginfo=dwarf ;; + *) as_fn_error $? "bad value ${enableval} for --enable-debug-info option; should be either stabs, dwarf-2, or dwarf-4" "$LINENO" 5 ;; + esac +else + debuginfo="" +fi + + +case "$debuginfo" in +"") CDEBUG=""; ASDEBUG="" ;; +stabs) CDEBUG="-gstabs"; ASDEBUG="-Wa,-gstabs" ;; +dwarf2) CDEBUG="-gdwarf-2"; ASDEBUG="-Wa,-gdwarf-2" ;; +dwarf4) CDEBUG="-gdwarf-4"; ASDEBUG="-Wa,-gdwarf-2" ;; +dwarf) CDEBUG="-gdwarf"; ASDEBUG="-Wa,-gdwarf-2" ;; +esac + + + + +FNO_JUMP_TABLES="" + + +HAS_DELAY_CYCLES=0 + + + + + + + + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mno-tablejump" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -mno-tablejump" >&5 +$as_echo_n "checking whether ${CC} supports -mno-tablejump... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_mno_tablejump=yes +else + has_mno_tablejump=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_mno_tablejump" = "xyes" + then + FNO_JUMP_TABLES="-mno-tablejump" + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_mno_tablejump" >&5 +$as_echo "$has_mno_tablejump" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-fno-jump-tables" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports -fno-jump-tables" >&5 +$as_echo_n "checking whether ${CC} supports -fno-jump-tables... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_fno_jump_tables=yes +else + has_fno_jump_tables=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_fno_jump_tables" = "xyes" + then + FNO_JUMP_TABLES="-fno-jump-tables" + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_fno_jump_tables" >&5 +$as_echo "$has_fno_jump_tables" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${CC} supports __builtin_avr_delay_cycles" >&5 +$as_echo_n "checking whether ${CC} supports __builtin_avr_delay_cycles... " >&6; } + echo "extern void __builtin_avr_delay_cycles(unsigned long);\ + int main(void) { __builtin_avr_delay_cycles(42); return 0; }" |\ + ${CC} -S -xc -o - - |\ + grep __builtin_avr_delay_cycles >/dev/null + if test "$?" != "0" + then + HAS_DELAY_CYCLES=1 + has_delay_cycles="yes" + else + has_delay_cycles="no" + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_delay_cycles" >&5 +$as_echo "$has_delay_cycles" >&6; } + CC=${old_CC} + + + + + + +# avr1 + if true; then + HAS_avr1_TRUE= + HAS_avr1_FALSE='#' +else + HAS_avr1_TRUE='#' + HAS_avr1_FALSE= +fi + + if true; then + HAS_at90s1200_TRUE= + HAS_at90s1200_FALSE='#' +else + HAS_at90s1200_TRUE='#' + HAS_at90s1200_FALSE= +fi + + if true; then + HAS_attiny11_TRUE= + HAS_attiny11_FALSE='#' +else + HAS_attiny11_TRUE='#' + HAS_attiny11_FALSE= +fi + + if true; then + HAS_attiny12_TRUE= + HAS_attiny12_FALSE='#' +else + HAS_attiny12_TRUE='#' + HAS_attiny12_FALSE= +fi + + if true; then + HAS_attiny15_TRUE= + HAS_attiny15_FALSE='#' +else + HAS_attiny15_TRUE='#' + HAS_attiny15_FALSE= +fi + + if true; then + HAS_attiny28_TRUE= + HAS_attiny28_FALSE='#' +else + HAS_attiny28_TRUE='#' + HAS_attiny28_FALSE= +fi + + + +# avr2 + if true; then + HAS_avr2_TRUE= + HAS_avr2_FALSE='#' +else + HAS_avr2_TRUE='#' + HAS_avr2_FALSE= +fi + + if true; then + HAS_at90s2313_TRUE= + HAS_at90s2313_FALSE='#' +else + HAS_at90s2313_TRUE='#' + HAS_at90s2313_FALSE= +fi + + if true; then + HAS_at90s2323_TRUE= + HAS_at90s2323_FALSE='#' +else + HAS_at90s2323_TRUE='#' + HAS_at90s2323_FALSE= +fi + + if true; then + HAS_at90s2333_TRUE= + HAS_at90s2333_FALSE='#' +else + HAS_at90s2333_TRUE='#' + HAS_at90s2333_FALSE= +fi + + if true; then + HAS_at90s2343_TRUE= + HAS_at90s2343_FALSE='#' +else + HAS_at90s2343_TRUE='#' + HAS_at90s2343_FALSE= +fi + + if true; then + HAS_at90s4414_TRUE= + HAS_at90s4414_FALSE='#' +else + HAS_at90s4414_TRUE='#' + HAS_at90s4414_FALSE= +fi + + if true; then + HAS_at90s4433_TRUE= + HAS_at90s4433_FALSE='#' +else + HAS_at90s4433_TRUE='#' + HAS_at90s4433_FALSE= +fi + + if true; then + HAS_at90s4434_TRUE= + HAS_at90s4434_FALSE='#' +else + HAS_at90s4434_TRUE='#' + HAS_at90s4434_FALSE= +fi + + if true; then + HAS_at90s8515_TRUE= + HAS_at90s8515_FALSE='#' +else + HAS_at90s8515_TRUE='#' + HAS_at90s8515_FALSE= +fi + + if true; then + HAS_at90c8534_TRUE= + HAS_at90c8534_FALSE='#' +else + HAS_at90c8534_TRUE='#' + HAS_at90c8534_FALSE= +fi + + if true; then + HAS_at90s8535_TRUE= + HAS_at90s8535_FALSE='#' +else + HAS_at90s8535_TRUE='#' + HAS_at90s8535_FALSE= +fi + + if true; then + HAS_attiny22_TRUE= + HAS_attiny22_FALSE='#' +else + HAS_attiny22_TRUE='#' + HAS_attiny22_FALSE= +fi + + if true; then + HAS_attiny26_TRUE= + HAS_attiny26_FALSE='#' +else + HAS_attiny26_TRUE='#' + HAS_attiny26_FALSE= +fi + + + +#avr25 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avr25" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr25" >&5 +$as_echo_n "checking if ${CC} has support for avr25... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avr25=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avr25" = "xyes"; then + HAS_avr25_TRUE= + HAS_avr25_FALSE='#' +else + HAS_avr25_TRUE='#' + HAS_avr25_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5272" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5272" >&5 +$as_echo_n "checking if ${CC} has support for ata5272... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5272=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5272" = "xyes"; then + HAS_ata5272_TRUE= + HAS_ata5272_FALSE='#' +else + HAS_ata5272_TRUE='#' + HAS_ata5272_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6616c" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6616c" >&5 +$as_echo_n "checking if ${CC} has support for ata6616c... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6616c=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6616c" = "xyes"; then + HAS_ata6616c_TRUE= + HAS_ata6616c_FALSE='#' +else + HAS_ata6616c_TRUE='#' + HAS_ata6616c_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny13" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13" >&5 +$as_echo_n "checking if ${CC} has support for attiny13... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny13=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny13" = "xyes"; then + HAS_attiny13_TRUE= + HAS_attiny13_FALSE='#' +else + HAS_attiny13_TRUE='#' + HAS_attiny13_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny13a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny13a" >&5 +$as_echo_n "checking if ${CC} has support for attiny13a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny13a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny13a" = "xyes"; then + HAS_attiny13a_TRUE= + HAS_attiny13a_FALSE='#' +else + HAS_attiny13a_TRUE='#' + HAS_attiny13a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny2313" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313" >&5 +$as_echo_n "checking if ${CC} has support for attiny2313... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny2313=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny2313" = "xyes"; then + HAS_attiny2313_TRUE= + HAS_attiny2313_FALSE='#' +else + HAS_attiny2313_TRUE='#' + HAS_attiny2313_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny2313a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny2313a" >&5 +$as_echo_n "checking if ${CC} has support for attiny2313a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny2313a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny2313a" = "xyes"; then + HAS_attiny2313a_TRUE= + HAS_attiny2313a_FALSE='#' +else + HAS_attiny2313a_TRUE='#' + HAS_attiny2313a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny24" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24" >&5 +$as_echo_n "checking if ${CC} has support for attiny24... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny24=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny24" = "xyes"; then + HAS_attiny24_TRUE= + HAS_attiny24_FALSE='#' +else + HAS_attiny24_TRUE='#' + HAS_attiny24_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny24a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny24a" >&5 +$as_echo_n "checking if ${CC} has support for attiny24a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny24a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny24a" = "xyes"; then + HAS_attiny24a_TRUE= + HAS_attiny24a_FALSE='#' +else + HAS_attiny24a_TRUE='#' + HAS_attiny24a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny25" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny25" >&5 +$as_echo_n "checking if ${CC} has support for attiny25... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny25=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny25" = "xyes"; then + HAS_attiny25_TRUE= + HAS_attiny25_FALSE='#' +else + HAS_attiny25_TRUE='#' + HAS_attiny25_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny261" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261" >&5 +$as_echo_n "checking if ${CC} has support for attiny261... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny261=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny261" = "xyes"; then + HAS_attiny261_TRUE= + HAS_attiny261_FALSE='#' +else + HAS_attiny261_TRUE='#' + HAS_attiny261_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny261a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny261a" >&5 +$as_echo_n "checking if ${CC} has support for attiny261a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny261a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny261a" = "xyes"; then + HAS_attiny261a_TRUE= + HAS_attiny261a_FALSE='#' +else + HAS_attiny261a_TRUE='#' + HAS_attiny261a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny43u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny43u" >&5 +$as_echo_n "checking if ${CC} has support for attiny43u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny43u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny43u" = "xyes"; then + HAS_attiny43u_TRUE= + HAS_attiny43u_FALSE='#' +else + HAS_attiny43u_TRUE='#' + HAS_attiny43u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny4313" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4313" >&5 +$as_echo_n "checking if ${CC} has support for attiny4313... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny4313=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny4313" = "xyes"; then + HAS_attiny4313_TRUE= + HAS_attiny4313_FALSE='#' +else + HAS_attiny4313_TRUE='#' + HAS_attiny4313_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny44" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44" >&5 +$as_echo_n "checking if ${CC} has support for attiny44... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny44=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny44" = "xyes"; then + HAS_attiny44_TRUE= + HAS_attiny44_FALSE='#' +else + HAS_attiny44_TRUE='#' + HAS_attiny44_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny441" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny441" >&5 +$as_echo_n "checking if ${CC} has support for attiny441... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny441=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny441" = "xyes"; then + HAS_attiny441_TRUE= + HAS_attiny441_FALSE='#' +else + HAS_attiny441_TRUE='#' + HAS_attiny441_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny44a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny44a" >&5 +$as_echo_n "checking if ${CC} has support for attiny44a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny44a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny44a" = "xyes"; then + HAS_attiny44a_TRUE= + HAS_attiny44a_FALSE='#' +else + HAS_attiny44a_TRUE='#' + HAS_attiny44a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny45" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny45" >&5 +$as_echo_n "checking if ${CC} has support for attiny45... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny45=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny45" = "xyes"; then + HAS_attiny45_TRUE= + HAS_attiny45_FALSE='#' +else + HAS_attiny45_TRUE='#' + HAS_attiny45_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny461" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461" >&5 +$as_echo_n "checking if ${CC} has support for attiny461... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny461=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny461" = "xyes"; then + HAS_attiny461_TRUE= + HAS_attiny461_FALSE='#' +else + HAS_attiny461_TRUE='#' + HAS_attiny461_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny461a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny461a" >&5 +$as_echo_n "checking if ${CC} has support for attiny461a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny461a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny461a" = "xyes"; then + HAS_attiny461a_TRUE= + HAS_attiny461a_FALSE='#' +else + HAS_attiny461a_TRUE='#' + HAS_attiny461a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny48" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny48" >&5 +$as_echo_n "checking if ${CC} has support for attiny48... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny48=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny48" = "xyes"; then + HAS_attiny48_TRUE= + HAS_attiny48_FALSE='#' +else + HAS_attiny48_TRUE='#' + HAS_attiny48_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny828" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny828" >&5 +$as_echo_n "checking if ${CC} has support for attiny828... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny828=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny828" = "xyes"; then + HAS_attiny828_TRUE= + HAS_attiny828_FALSE='#' +else + HAS_attiny828_TRUE='#' + HAS_attiny828_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny84" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84" >&5 +$as_echo_n "checking if ${CC} has support for attiny84... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny84=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny84" = "xyes"; then + HAS_attiny84_TRUE= + HAS_attiny84_FALSE='#' +else + HAS_attiny84_TRUE='#' + HAS_attiny84_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny841" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny841" >&5 +$as_echo_n "checking if ${CC} has support for attiny841... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny841=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny841" = "xyes"; then + HAS_attiny841_TRUE= + HAS_attiny841_FALSE='#' +else + HAS_attiny841_TRUE='#' + HAS_attiny841_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny84a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny84a" >&5 +$as_echo_n "checking if ${CC} has support for attiny84a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny84a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny84a" = "xyes"; then + HAS_attiny84a_TRUE= + HAS_attiny84a_FALSE='#' +else + HAS_attiny84a_TRUE='#' + HAS_attiny84a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny85" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny85" >&5 +$as_echo_n "checking if ${CC} has support for attiny85... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny85=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny85" = "xyes"; then + HAS_attiny85_TRUE= + HAS_attiny85_FALSE='#' +else + HAS_attiny85_TRUE='#' + HAS_attiny85_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny861" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861" >&5 +$as_echo_n "checking if ${CC} has support for attiny861... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny861=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny861" = "xyes"; then + HAS_attiny861_TRUE= + HAS_attiny861_FALSE='#' +else + HAS_attiny861_TRUE='#' + HAS_attiny861_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny861a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny861a" >&5 +$as_echo_n "checking if ${CC} has support for attiny861a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny861a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny861a" = "xyes"; then + HAS_attiny861a_TRUE= + HAS_attiny861a_FALSE='#' +else + HAS_attiny861a_TRUE='#' + HAS_attiny861a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny87" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny87" >&5 +$as_echo_n "checking if ${CC} has support for attiny87... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny87=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny87" = "xyes"; then + HAS_attiny87_TRUE= + HAS_attiny87_FALSE='#' +else + HAS_attiny87_TRUE='#' + HAS_attiny87_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny88" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny88" >&5 +$as_echo_n "checking if ${CC} has support for attiny88... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny88=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny88" = "xyes"; then + HAS_attiny88_TRUE= + HAS_attiny88_FALSE='#' +else + HAS_attiny88_TRUE='#' + HAS_attiny88_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at86rf401" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at86rf401" >&5 +$as_echo_n "checking if ${CC} has support for at86rf401... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at86rf401=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at86rf401" = "xyes"; then + HAS_at86rf401_TRUE= + HAS_at86rf401_FALSE='#' +else + HAS_at86rf401_TRUE='#' + HAS_at86rf401_FALSE= +fi + + + +# avr3 + if true; then + HAS_avr3_TRUE= + HAS_avr3_FALSE='#' +else + HAS_avr3_TRUE='#' + HAS_avr3_FALSE= +fi + + if true; then + HAS_at43usb320_TRUE= + HAS_at43usb320_FALSE='#' +else + HAS_at43usb320_TRUE='#' + HAS_at43usb320_FALSE= +fi + + if true; then + HAS_at43usb355_TRUE= + HAS_at43usb355_FALSE='#' +else + HAS_at43usb355_TRUE='#' + HAS_at43usb355_FALSE= +fi + + if true; then + HAS_at76c711_TRUE= + HAS_at76c711_FALSE='#' +else + HAS_at76c711_TRUE='#' + HAS_at76c711_FALSE= +fi + + +#avr31 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avr31" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr31" >&5 +$as_echo_n "checking if ${CC} has support for avr31... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avr31=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avr31" = "xyes"; then + HAS_avr31_TRUE= + HAS_avr31_FALSE='#' +else + HAS_avr31_TRUE='#' + HAS_avr31_FALSE= +fi + + + if true; then + HAS_atmega103_TRUE= + HAS_atmega103_FALSE='#' +else + HAS_atmega103_TRUE='#' + HAS_atmega103_FALSE= +fi + + + +#avr35 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avr35" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr35" >&5 +$as_echo_n "checking if ${CC} has support for avr35... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avr35=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avr35" = "xyes"; then + HAS_avr35_TRUE= + HAS_avr35_FALSE='#' +else + HAS_avr35_TRUE='#' + HAS_avr35_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb82" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb82" >&5 +$as_echo_n "checking if ${CC} has support for at90usb82... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb82=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb82" = "xyes"; then + HAS_at90usb82_TRUE= + HAS_at90usb82_FALSE='#' +else + HAS_at90usb82_TRUE='#' + HAS_at90usb82_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb162" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb162" >&5 +$as_echo_n "checking if ${CC} has support for at90usb162... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb162=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb162" = "xyes"; then + HAS_at90usb162_TRUE= + HAS_at90usb162_FALSE='#' +else + HAS_at90usb162_TRUE='#' + HAS_at90usb162_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5505" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5505" >&5 +$as_echo_n "checking if ${CC} has support for ata5505... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5505=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5505" = "xyes"; then + HAS_ata5505_TRUE= + HAS_ata5505_FALSE='#' +else + HAS_ata5505_TRUE='#' + HAS_ata5505_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6617c" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6617c" >&5 +$as_echo_n "checking if ${CC} has support for ata6617c... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6617c=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6617c" = "xyes"; then + HAS_ata6617c_TRUE= + HAS_ata6617c_FALSE='#' +else + HAS_ata6617c_TRUE='#' + HAS_ata6617c_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata664251" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata664251" >&5 +$as_echo_n "checking if ${CC} has support for ata664251... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata664251=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata664251" = "xyes"; then + HAS_ata664251_TRUE= + HAS_ata664251_FALSE='#' +else + HAS_ata664251_TRUE='#' + HAS_ata664251_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega8u2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8u2" >&5 +$as_echo_n "checking if ${CC} has support for atmega8u2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega8u2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega8u2" = "xyes"; then + HAS_atmega8u2_TRUE= + HAS_atmega8u2_FALSE='#' +else + HAS_atmega8u2_TRUE='#' + HAS_atmega8u2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16u2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u2" >&5 +$as_echo_n "checking if ${CC} has support for atmega16u2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16u2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16u2" = "xyes"; then + HAS_atmega16u2_TRUE= + HAS_atmega16u2_FALSE='#' +else + HAS_atmega16u2_TRUE='#' + HAS_atmega16u2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32u2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u2" >&5 +$as_echo_n "checking if ${CC} has support for atmega32u2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32u2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32u2" = "xyes"; then + HAS_atmega32u2_TRUE= + HAS_atmega32u2_FALSE='#' +else + HAS_atmega32u2_TRUE='#' + HAS_atmega32u2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny167" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny167" >&5 +$as_echo_n "checking if ${CC} has support for attiny167... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny167=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny167" = "xyes"; then + HAS_attiny167_TRUE= + HAS_attiny167_FALSE='#' +else + HAS_attiny167_TRUE='#' + HAS_attiny167_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny1634" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny1634" >&5 +$as_echo_n "checking if ${CC} has support for attiny1634... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny1634=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny1634" = "xyes"; then + HAS_attiny1634_TRUE= + HAS_attiny1634_FALSE='#' +else + HAS_attiny1634_TRUE='#' + HAS_attiny1634_FALSE= +fi + + + +# avr4 + if true; then + HAS_avr4_TRUE= + HAS_avr4_FALSE='#' +else + HAS_avr4_TRUE='#' + HAS_avr4_FALSE= +fi + + if true; then + HAS_atmega8_TRUE= + HAS_atmega8_FALSE='#' +else + HAS_atmega8_TRUE='#' + HAS_atmega8_FALSE= +fi + + if true; then + HAS_atmega8515_TRUE= + HAS_atmega8515_FALSE='#' +else + HAS_atmega8515_TRUE='#' + HAS_atmega8515_FALSE= +fi + + if true; then + HAS_atmega8535_TRUE= + HAS_atmega8535_FALSE='#' +else + HAS_atmega8535_TRUE='#' + HAS_atmega8535_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6285" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6285" >&5 +$as_echo_n "checking if ${CC} has support for ata6285... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6285=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6285" = "xyes"; then + HAS_ata6285_TRUE= + HAS_ata6285_FALSE='#' +else + HAS_ata6285_TRUE='#' + HAS_ata6285_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6286" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6286" >&5 +$as_echo_n "checking if ${CC} has support for ata6286... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6286=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6286" = "xyes"; then + HAS_ata6286_TRUE= + HAS_ata6286_FALSE='#' +else + HAS_ata6286_TRUE='#' + HAS_ata6286_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6289" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6289" >&5 +$as_echo_n "checking if ${CC} has support for ata6289... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6289=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6289" = "xyes"; then + HAS_ata6289_TRUE= + HAS_ata6289_FALSE='#' +else + HAS_ata6289_TRUE='#' + HAS_ata6289_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6612c" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6612c" >&5 +$as_echo_n "checking if ${CC} has support for ata6612c... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6612c=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6612c" = "xyes"; then + HAS_ata6612c_TRUE= + HAS_ata6612c_FALSE='#' +else + HAS_ata6612c_TRUE='#' + HAS_ata6612c_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega8a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8a" >&5 +$as_echo_n "checking if ${CC} has support for atmega8a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega8a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega8a" = "xyes"; then + HAS_atmega8a_TRUE= + HAS_atmega8a_FALSE='#' +else + HAS_atmega8a_TRUE='#' + HAS_atmega8a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega48" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48" >&5 +$as_echo_n "checking if ${CC} has support for atmega48... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega48=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega48" = "xyes"; then + HAS_atmega48_TRUE= + HAS_atmega48_FALSE='#' +else + HAS_atmega48_TRUE='#' + HAS_atmega48_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega48a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48a" >&5 +$as_echo_n "checking if ${CC} has support for atmega48a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega48a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega48a" = "xyes"; then + HAS_atmega48a_TRUE= + HAS_atmega48a_FALSE='#' +else + HAS_atmega48a_TRUE='#' + HAS_atmega48a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega48pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega48pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega48pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega48pa" = "xyes"; then + HAS_atmega48pa_TRUE= + HAS_atmega48pa_FALSE='#' +else + HAS_atmega48pa_TRUE='#' + HAS_atmega48pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega48pb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48pb" >&5 +$as_echo_n "checking if ${CC} has support for atmega48pb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega48pb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega48pb" = "xyes"; then + HAS_atmega48pb_TRUE= + HAS_atmega48pb_FALSE='#' +else + HAS_atmega48pb_TRUE='#' + HAS_atmega48pb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega48p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega48p" >&5 +$as_echo_n "checking if ${CC} has support for atmega48p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega48p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega48p" = "xyes"; then + HAS_atmega48p_TRUE= + HAS_atmega48p_FALSE='#' +else + HAS_atmega48p_TRUE='#' + HAS_atmega48p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega88" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88" >&5 +$as_echo_n "checking if ${CC} has support for atmega88... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega88=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega88" = "xyes"; then + HAS_atmega88_TRUE= + HAS_atmega88_FALSE='#' +else + HAS_atmega88_TRUE='#' + HAS_atmega88_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega88a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88a" >&5 +$as_echo_n "checking if ${CC} has support for atmega88a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega88a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega88a" = "xyes"; then + HAS_atmega88a_TRUE= + HAS_atmega88a_FALSE='#' +else + HAS_atmega88a_TRUE='#' + HAS_atmega88a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega88p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88p" >&5 +$as_echo_n "checking if ${CC} has support for atmega88p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega88p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega88p" = "xyes"; then + HAS_atmega88p_TRUE= + HAS_atmega88p_FALSE='#' +else + HAS_atmega88p_TRUE='#' + HAS_atmega88p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega88pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega88pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega88pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega88pa" = "xyes"; then + HAS_atmega88pa_TRUE= + HAS_atmega88pa_FALSE='#' +else + HAS_atmega88pa_TRUE='#' + HAS_atmega88pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega88pb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega88pb" >&5 +$as_echo_n "checking if ${CC} has support for atmega88pb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega88pb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega88pb" = "xyes"; then + HAS_atmega88pb_TRUE= + HAS_atmega88pb_FALSE='#' +else + HAS_atmega88pb_TRUE='#' + HAS_atmega88pb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega8hva" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega8hva" >&5 +$as_echo_n "checking if ${CC} has support for atmega8hva... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega8hva=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega8hva" = "xyes"; then + HAS_atmega8hva_TRUE= + HAS_atmega8hva_FALSE='#' +else + HAS_atmega8hva_TRUE='#' + HAS_atmega8hva_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm1" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm1" = "xyes"; then + HAS_at90pwm1_TRUE= + HAS_at90pwm1_FALSE='#' +else + HAS_at90pwm1_TRUE='#' + HAS_at90pwm1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm2" = "xyes"; then + HAS_at90pwm2_TRUE= + HAS_at90pwm2_FALSE='#' +else + HAS_at90pwm2_TRUE='#' + HAS_at90pwm2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm2b" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm2b" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm2b... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm2b=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm2b" = "xyes"; then + HAS_at90pwm2b_TRUE= + HAS_at90pwm2b_FALSE='#' +else + HAS_at90pwm2b_TRUE='#' + HAS_at90pwm2b_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm3" = "xyes"; then + HAS_at90pwm3_TRUE= + HAS_at90pwm3_FALSE='#' +else + HAS_at90pwm3_TRUE='#' + HAS_at90pwm3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm3b" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm3b" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm3b... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm3b=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm3b" = "xyes"; then + HAS_at90pwm3b_TRUE= + HAS_at90pwm3b_FALSE='#' +else + HAS_at90pwm3b_TRUE='#' + HAS_at90pwm3b_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm81" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm81" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm81... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm81=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm81" = "xyes"; then + HAS_at90pwm81_TRUE= + HAS_at90pwm81_FALSE='#' +else + HAS_at90pwm81_TRUE='#' + HAS_at90pwm81_FALSE= +fi + + + +# avr5 + if true; then + HAS_avr5_TRUE= + HAS_avr5_FALSE='#' +else + HAS_avr5_TRUE='#' + HAS_avr5_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90can32" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can32" >&5 +$as_echo_n "checking if ${CC} has support for at90can32... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90can32=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90can32" = "xyes"; then + HAS_at90can32_TRUE= + HAS_at90can32_FALSE='#' +else + HAS_at90can32_TRUE='#' + HAS_at90can32_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90can64" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can64" >&5 +$as_echo_n "checking if ${CC} has support for at90can64... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90can64=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90can64" = "xyes"; then + HAS_at90can64_TRUE= + HAS_at90can64_FALSE='#' +else + HAS_at90can64_TRUE='#' + HAS_at90can64_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90scr100" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90scr100" >&5 +$as_echo_n "checking if ${CC} has support for at90scr100... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90scr100=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90scr100" = "xyes"; then + HAS_at90scr100_TRUE= + HAS_at90scr100_FALSE='#' +else + HAS_at90scr100_TRUE='#' + HAS_at90scr100_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb646" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb646" >&5 +$as_echo_n "checking if ${CC} has support for at90usb646... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb646=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb646" = "xyes"; then + HAS_at90usb646_TRUE= + HAS_at90usb646_FALSE='#' +else + HAS_at90usb646_TRUE='#' + HAS_at90usb646_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb647" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb647" >&5 +$as_echo_n "checking if ${CC} has support for at90usb647... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb647=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb647" = "xyes"; then + HAS_at90usb647_TRUE= + HAS_at90usb647_FALSE='#' +else + HAS_at90usb647_TRUE='#' + HAS_at90usb647_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm316" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm316" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm316... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm316=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm316" = "xyes"; then + HAS_at90pwm316_TRUE= + HAS_at90pwm316_FALSE='#' +else + HAS_at90pwm316_TRUE='#' + HAS_at90pwm316_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm216" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm216" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm216... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm216=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm216" = "xyes"; then + HAS_at90pwm216_TRUE= + HAS_at90pwm216_FALSE='#' +else + HAS_at90pwm216_TRUE='#' + HAS_at90pwm216_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90pwm161" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90pwm161" >&5 +$as_echo_n "checking if ${CC} has support for at90pwm161... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90pwm161=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90pwm161" = "xyes"; then + HAS_at90pwm161_TRUE= + HAS_at90pwm161_FALSE='#' +else + HAS_at90pwm161_TRUE='#' + HAS_at90pwm161_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at94k" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at94k" >&5 +$as_echo_n "checking if ${CC} has support for at94k... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at94k=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at94k" = "xyes"; then + HAS_at94k_TRUE= + HAS_at94k_FALSE='#' +else + HAS_at94k_TRUE='#' + HAS_at94k_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5702m322" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5702m322" >&5 +$as_echo_n "checking if ${CC} has support for ata5702m322... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5702m322=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5702m322" = "xyes"; then + HAS_ata5702m322_TRUE= + HAS_ata5702m322_FALSE='#' +else + HAS_ata5702m322_TRUE='#' + HAS_ata5702m322_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5782" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5782" >&5 +$as_echo_n "checking if ${CC} has support for ata5782... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5782=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5782" = "xyes"; then + HAS_ata5782_TRUE= + HAS_ata5782_FALSE='#' +else + HAS_ata5782_TRUE='#' + HAS_ata5782_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5790" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5790" >&5 +$as_echo_n "checking if ${CC} has support for ata5790... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5790=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5790" = "xyes"; then + HAS_ata5790_TRUE= + HAS_ata5790_FALSE='#' +else + HAS_ata5790_TRUE='#' + HAS_ata5790_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5790n" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5790n" >&5 +$as_echo_n "checking if ${CC} has support for ata5790n... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5790n=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5790n" = "xyes"; then + HAS_ata5790n_TRUE= + HAS_ata5790n_FALSE='#' +else + HAS_ata5790n_TRUE='#' + HAS_ata5790n_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5791" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5791" >&5 +$as_echo_n "checking if ${CC} has support for ata5791... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5791=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5791" = "xyes"; then + HAS_ata5791_TRUE= + HAS_ata5791_FALSE='#' +else + HAS_ata5791_TRUE='#' + HAS_ata5791_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5795" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5795" >&5 +$as_echo_n "checking if ${CC} has support for ata5795... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5795=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5795" = "xyes"; then + HAS_ata5795_TRUE= + HAS_ata5795_FALSE='#' +else + HAS_ata5795_TRUE='#' + HAS_ata5795_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata5831" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata5831" >&5 +$as_echo_n "checking if ${CC} has support for ata5831... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata5831=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata5831" = "xyes"; then + HAS_ata5831_TRUE= + HAS_ata5831_FALSE='#' +else + HAS_ata5831_TRUE='#' + HAS_ata5831_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6613c" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6613c" >&5 +$as_echo_n "checking if ${CC} has support for ata6613c... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6613c=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6613c" = "xyes"; then + HAS_ata6613c_TRUE= + HAS_ata6613c_FALSE='#' +else + HAS_ata6613c_TRUE='#' + HAS_ata6613c_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata6614q" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata6614q" >&5 +$as_echo_n "checking if ${CC} has support for ata6614q... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata6614q=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata6614q" = "xyes"; then + HAS_ata6614q_TRUE= + HAS_ata6614q_FALSE='#' +else + HAS_ata6614q_TRUE='#' + HAS_ata6614q_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata8210" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata8210" >&5 +$as_echo_n "checking if ${CC} has support for ata8210... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata8210=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata8210" = "xyes"; then + HAS_ata8210_TRUE= + HAS_ata8210_FALSE='#' +else + HAS_ata8210_TRUE='#' + HAS_ata8210_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=ata8510" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for ata8510" >&5 +$as_echo_n "checking if ${CC} has support for ata8510... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_ata8510=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_ata8510" = "xyes"; then + HAS_ata8510_TRUE= + HAS_ata8510_FALSE='#' +else + HAS_ata8510_TRUE='#' + HAS_ata8510_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16" >&5 +$as_echo_n "checking if ${CC} has support for atmega16... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16" = "xyes"; then + HAS_atmega16_TRUE= + HAS_atmega16_FALSE='#' +else + HAS_atmega16_TRUE='#' + HAS_atmega16_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16a" >&5 +$as_echo_n "checking if ${CC} has support for atmega16a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16a" = "xyes"; then + HAS_atmega16a_TRUE= + HAS_atmega16a_FALSE='#' +else + HAS_atmega16a_TRUE='#' + HAS_atmega16a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega161" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega161" >&5 +$as_echo_n "checking if ${CC} has support for atmega161... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega161=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega161" = "xyes"; then + HAS_atmega161_TRUE= + HAS_atmega161_FALSE='#' +else + HAS_atmega161_TRUE='#' + HAS_atmega161_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega162" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega162" >&5 +$as_echo_n "checking if ${CC} has support for atmega162... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega162=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega162" = "xyes"; then + HAS_atmega162_TRUE= + HAS_atmega162_FALSE='#' +else + HAS_atmega162_TRUE='#' + HAS_atmega162_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega163" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega163" >&5 +$as_echo_n "checking if ${CC} has support for atmega163... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega163=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega163" = "xyes"; then + HAS_atmega163_TRUE= + HAS_atmega163_FALSE='#' +else + HAS_atmega163_TRUE='#' + HAS_atmega163_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega164a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164a" >&5 +$as_echo_n "checking if ${CC} has support for atmega164a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega164a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega164a" = "xyes"; then + HAS_atmega164a_TRUE= + HAS_atmega164a_FALSE='#' +else + HAS_atmega164a_TRUE='#' + HAS_atmega164a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega164p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164p" >&5 +$as_echo_n "checking if ${CC} has support for atmega164p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega164p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega164p" = "xyes"; then + HAS_atmega164p_TRUE= + HAS_atmega164p_FALSE='#' +else + HAS_atmega164p_TRUE='#' + HAS_atmega164p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega164pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega164pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega164pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega164pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega164pa" = "xyes"; then + HAS_atmega164pa_TRUE= + HAS_atmega164pa_FALSE='#' +else + HAS_atmega164pa_TRUE='#' + HAS_atmega164pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega165" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165" >&5 +$as_echo_n "checking if ${CC} has support for atmega165... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega165=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega165" = "xyes"; then + HAS_atmega165_TRUE= + HAS_atmega165_FALSE='#' +else + HAS_atmega165_TRUE='#' + HAS_atmega165_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega165a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165a" >&5 +$as_echo_n "checking if ${CC} has support for atmega165a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega165a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega165a" = "xyes"; then + HAS_atmega165a_TRUE= + HAS_atmega165a_FALSE='#' +else + HAS_atmega165a_TRUE='#' + HAS_atmega165a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega165p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165p" >&5 +$as_echo_n "checking if ${CC} has support for atmega165p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega165p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega165p" = "xyes"; then + HAS_atmega165p_TRUE= + HAS_atmega165p_FALSE='#' +else + HAS_atmega165p_TRUE='#' + HAS_atmega165p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega165pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega165pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega165pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega165pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega165pa" = "xyes"; then + HAS_atmega165pa_TRUE= + HAS_atmega165pa_FALSE='#' +else + HAS_atmega165pa_TRUE='#' + HAS_atmega165pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega168" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168" >&5 +$as_echo_n "checking if ${CC} has support for atmega168... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega168=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega168" = "xyes"; then + HAS_atmega168_TRUE= + HAS_atmega168_FALSE='#' +else + HAS_atmega168_TRUE='#' + HAS_atmega168_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega168a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168a" >&5 +$as_echo_n "checking if ${CC} has support for atmega168a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega168a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega168a" = "xyes"; then + HAS_atmega168a_TRUE= + HAS_atmega168a_FALSE='#' +else + HAS_atmega168a_TRUE='#' + HAS_atmega168a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega168p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168p" >&5 +$as_echo_n "checking if ${CC} has support for atmega168p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega168p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega168p" = "xyes"; then + HAS_atmega168p_TRUE= + HAS_atmega168p_FALSE='#' +else + HAS_atmega168p_TRUE='#' + HAS_atmega168p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega168pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega168pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega168pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega168pa" = "xyes"; then + HAS_atmega168pa_TRUE= + HAS_atmega168pa_FALSE='#' +else + HAS_atmega168pa_TRUE='#' + HAS_atmega168pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega168pb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega168pb" >&5 +$as_echo_n "checking if ${CC} has support for atmega168pb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega168pb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega168pb" = "xyes"; then + HAS_atmega168pb_TRUE= + HAS_atmega168pb_FALSE='#' +else + HAS_atmega168pb_TRUE='#' + HAS_atmega168pb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega169" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169" >&5 +$as_echo_n "checking if ${CC} has support for atmega169... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega169=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega169" = "xyes"; then + HAS_atmega169_TRUE= + HAS_atmega169_FALSE='#' +else + HAS_atmega169_TRUE='#' + HAS_atmega169_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega169a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169a" >&5 +$as_echo_n "checking if ${CC} has support for atmega169a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega169a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega169a" = "xyes"; then + HAS_atmega169a_TRUE= + HAS_atmega169a_FALSE='#' +else + HAS_atmega169a_TRUE='#' + HAS_atmega169a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega169p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169p" >&5 +$as_echo_n "checking if ${CC} has support for atmega169p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega169p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega169p" = "xyes"; then + HAS_atmega169p_TRUE= + HAS_atmega169p_FALSE='#' +else + HAS_atmega169p_TRUE='#' + HAS_atmega169p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega169pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega169pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega169pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega169pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega169pa" = "xyes"; then + HAS_atmega169pa_TRUE= + HAS_atmega169pa_FALSE='#' +else + HAS_atmega169pa_TRUE='#' + HAS_atmega169pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16hva" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva" >&5 +$as_echo_n "checking if ${CC} has support for atmega16hva... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16hva=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16hva" = "xyes"; then + HAS_atmega16hva_TRUE= + HAS_atmega16hva_FALSE='#' +else + HAS_atmega16hva_TRUE='#' + HAS_atmega16hva_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16hva2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hva2" >&5 +$as_echo_n "checking if ${CC} has support for atmega16hva2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16hva2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16hva2" = "xyes"; then + HAS_atmega16hva2_TRUE= + HAS_atmega16hva2_FALSE='#' +else + HAS_atmega16hva2_TRUE='#' + HAS_atmega16hva2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16hvb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvb" >&5 +$as_echo_n "checking if ${CC} has support for atmega16hvb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16hvb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16hvb" = "xyes"; then + HAS_atmega16hvb_TRUE= + HAS_atmega16hvb_FALSE='#' +else + HAS_atmega16hvb_TRUE='#' + HAS_atmega16hvb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16hvbrevb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16hvbrevb" >&5 +$as_echo_n "checking if ${CC} has support for atmega16hvbrevb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16hvbrevb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16hvbrevb" = "xyes"; then + HAS_atmega16hvbrevb_TRUE= + HAS_atmega16hvbrevb_FALSE='#' +else + HAS_atmega16hvbrevb_TRUE='#' + HAS_atmega16hvbrevb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16m1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16m1" >&5 +$as_echo_n "checking if ${CC} has support for atmega16m1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16m1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16m1" = "xyes"; then + HAS_atmega16m1_TRUE= + HAS_atmega16m1_FALSE='#' +else + HAS_atmega16m1_TRUE='#' + HAS_atmega16m1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega16u4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega16u4" >&5 +$as_echo_n "checking if ${CC} has support for atmega16u4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega16u4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega16u4" = "xyes"; then + HAS_atmega16u4_TRUE= + HAS_atmega16u4_FALSE='#' +else + HAS_atmega16u4_TRUE='#' + HAS_atmega16u4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32" >&5 +$as_echo_n "checking if ${CC} has support for atmega32... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32" = "xyes"; then + HAS_atmega32_TRUE= + HAS_atmega32_FALSE='#' +else + HAS_atmega32_TRUE='#' + HAS_atmega32_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32a" >&5 +$as_echo_n "checking if ${CC} has support for atmega32a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32a" = "xyes"; then + HAS_atmega32a_TRUE= + HAS_atmega32a_FALSE='#' +else + HAS_atmega32a_TRUE='#' + HAS_atmega32a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega323" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega323" >&5 +$as_echo_n "checking if ${CC} has support for atmega323... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega323=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega323" = "xyes"; then + HAS_atmega323_TRUE= + HAS_atmega323_FALSE='#' +else + HAS_atmega323_TRUE='#' + HAS_atmega323_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega324a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324a" >&5 +$as_echo_n "checking if ${CC} has support for atmega324a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega324a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega324a" = "xyes"; then + HAS_atmega324a_TRUE= + HAS_atmega324a_FALSE='#' +else + HAS_atmega324a_TRUE='#' + HAS_atmega324a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega324p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324p" >&5 +$as_echo_n "checking if ${CC} has support for atmega324p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega324p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega324p" = "xyes"; then + HAS_atmega324p_TRUE= + HAS_atmega324p_FALSE='#' +else + HAS_atmega324p_TRUE='#' + HAS_atmega324p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega324pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega324pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega324pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega324pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega324pa" = "xyes"; then + HAS_atmega324pa_TRUE= + HAS_atmega324pa_FALSE='#' +else + HAS_atmega324pa_TRUE='#' + HAS_atmega324pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega325" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325" >&5 +$as_echo_n "checking if ${CC} has support for atmega325... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega325=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega325" = "xyes"; then + HAS_atmega325_TRUE= + HAS_atmega325_FALSE='#' +else + HAS_atmega325_TRUE='#' + HAS_atmega325_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega325a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325a" >&5 +$as_echo_n "checking if ${CC} has support for atmega325a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega325a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega325a" = "xyes"; then + HAS_atmega325a_TRUE= + HAS_atmega325a_FALSE='#' +else + HAS_atmega325a_TRUE='#' + HAS_atmega325a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega325p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325p" >&5 +$as_echo_n "checking if ${CC} has support for atmega325p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega325p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega325p" = "xyes"; then + HAS_atmega325p_TRUE= + HAS_atmega325p_FALSE='#' +else + HAS_atmega325p_TRUE='#' + HAS_atmega325p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega325pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega325pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega325pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega325pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega325pa" = "xyes"; then + HAS_atmega325pa_TRUE= + HAS_atmega325pa_FALSE='#' +else + HAS_atmega325pa_TRUE='#' + HAS_atmega325pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3250" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250" >&5 +$as_echo_n "checking if ${CC} has support for atmega3250... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3250=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3250" = "xyes"; then + HAS_atmega3250_TRUE= + HAS_atmega3250_FALSE='#' +else + HAS_atmega3250_TRUE='#' + HAS_atmega3250_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3250a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250a" >&5 +$as_echo_n "checking if ${CC} has support for atmega3250a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3250a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3250a" = "xyes"; then + HAS_atmega3250a_TRUE= + HAS_atmega3250a_FALSE='#' +else + HAS_atmega3250a_TRUE='#' + HAS_atmega3250a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3250p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250p" >&5 +$as_echo_n "checking if ${CC} has support for atmega3250p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3250p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3250p" = "xyes"; then + HAS_atmega3250p_TRUE= + HAS_atmega3250p_FALSE='#' +else + HAS_atmega3250p_TRUE='#' + HAS_atmega3250p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3250pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3250pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega3250pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3250pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3250pa" = "xyes"; then + HAS_atmega3250pa_TRUE= + HAS_atmega3250pa_FALSE='#' +else + HAS_atmega3250pa_TRUE='#' + HAS_atmega3250pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega328" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328" >&5 +$as_echo_n "checking if ${CC} has support for atmega328... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega328=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega328" = "xyes"; then + HAS_atmega328_TRUE= + HAS_atmega328_FALSE='#' +else + HAS_atmega328_TRUE='#' + HAS_atmega328_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega328p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega328p" >&5 +$as_echo_n "checking if ${CC} has support for atmega328p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega328p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega328p" = "xyes"; then + HAS_atmega328p_TRUE= + HAS_atmega328p_FALSE='#' +else + HAS_atmega328p_TRUE='#' + HAS_atmega328p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega329" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329" >&5 +$as_echo_n "checking if ${CC} has support for atmega329... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega329=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega329" = "xyes"; then + HAS_atmega329_TRUE= + HAS_atmega329_FALSE='#' +else + HAS_atmega329_TRUE='#' + HAS_atmega329_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega329a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329a" >&5 +$as_echo_n "checking if ${CC} has support for atmega329a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega329a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega329a" = "xyes"; then + HAS_atmega329a_TRUE= + HAS_atmega329a_FALSE='#' +else + HAS_atmega329a_TRUE='#' + HAS_atmega329a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega329p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329p" >&5 +$as_echo_n "checking if ${CC} has support for atmega329p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega329p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega329p" = "xyes"; then + HAS_atmega329p_TRUE= + HAS_atmega329p_FALSE='#' +else + HAS_atmega329p_TRUE='#' + HAS_atmega329p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega329pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega329pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega329pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega329pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega329pa" = "xyes"; then + HAS_atmega329pa_TRUE= + HAS_atmega329pa_FALSE='#' +else + HAS_atmega329pa_TRUE='#' + HAS_atmega329pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3290" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290" >&5 +$as_echo_n "checking if ${CC} has support for atmega3290... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3290=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3290" = "xyes"; then + HAS_atmega3290_TRUE= + HAS_atmega3290_FALSE='#' +else + HAS_atmega3290_TRUE='#' + HAS_atmega3290_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3290a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290a" >&5 +$as_echo_n "checking if ${CC} has support for atmega3290a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3290a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3290a" = "xyes"; then + HAS_atmega3290a_TRUE= + HAS_atmega3290a_FALSE='#' +else + HAS_atmega3290a_TRUE='#' + HAS_atmega3290a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3290p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290p" >&5 +$as_echo_n "checking if ${CC} has support for atmega3290p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3290p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3290p" = "xyes"; then + HAS_atmega3290p_TRUE= + HAS_atmega3290p_FALSE='#' +else + HAS_atmega3290p_TRUE='#' + HAS_atmega3290p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega3290pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega3290pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega3290pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega3290pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega3290pa" = "xyes"; then + HAS_atmega3290pa_TRUE= + HAS_atmega3290pa_FALSE='#' +else + HAS_atmega3290pa_TRUE='#' + HAS_atmega3290pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32c1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32c1" >&5 +$as_echo_n "checking if ${CC} has support for atmega32c1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32c1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32c1" = "xyes"; then + HAS_atmega32c1_TRUE= + HAS_atmega32c1_FALSE='#' +else + HAS_atmega32c1_TRUE='#' + HAS_atmega32c1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32hvb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvb" >&5 +$as_echo_n "checking if ${CC} has support for atmega32hvb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32hvb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32hvb" = "xyes"; then + HAS_atmega32hvb_TRUE= + HAS_atmega32hvb_FALSE='#' +else + HAS_atmega32hvb_TRUE='#' + HAS_atmega32hvb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32hvbrevb" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32hvbrevb" >&5 +$as_echo_n "checking if ${CC} has support for atmega32hvbrevb... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32hvbrevb=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32hvbrevb" = "xyes"; then + HAS_atmega32hvbrevb_TRUE= + HAS_atmega32hvbrevb_FALSE='#' +else + HAS_atmega32hvbrevb_TRUE='#' + HAS_atmega32hvbrevb_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32m1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32m1" >&5 +$as_echo_n "checking if ${CC} has support for atmega32m1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32m1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32m1" = "xyes"; then + HAS_atmega32m1_TRUE= + HAS_atmega32m1_FALSE='#' +else + HAS_atmega32m1_TRUE='#' + HAS_atmega32m1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32u4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u4" >&5 +$as_echo_n "checking if ${CC} has support for atmega32u4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32u4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32u4" = "xyes"; then + HAS_atmega32u4_TRUE= + HAS_atmega32u4_FALSE='#' +else + HAS_atmega32u4_TRUE='#' + HAS_atmega32u4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega32u6" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega32u6" >&5 +$as_echo_n "checking if ${CC} has support for atmega32u6... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega32u6=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega32u6" = "xyes"; then + HAS_atmega32u6_TRUE= + HAS_atmega32u6_FALSE='#' +else + HAS_atmega32u6_TRUE='#' + HAS_atmega32u6_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega406" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega406" >&5 +$as_echo_n "checking if ${CC} has support for atmega406... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega406=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega406" = "xyes"; then + HAS_atmega406_TRUE= + HAS_atmega406_FALSE='#' +else + HAS_atmega406_TRUE='#' + HAS_atmega406_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega644rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega644rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega644rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega644rfr2" = "xyes"; then + HAS_atmega644rfr2_TRUE= + HAS_atmega644rfr2_FALSE='#' +else + HAS_atmega644rfr2_TRUE='#' + HAS_atmega644rfr2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega64rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64rfr2" = "xyes"; then + HAS_atmega64rfr2_TRUE= + HAS_atmega64rfr2_FALSE='#' +else + HAS_atmega64rfr2_TRUE='#' + HAS_atmega64rfr2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64" >&5 +$as_echo_n "checking if ${CC} has support for atmega64... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64" = "xyes"; then + HAS_atmega64_TRUE= + HAS_atmega64_FALSE='#' +else + HAS_atmega64_TRUE='#' + HAS_atmega64_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64a" >&5 +$as_echo_n "checking if ${CC} has support for atmega64a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64a" = "xyes"; then + HAS_atmega64a_TRUE= + HAS_atmega64a_FALSE='#' +else + HAS_atmega64a_TRUE='#' + HAS_atmega64a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega640" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega640" >&5 +$as_echo_n "checking if ${CC} has support for atmega640... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega640=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega640" = "xyes"; then + HAS_atmega640_TRUE= + HAS_atmega640_FALSE='#' +else + HAS_atmega640_TRUE='#' + HAS_atmega640_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega644" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644" >&5 +$as_echo_n "checking if ${CC} has support for atmega644... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega644=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega644" = "xyes"; then + HAS_atmega644_TRUE= + HAS_atmega644_FALSE='#' +else + HAS_atmega644_TRUE='#' + HAS_atmega644_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega644a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644a" >&5 +$as_echo_n "checking if ${CC} has support for atmega644a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega644a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega644a" = "xyes"; then + HAS_atmega644a_TRUE= + HAS_atmega644a_FALSE='#' +else + HAS_atmega644a_TRUE='#' + HAS_atmega644a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega644p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644p" >&5 +$as_echo_n "checking if ${CC} has support for atmega644p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega644p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega644p" = "xyes"; then + HAS_atmega644p_TRUE= + HAS_atmega644p_FALSE='#' +else + HAS_atmega644p_TRUE='#' + HAS_atmega644p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega644pa" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega644pa" >&5 +$as_echo_n "checking if ${CC} has support for atmega644pa... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega644pa=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega644pa" = "xyes"; then + HAS_atmega644pa_TRUE= + HAS_atmega644pa_FALSE='#' +else + HAS_atmega644pa_TRUE='#' + HAS_atmega644pa_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega645" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645" >&5 +$as_echo_n "checking if ${CC} has support for atmega645... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega645=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega645" = "xyes"; then + HAS_atmega645_TRUE= + HAS_atmega645_FALSE='#' +else + HAS_atmega645_TRUE='#' + HAS_atmega645_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega645a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645a" >&5 +$as_echo_n "checking if ${CC} has support for atmega645a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega645a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega645a" = "xyes"; then + HAS_atmega645a_TRUE= + HAS_atmega645a_FALSE='#' +else + HAS_atmega645a_TRUE='#' + HAS_atmega645a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega645p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega645p" >&5 +$as_echo_n "checking if ${CC} has support for atmega645p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega645p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega645p" = "xyes"; then + HAS_atmega645p_TRUE= + HAS_atmega645p_FALSE='#' +else + HAS_atmega645p_TRUE='#' + HAS_atmega645p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6450" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450" >&5 +$as_echo_n "checking if ${CC} has support for atmega6450... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6450=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6450" = "xyes"; then + HAS_atmega6450_TRUE= + HAS_atmega6450_FALSE='#' +else + HAS_atmega6450_TRUE='#' + HAS_atmega6450_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6450a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450a" >&5 +$as_echo_n "checking if ${CC} has support for atmega6450a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6450a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6450a" = "xyes"; then + HAS_atmega6450a_TRUE= + HAS_atmega6450a_FALSE='#' +else + HAS_atmega6450a_TRUE='#' + HAS_atmega6450a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6450p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6450p" >&5 +$as_echo_n "checking if ${CC} has support for atmega6450p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6450p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6450p" = "xyes"; then + HAS_atmega6450p_TRUE= + HAS_atmega6450p_FALSE='#' +else + HAS_atmega6450p_TRUE='#' + HAS_atmega6450p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega649" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649" >&5 +$as_echo_n "checking if ${CC} has support for atmega649... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega649=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega649" = "xyes"; then + HAS_atmega649_TRUE= + HAS_atmega649_FALSE='#' +else + HAS_atmega649_TRUE='#' + HAS_atmega649_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega649a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649a" >&5 +$as_echo_n "checking if ${CC} has support for atmega649a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega649a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega649a" = "xyes"; then + HAS_atmega649a_TRUE= + HAS_atmega649a_FALSE='#' +else + HAS_atmega649a_TRUE='#' + HAS_atmega649a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega649p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega649p" >&5 +$as_echo_n "checking if ${CC} has support for atmega649p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega649p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega649p" = "xyes"; then + HAS_atmega649p_TRUE= + HAS_atmega649p_FALSE='#' +else + HAS_atmega649p_TRUE='#' + HAS_atmega649p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6490" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490" >&5 +$as_echo_n "checking if ${CC} has support for atmega6490... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6490=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6490" = "xyes"; then + HAS_atmega6490_TRUE= + HAS_atmega6490_FALSE='#' +else + HAS_atmega6490_TRUE='#' + HAS_atmega6490_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6490a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490a" >&5 +$as_echo_n "checking if ${CC} has support for atmega6490a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6490a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6490a" = "xyes"; then + HAS_atmega6490a_TRUE= + HAS_atmega6490a_FALSE='#' +else + HAS_atmega6490a_TRUE='#' + HAS_atmega6490a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega6490p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega6490p" >&5 +$as_echo_n "checking if ${CC} has support for atmega6490p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega6490p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega6490p" = "xyes"; then + HAS_atmega6490p_TRUE= + HAS_atmega6490p_FALSE='#' +else + HAS_atmega6490p_TRUE='#' + HAS_atmega6490p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64c1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64c1" >&5 +$as_echo_n "checking if ${CC} has support for atmega64c1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64c1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64c1" = "xyes"; then + HAS_atmega64c1_TRUE= + HAS_atmega64c1_FALSE='#' +else + HAS_atmega64c1_TRUE='#' + HAS_atmega64c1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64hve" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64hve" >&5 +$as_echo_n "checking if ${CC} has support for atmega64hve... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64hve=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64hve" = "xyes"; then + HAS_atmega64hve_TRUE= + HAS_atmega64hve_FALSE='#' +else + HAS_atmega64hve_TRUE='#' + HAS_atmega64hve_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64hve2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64hve2" >&5 +$as_echo_n "checking if ${CC} has support for atmega64hve2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64hve2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64hve2" = "xyes"; then + HAS_atmega64hve2_TRUE= + HAS_atmega64hve2_FALSE='#' +else + HAS_atmega64hve2_TRUE='#' + HAS_atmega64hve2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega64m1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega64m1" >&5 +$as_echo_n "checking if ${CC} has support for atmega64m1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega64m1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega64m1" = "xyes"; then + HAS_atmega64m1_TRUE= + HAS_atmega64m1_FALSE='#' +else + HAS_atmega64m1_TRUE='#' + HAS_atmega64m1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega128rfa1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128rfa1" >&5 +$as_echo_n "checking if ${CC} has support for atmega128rfa1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega128rfa1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega128rfa1" = "xyes"; then + HAS_atmega128rfa1_TRUE= + HAS_atmega128rfa1_FALSE='#' +else + HAS_atmega128rfa1_TRUE='#' + HAS_atmega128rfa1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=m3000" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for m3000" >&5 +$as_echo_n "checking if ${CC} has support for m3000... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_m3000=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_m3000" = "xyes"; then + HAS_m3000_TRUE= + HAS_m3000_FALSE='#' +else + HAS_m3000_TRUE='#' + HAS_m3000_FALSE= +fi + + + + +#avr51 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avr51" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr51" >&5 +$as_echo_n "checking if ${CC} has support for avr51... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avr51=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avr51" = "xyes"; then + HAS_avr51_TRUE= + HAS_avr51_FALSE='#' +else + HAS_avr51_TRUE='#' + HAS_avr51_FALSE= +fi + + + if true; then + HAS_atmega128_TRUE= + HAS_atmega128_FALSE='#' +else + HAS_atmega128_TRUE='#' + HAS_atmega128_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega128a" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128a" >&5 +$as_echo_n "checking if ${CC} has support for atmega128a... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega128a=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega128a" = "xyes"; then + HAS_atmega128a_TRUE= + HAS_atmega128a_FALSE='#' +else + HAS_atmega128a_TRUE='#' + HAS_atmega128a_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega1280" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1280" >&5 +$as_echo_n "checking if ${CC} has support for atmega1280... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega1280=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega1280" = "xyes"; then + HAS_atmega1280_TRUE= + HAS_atmega1280_FALSE='#' +else + HAS_atmega1280_TRUE='#' + HAS_atmega1280_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega1281" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1281" >&5 +$as_echo_n "checking if ${CC} has support for atmega1281... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega1281=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega1281" = "xyes"; then + HAS_atmega1281_TRUE= + HAS_atmega1281_FALSE='#' +else + HAS_atmega1281_TRUE='#' + HAS_atmega1281_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega1284" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284" >&5 +$as_echo_n "checking if ${CC} has support for atmega1284... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega1284=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega1284" = "xyes"; then + HAS_atmega1284_TRUE= + HAS_atmega1284_FALSE='#' +else + HAS_atmega1284_TRUE='#' + HAS_atmega1284_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega1284p" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284p" >&5 +$as_echo_n "checking if ${CC} has support for atmega1284p... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega1284p=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega1284p" = "xyes"; then + HAS_atmega1284p_TRUE= + HAS_atmega1284p_FALSE='#' +else + HAS_atmega1284p_TRUE='#' + HAS_atmega1284p_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90can128" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90can128" >&5 +$as_echo_n "checking if ${CC} has support for at90can128... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90can128=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90can128" = "xyes"; then + HAS_at90can128_TRUE= + HAS_at90can128_FALSE='#' +else + HAS_at90can128_TRUE='#' + HAS_at90can128_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb1286" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1286" >&5 +$as_echo_n "checking if ${CC} has support for at90usb1286... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb1286=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb1286" = "xyes"; then + HAS_at90usb1286_TRUE= + HAS_at90usb1286_FALSE='#' +else + HAS_at90usb1286_TRUE='#' + HAS_at90usb1286_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=at90usb1287" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for at90usb1287" >&5 +$as_echo_n "checking if ${CC} has support for at90usb1287... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_at90usb1287=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_at90usb1287" = "xyes"; then + HAS_at90usb1287_TRUE= + HAS_at90usb1287_FALSE='#' +else + HAS_at90usb1287_TRUE='#' + HAS_at90usb1287_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega1284rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega1284rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega1284rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega1284rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega1284rfr2" = "xyes"; then + HAS_atmega1284rfr2_TRUE= + HAS_atmega1284rfr2_FALSE='#' +else + HAS_atmega1284rfr2_TRUE='#' + HAS_atmega1284rfr2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega128rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega128rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega128rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega128rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega128rfr2" = "xyes"; then + HAS_atmega128rfr2_TRUE= + HAS_atmega128rfr2_FALSE='#' +else + HAS_atmega128rfr2_TRUE='#' + HAS_atmega128rfr2_FALSE= +fi + + + +# avr6 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avr6" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avr6" >&5 +$as_echo_n "checking if ${CC} has support for avr6... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avr6=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avr6" = "xyes"; then + HAS_avr6_TRUE= + HAS_avr6_FALSE='#' +else + HAS_avr6_TRUE='#' + HAS_avr6_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega2560" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2560" >&5 +$as_echo_n "checking if ${CC} has support for atmega2560... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega2560=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega2560" = "xyes"; then + HAS_atmega2560_TRUE= + HAS_atmega2560_FALSE='#' +else + HAS_atmega2560_TRUE='#' + HAS_atmega2560_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega2561" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2561" >&5 +$as_echo_n "checking if ${CC} has support for atmega2561... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega2561=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega2561" = "xyes"; then + HAS_atmega2561_TRUE= + HAS_atmega2561_FALSE='#' +else + HAS_atmega2561_TRUE='#' + HAS_atmega2561_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega2564rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega2564rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega2564rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega2564rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega2564rfr2" = "xyes"; then + HAS_atmega2564rfr2_TRUE= + HAS_atmega2564rfr2_FALSE='#' +else + HAS_atmega2564rfr2_TRUE='#' + HAS_atmega2564rfr2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atmega256rfr2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atmega256rfr2" >&5 +$as_echo_n "checking if ${CC} has support for atmega256rfr2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atmega256rfr2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atmega256rfr2" = "xyes"; then + HAS_atmega256rfr2_TRUE= + HAS_atmega256rfr2_FALSE='#' +else + HAS_atmega256rfr2_TRUE='#' + HAS_atmega256rfr2_FALSE= +fi + + + +# avrxmega2 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega2" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega2" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega2... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega2=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega2" = "xyes"; then + HAS_avrxmega2_TRUE= + HAS_avrxmega2_FALSE='#' +else + HAS_avrxmega2_TRUE='#' + HAS_avrxmega2_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega8e5" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega8e5" >&5 +$as_echo_n "checking if ${CC} has support for atxmega8e5... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega8e5=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega8e5" = "xyes"; then + HAS_atxmega8e5_TRUE= + HAS_atxmega8e5_FALSE='#' +else + HAS_atxmega8e5_TRUE='#' + HAS_atxmega8e5_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega16a4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16a4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega16a4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega16a4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega16a4" = "xyes"; then + HAS_atxmega16a4_TRUE= + HAS_atxmega16a4_FALSE='#' +else + HAS_atxmega16a4_TRUE='#' + HAS_atxmega16a4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega16a4u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16a4u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega16a4u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega16a4u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega16a4u" = "xyes"; then + HAS_atxmega16a4u_TRUE= + HAS_atxmega16a4u_FALSE='#' +else + HAS_atxmega16a4u_TRUE='#' + HAS_atxmega16a4u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega16c4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16c4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega16c4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega16c4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega16c4" = "xyes"; then + HAS_atxmega16c4_TRUE= + HAS_atxmega16c4_FALSE='#' +else + HAS_atxmega16c4_TRUE='#' + HAS_atxmega16c4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega16d4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16d4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega16d4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega16d4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega16d4" = "xyes"; then + HAS_atxmega16d4_TRUE= + HAS_atxmega16d4_FALSE='#' +else + HAS_atxmega16d4_TRUE='#' + HAS_atxmega16d4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32a4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32a4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32a4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32a4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32a4" = "xyes"; then + HAS_atxmega32a4_TRUE= + HAS_atxmega32a4_FALSE='#' +else + HAS_atxmega32a4_TRUE='#' + HAS_atxmega32a4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32a4u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32a4u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32a4u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32a4u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32a4u" = "xyes"; then + HAS_atxmega32a4u_TRUE= + HAS_atxmega32a4u_FALSE='#' +else + HAS_atxmega32a4u_TRUE='#' + HAS_atxmega32a4u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32c3" = "xyes"; then + HAS_atxmega32c3_TRUE= + HAS_atxmega32c3_FALSE='#' +else + HAS_atxmega32c3_TRUE='#' + HAS_atxmega32c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32c4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32c4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32c4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32c4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32c4" = "xyes"; then + HAS_atxmega32c4_TRUE= + HAS_atxmega32c4_FALSE='#' +else + HAS_atxmega32c4_TRUE='#' + HAS_atxmega32c4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32d3" = "xyes"; then + HAS_atxmega32d3_TRUE= + HAS_atxmega32d3_FALSE='#' +else + HAS_atxmega32d3_TRUE='#' + HAS_atxmega32d3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32d4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32d4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32d4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32d4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32d4" = "xyes"; then + HAS_atxmega32d4_TRUE= + HAS_atxmega32d4_FALSE='#' +else + HAS_atxmega32d4_TRUE='#' + HAS_atxmega32d4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega16e5" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega16e5" >&5 +$as_echo_n "checking if ${CC} has support for atxmega16e5... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega16e5=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega16e5" = "xyes"; then + HAS_atxmega16e5_TRUE= + HAS_atxmega16e5_FALSE='#' +else + HAS_atxmega16e5_TRUE='#' + HAS_atxmega16e5_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega32e5" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega32e5" >&5 +$as_echo_n "checking if ${CC} has support for atxmega32e5... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega32e5=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega32e5" = "xyes"; then + HAS_atxmega32e5_TRUE= + HAS_atxmega32e5_FALSE='#' +else + HAS_atxmega32e5_TRUE='#' + HAS_atxmega32e5_FALSE= +fi + + + +# avrxmega3 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega3" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega3" = "xyes"; then + HAS_avrxmega3_TRUE= + HAS_avrxmega3_FALSE='#' +else + HAS_avrxmega3_TRUE='#' + HAS_avrxmega3_FALSE= +fi + + + +# avrxmega4 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega4" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega4" = "xyes"; then + HAS_avrxmega4_TRUE= + HAS_avrxmega4_FALSE='#' +else + HAS_avrxmega4_TRUE='#' + HAS_avrxmega4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64a3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64a3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64a3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64a3" = "xyes"; then + HAS_atxmega64a3_TRUE= + HAS_atxmega64a3_FALSE='#' +else + HAS_atxmega64a3_TRUE='#' + HAS_atxmega64a3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64a3u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a3u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64a3u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64a3u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64a3u" = "xyes"; then + HAS_atxmega64a3u_TRUE= + HAS_atxmega64a3u_FALSE='#' +else + HAS_atxmega64a3u_TRUE='#' + HAS_atxmega64a3u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64a4u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a4u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64a4u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64a4u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64a4u" = "xyes"; then + HAS_atxmega64a4u_TRUE= + HAS_atxmega64a4u_FALSE='#' +else + HAS_atxmega64a4u_TRUE='#' + HAS_atxmega64a4u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64b1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64b1" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64b1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64b1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64b1" = "xyes"; then + HAS_atxmega64b1_TRUE= + HAS_atxmega64b1_FALSE='#' +else + HAS_atxmega64b1_TRUE='#' + HAS_atxmega64b1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64b3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64b3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64b3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64b3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64b3" = "xyes"; then + HAS_atxmega64b3_TRUE= + HAS_atxmega64b3_FALSE='#' +else + HAS_atxmega64b3_TRUE='#' + HAS_atxmega64b3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64c3" = "xyes"; then + HAS_atxmega64c3_TRUE= + HAS_atxmega64c3_FALSE='#' +else + HAS_atxmega64c3_TRUE='#' + HAS_atxmega64c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64d3" = "xyes"; then + HAS_atxmega64d3_TRUE= + HAS_atxmega64d3_FALSE='#' +else + HAS_atxmega64d3_TRUE='#' + HAS_atxmega64d3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64d4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64d4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64d4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64d4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64d4" = "xyes"; then + HAS_atxmega64d4_TRUE= + HAS_atxmega64d4_FALSE='#' +else + HAS_atxmega64d4_TRUE='#' + HAS_atxmega64d4_FALSE= +fi + + + +# avrxmega5 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega5" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega5" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega5... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega5=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega5" = "xyes"; then + HAS_avrxmega5_TRUE= + HAS_avrxmega5_FALSE='#' +else + HAS_avrxmega5_TRUE='#' + HAS_avrxmega5_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64a1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64a1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64a1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64a1" = "xyes"; then + HAS_atxmega64a1_TRUE= + HAS_atxmega64a1_FALSE='#' +else + HAS_atxmega64a1_TRUE='#' + HAS_atxmega64a1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega64a1u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega64a1u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega64a1u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega64a1u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega64a1u" = "xyes"; then + HAS_atxmega64a1u_TRUE= + HAS_atxmega64a1u_FALSE='#' +else + HAS_atxmega64a1u_TRUE='#' + HAS_atxmega64a1u_FALSE= +fi + + + +# avrxmega6 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega6" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega6" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega6... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega6=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega6" = "xyes"; then + HAS_avrxmega6_TRUE= + HAS_avrxmega6_FALSE='#' +else + HAS_avrxmega6_TRUE='#' + HAS_avrxmega6_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128a3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128a3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128a3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128a3" = "xyes"; then + HAS_atxmega128a3_TRUE= + HAS_atxmega128a3_FALSE='#' +else + HAS_atxmega128a3_TRUE='#' + HAS_atxmega128a3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128a3u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a3u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128a3u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128a3u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128a3u" = "xyes"; then + HAS_atxmega128a3u_TRUE= + HAS_atxmega128a3u_FALSE='#' +else + HAS_atxmega128a3u_TRUE='#' + HAS_atxmega128a3u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128b1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128b1" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128b1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128b1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128b1" = "xyes"; then + HAS_atxmega128b1_TRUE= + HAS_atxmega128b1_FALSE='#' +else + HAS_atxmega128b1_TRUE='#' + HAS_atxmega128b1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128b3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128b3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128b3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128b3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128b3" = "xyes"; then + HAS_atxmega128b3_TRUE= + HAS_atxmega128b3_FALSE='#' +else + HAS_atxmega128b3_TRUE='#' + HAS_atxmega128b3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128c3" = "xyes"; then + HAS_atxmega128c3_TRUE= + HAS_atxmega128c3_FALSE='#' +else + HAS_atxmega128c3_TRUE='#' + HAS_atxmega128c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128d3" = "xyes"; then + HAS_atxmega128d3_TRUE= + HAS_atxmega128d3_FALSE='#' +else + HAS_atxmega128d3_TRUE='#' + HAS_atxmega128d3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128d4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128d4" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128d4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128d4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128d4" = "xyes"; then + HAS_atxmega128d4_TRUE= + HAS_atxmega128d4_FALSE='#' +else + HAS_atxmega128d4_TRUE='#' + HAS_atxmega128d4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega192a3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192a3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega192a3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega192a3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega192a3" = "xyes"; then + HAS_atxmega192a3_TRUE= + HAS_atxmega192a3_FALSE='#' +else + HAS_atxmega192a3_TRUE='#' + HAS_atxmega192a3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega192a3u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192a3u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega192a3u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega192a3u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega192a3u" = "xyes"; then + HAS_atxmega192a3u_TRUE= + HAS_atxmega192a3u_FALSE='#' +else + HAS_atxmega192a3u_TRUE='#' + HAS_atxmega192a3u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega192c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega192c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega192c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega192c3" = "xyes"; then + HAS_atxmega192c3_TRUE= + HAS_atxmega192c3_FALSE='#' +else + HAS_atxmega192c3_TRUE='#' + HAS_atxmega192c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega192d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega192d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega192d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega192d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega192d3" = "xyes"; then + HAS_atxmega192d3_TRUE= + HAS_atxmega192d3_FALSE='#' +else + HAS_atxmega192d3_TRUE='#' + HAS_atxmega192d3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256a3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256a3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256a3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256a3" = "xyes"; then + HAS_atxmega256a3_TRUE= + HAS_atxmega256a3_FALSE='#' +else + HAS_atxmega256a3_TRUE='#' + HAS_atxmega256a3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256a3u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256a3u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256a3u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256a3u" = "xyes"; then + HAS_atxmega256a3u_TRUE= + HAS_atxmega256a3u_FALSE='#' +else + HAS_atxmega256a3u_TRUE='#' + HAS_atxmega256a3u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256a3b" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3b" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256a3b... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256a3b=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256a3b" = "xyes"; then + HAS_atxmega256a3b_TRUE= + HAS_atxmega256a3b_FALSE='#' +else + HAS_atxmega256a3b_TRUE='#' + HAS_atxmega256a3b_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256a3bu" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256a3bu" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256a3bu... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256a3bu=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256a3bu" = "xyes"; then + HAS_atxmega256a3bu_TRUE= + HAS_atxmega256a3bu_FALSE='#' +else + HAS_atxmega256a3bu_TRUE='#' + HAS_atxmega256a3bu_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256c3" = "xyes"; then + HAS_atxmega256c3_TRUE= + HAS_atxmega256c3_FALSE='#' +else + HAS_atxmega256c3_TRUE='#' + HAS_atxmega256c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega256d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega256d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega256d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega256d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega256d3" = "xyes"; then + HAS_atxmega256d3_TRUE= + HAS_atxmega256d3_FALSE='#' +else + HAS_atxmega256d3_TRUE='#' + HAS_atxmega256d3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega384c3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega384c3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega384c3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega384c3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega384c3" = "xyes"; then + HAS_atxmega384c3_TRUE= + HAS_atxmega384c3_FALSE='#' +else + HAS_atxmega384c3_TRUE='#' + HAS_atxmega384c3_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega384d3" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega384d3" >&5 +$as_echo_n "checking if ${CC} has support for atxmega384d3... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega384d3=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega384d3" = "xyes"; then + HAS_atxmega384d3_TRUE= + HAS_atxmega384d3_FALSE='#' +else + HAS_atxmega384d3_TRUE='#' + HAS_atxmega384d3_FALSE= +fi + + +# avrxmega7 + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrxmega7" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrxmega7" >&5 +$as_echo_n "checking if ${CC} has support for avrxmega7... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrxmega7=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrxmega7" = "xyes"; then + HAS_avrxmega7_TRUE= + HAS_avrxmega7_FALSE='#' +else + HAS_avrxmega7_TRUE='#' + HAS_avrxmega7_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128a1" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128a1... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128a1=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128a1" = "xyes"; then + HAS_atxmega128a1_TRUE= + HAS_atxmega128a1_FALSE='#' +else + HAS_atxmega128a1_TRUE='#' + HAS_atxmega128a1_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128a1u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a1u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128a1u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128a1u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128a1u" = "xyes"; then + HAS_atxmega128a1u_TRUE= + HAS_atxmega128a1u_FALSE='#' +else + HAS_atxmega128a1u_TRUE='#' + HAS_atxmega128a1u_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=atxmega128a4u" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for atxmega128a4u" >&5 +$as_echo_n "checking if ${CC} has support for atxmega128a4u... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_atxmega128a4u=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_atxmega128a4u" = "xyes"; then + HAS_atxmega128a4u_TRUE= + HAS_atxmega128a4u_FALSE='#' +else + HAS_atxmega128a4u_TRUE='#' + HAS_atxmega128a4u_FALSE= +fi + + + +# avrtiny + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=avrtiny" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for avrtiny" >&5 +$as_echo_n "checking if ${CC} has support for avrtiny... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_avrtiny=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_avrtiny" = "xyes"; then + HAS_avrtiny_TRUE= + HAS_avrtiny_FALSE='#' +else + HAS_avrtiny_TRUE='#' + HAS_avrtiny_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny4" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny4" >&5 +$as_echo_n "checking if ${CC} has support for attiny4... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny4=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny4" = "xyes"; then + HAS_attiny4_TRUE= + HAS_attiny4_FALSE='#' +else + HAS_attiny4_TRUE='#' + HAS_attiny4_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny5" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny5" >&5 +$as_echo_n "checking if ${CC} has support for attiny5... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny5=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny5" = "xyes"; then + HAS_attiny5_TRUE= + HAS_attiny5_FALSE='#' +else + HAS_attiny5_TRUE='#' + HAS_attiny5_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny9" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny9" >&5 +$as_echo_n "checking if ${CC} has support for attiny9... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny9=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny9" = "xyes"; then + HAS_attiny9_TRUE= + HAS_attiny9_FALSE='#' +else + HAS_attiny9_TRUE='#' + HAS_attiny9_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny10" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny10" >&5 +$as_echo_n "checking if ${CC} has support for attiny10... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny10=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny10" = "xyes"; then + HAS_attiny10_TRUE= + HAS_attiny10_FALSE='#' +else + HAS_attiny10_TRUE='#' + HAS_attiny10_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny20" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny20" >&5 +$as_echo_n "checking if ${CC} has support for attiny20... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny20=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny20" = "xyes"; then + HAS_attiny20_TRUE= + HAS_attiny20_FALSE='#' +else + HAS_attiny20_TRUE='#' + HAS_attiny20_FALSE= +fi + + + + old_CC=${CC} + old_CFLAGS=${CFLAGS} + CFLAGS="-mmcu=attiny40" + CC=`echo "${CC}" | sed 's/-mmcu=avr.//'` + { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ${CC} has support for attiny40" >&5 +$as_echo_n "checking if ${CC} has support for attiny40... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ + +_ACEOF +if ac_fn_c_try_compile "$LINENO"; then : + has_dev_support=yes +else + has_dev_support=no + +fi +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "x$has_dev_support" = "xyes" + then + HAS_attiny40=yes + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $has_dev_support" >&5 +$as_echo "$has_dev_support" >&6; } + CC=${old_CC} + CFLAGS=${old_CFLAGS} + + + if test "x$HAS_attiny40" = "xyes"; then + HAS_attiny40_TRUE= + HAS_attiny40_FALSE='#' +else + HAS_attiny40_TRUE='#' + HAS_attiny40_FALSE= +fi + + + + + +# Generate all files from *.in sources. + +ac_config_files="$ac_config_files Makefile avr-libc.spec avr/Makefile avr/lib/Makefile common/Makefile crt1/Makefile crt1/iosym/Makefile doc/Makefile doc/api/Makefile doc/examples/Makefile include/Makefile include/avr/Makefile include/avr/builtins.h include/compat/Makefile include/util/Makefile include/util/delay.h include/sys/Makefile libc/Makefile libc/misc/Makefile libc/pmstring/Makefile libc/stdio/Makefile libc/stdlib/Makefile libc/string/Makefile libc/time/Makefile libm/Makefile libm/fplib/Makefile scripts/Makefile devtools/Makefile" + + +#avr1 and avr2 +ac_config_files="$ac_config_files avr/lib/avr2/Makefile avr/lib/avr2/at90s1200/Makefile avr/lib/avr2/at90s4414/Makefile avr/lib/avr2/at90s4434/Makefile avr/lib/avr2/at90s8515/Makefile avr/lib/avr2/at90c8534/Makefile avr/lib/avr2/at90s8535/Makefile avr/lib/avr2/attiny11/Makefile avr/lib/avr2/attiny12/Makefile avr/lib/avr2/attiny15/Makefile avr/lib/avr2/attiny28/Makefile" + + +#avr2/tiny-stack +ac_config_files="$ac_config_files avr/lib/avr2/tiny-stack/Makefile avr/lib/avr2/tiny-stack/at90s2313/Makefile avr/lib/avr2/tiny-stack/at90s2323/Makefile avr/lib/avr2/tiny-stack/at90s2333/Makefile avr/lib/avr2/tiny-stack/at90s2343/Makefile avr/lib/avr2/tiny-stack/attiny22/Makefile avr/lib/avr2/tiny-stack/attiny26/Makefile avr/lib/avr2/tiny-stack/at90s4433/Makefile" + + +#avr25 +ac_config_files="$ac_config_files avr/lib/avr25/Makefile avr/lib/avr25/at86rf401/Makefile avr/lib/avr25/ata5272/Makefile avr/lib/avr25/ata6616c/Makefile avr/lib/avr25/attiny4313/Makefile avr/lib/avr25/attiny43u/Makefile avr/lib/avr25/attiny44/Makefile avr/lib/avr25/attiny44a/Makefile avr/lib/avr25/attiny441/Makefile avr/lib/avr25/attiny45/Makefile avr/lib/avr25/attiny461/Makefile avr/lib/avr25/attiny461a/Makefile avr/lib/avr25/attiny48/Makefile avr/lib/avr25/attiny828/Makefile avr/lib/avr25/attiny84/Makefile avr/lib/avr25/attiny84a/Makefile avr/lib/avr25/attiny841/Makefile avr/lib/avr25/attiny85/Makefile avr/lib/avr25/attiny861/Makefile avr/lib/avr25/attiny861a/Makefile avr/lib/avr25/attiny87/Makefile avr/lib/avr25/attiny88/Makefile" + + +#avr25/tiny-stack +ac_config_files="$ac_config_files avr/lib/avr25/tiny-stack/Makefile avr/lib/avr25/tiny-stack/attiny13/Makefile avr/lib/avr25/tiny-stack/attiny13a/Makefile avr/lib/avr25/tiny-stack/attiny2313/Makefile avr/lib/avr25/tiny-stack/attiny2313a/Makefile avr/lib/avr25/tiny-stack/attiny24/Makefile avr/lib/avr25/tiny-stack/attiny24a/Makefile avr/lib/avr25/tiny-stack/attiny25/Makefile avr/lib/avr25/tiny-stack/attiny261/Makefile avr/lib/avr25/tiny-stack/attiny261a/Makefile" + + +#avr3 +ac_config_files="$ac_config_files avr/lib/avr3/Makefile avr/lib/avr3/at43usb355/Makefile avr/lib/avr3/at76c711/Makefile" + + +#avr31 +ac_config_files="$ac_config_files avr/lib/avr31/Makefile avr/lib/avr31/atmega103/Makefile avr/lib/avr31/at43usb320/Makefile" + + +#avr35 +ac_config_files="$ac_config_files avr/lib/avr35/Makefile avr/lib/avr35/at90usb82/Makefile avr/lib/avr35/at90usb162/Makefile avr/lib/avr35/ata5505/Makefile avr/lib/avr35/ata6617c/Makefile avr/lib/avr35/ata664251/Makefile avr/lib/avr35/atmega8u2/Makefile avr/lib/avr35/atmega16u2/Makefile avr/lib/avr35/atmega32u2/Makefile avr/lib/avr35/attiny167/Makefile avr/lib/avr35/attiny1634/Makefile" + + +#avr4 +ac_config_files="$ac_config_files avr/lib/avr4/Makefile avr/lib/avr4/ata6285/Makefile avr/lib/avr4/ata6286/Makefile avr/lib/avr4/ata6289/Makefile avr/lib/avr4/ata6612c/Makefile avr/lib/avr4/atmega48/Makefile avr/lib/avr4/atmega48a/Makefile avr/lib/avr4/atmega48pa/Makefile avr/lib/avr4/atmega48pb/Makefile avr/lib/avr4/atmega48p/Makefile avr/lib/avr4/atmega8/Makefile avr/lib/avr4/atmega8a/Makefile avr/lib/avr4/atmega88/Makefile avr/lib/avr4/atmega88a/Makefile avr/lib/avr4/atmega88p/Makefile avr/lib/avr4/atmega88pa/Makefile avr/lib/avr4/atmega88pb/Makefile avr/lib/avr4/atmega8515/Makefile avr/lib/avr4/atmega8535/Makefile avr/lib/avr4/atmega8hva/Makefile avr/lib/avr4/at90pwm1/Makefile avr/lib/avr4/at90pwm2/Makefile avr/lib/avr4/at90pwm2b/Makefile avr/lib/avr4/at90pwm3/Makefile avr/lib/avr4/at90pwm3b/Makefile avr/lib/avr4/at90pwm81/Makefile" + + +#avr5 +ac_config_files="$ac_config_files avr/lib/avr5/Makefile avr/lib/avr5/at90can32/Makefile avr/lib/avr5/at90can64/Makefile avr/lib/avr5/at90pwm216/Makefile avr/lib/avr5/at90pwm316/Makefile avr/lib/avr5/at90pwm161/Makefile avr/lib/avr5/at90scr100/Makefile avr/lib/avr5/at90usb646/Makefile avr/lib/avr5/at90usb647/Makefile avr/lib/avr5/at94k/Makefile avr/lib/avr5/ata5702m322/Makefile avr/lib/avr5/ata5782/Makefile avr/lib/avr5/ata5790/Makefile avr/lib/avr5/ata5790n/Makefile avr/lib/avr5/ata5791/Makefile avr/lib/avr5/ata5795/Makefile avr/lib/avr5/ata5831/Makefile avr/lib/avr5/ata6613c/Makefile avr/lib/avr5/ata6614q/Makefile avr/lib/avr5/ata8210/Makefile avr/lib/avr5/ata8510/Makefile avr/lib/avr5/atmega16/Makefile avr/lib/avr5/atmega16a/Makefile avr/lib/avr5/atmega161/Makefile avr/lib/avr5/atmega162/Makefile avr/lib/avr5/atmega163/Makefile avr/lib/avr5/atmega164a/Makefile avr/lib/avr5/atmega164p/Makefile avr/lib/avr5/atmega164pa/Makefile avr/lib/avr5/atmega165/Makefile avr/lib/avr5/atmega165a/Makefile avr/lib/avr5/atmega165p/Makefile avr/lib/avr5/atmega165pa/Makefile avr/lib/avr5/atmega168/Makefile avr/lib/avr5/atmega168a/Makefile avr/lib/avr5/atmega168p/Makefile avr/lib/avr5/atmega168pa/Makefile avr/lib/avr5/atmega168pb/Makefile avr/lib/avr5/atmega169/Makefile avr/lib/avr5/atmega169a/Makefile avr/lib/avr5/atmega169p/Makefile avr/lib/avr5/atmega169pa/Makefile avr/lib/avr5/atmega16hva/Makefile avr/lib/avr5/atmega16hva2/Makefile avr/lib/avr5/atmega16hvb/Makefile avr/lib/avr5/atmega16hvbrevb/Makefile avr/lib/avr5/atmega16m1/Makefile avr/lib/avr5/atmega16u4/Makefile avr/lib/avr5/atmega32/Makefile avr/lib/avr5/atmega32a/Makefile avr/lib/avr5/atmega323/Makefile avr/lib/avr5/atmega324a/Makefile avr/lib/avr5/atmega324p/Makefile avr/lib/avr5/atmega324pa/Makefile avr/lib/avr5/atmega325/Makefile avr/lib/avr5/atmega325a/Makefile avr/lib/avr5/atmega325p/Makefile avr/lib/avr5/atmega325pa/Makefile avr/lib/avr5/atmega3250/Makefile avr/lib/avr5/atmega3250a/Makefile avr/lib/avr5/atmega3250p/Makefile avr/lib/avr5/atmega3250pa/Makefile avr/lib/avr5/atmega328/Makefile avr/lib/avr5/atmega328p/Makefile avr/lib/avr5/atmega329/Makefile avr/lib/avr5/atmega329a/Makefile avr/lib/avr5/atmega329p/Makefile avr/lib/avr5/atmega329pa/Makefile avr/lib/avr5/atmega3290/Makefile avr/lib/avr5/atmega3290a/Makefile avr/lib/avr5/atmega3290p/Makefile avr/lib/avr5/atmega3290pa/Makefile avr/lib/avr5/atmega32c1/Makefile avr/lib/avr5/atmega32hvb/Makefile avr/lib/avr5/atmega32hvbrevb/Makefile avr/lib/avr5/atmega32m1/Makefile avr/lib/avr5/atmega32u4/Makefile avr/lib/avr5/atmega32u6/Makefile avr/lib/avr5/atmega406/Makefile avr/lib/avr5/atmega64rfr2/Makefile avr/lib/avr5/atmega644rfr2/Makefile avr/lib/avr5/atmega64/Makefile avr/lib/avr5/atmega64a/Makefile avr/lib/avr5/atmega640/Makefile avr/lib/avr5/atmega644/Makefile avr/lib/avr5/atmega644a/Makefile avr/lib/avr5/atmega644p/Makefile avr/lib/avr5/atmega644pa/Makefile avr/lib/avr5/atmega645/Makefile avr/lib/avr5/atmega645a/Makefile avr/lib/avr5/atmega645p/Makefile avr/lib/avr5/atmega6450/Makefile avr/lib/avr5/atmega6450a/Makefile avr/lib/avr5/atmega6450p/Makefile avr/lib/avr5/atmega649/Makefile avr/lib/avr5/atmega649a/Makefile avr/lib/avr5/atmega649p/Makefile avr/lib/avr5/atmega6490/Makefile avr/lib/avr5/atmega6490a/Makefile avr/lib/avr5/atmega6490p/Makefile avr/lib/avr5/atmega64c1/Makefile avr/lib/avr5/atmega64hve/Makefile avr/lib/avr5/atmega64hve2/Makefile avr/lib/avr5/atmega64m1/Makefile avr/lib/avr5/m3000/Makefile" + + +#avr51 +ac_config_files="$ac_config_files avr/lib/avr51/Makefile avr/lib/avr51/atmega128/Makefile avr/lib/avr51/atmega128a/Makefile avr/lib/avr51/atmega1280/Makefile avr/lib/avr51/atmega1281/Makefile avr/lib/avr51/atmega1284/Makefile avr/lib/avr51/atmega1284p/Makefile avr/lib/avr51/atmega128rfa1/Makefile avr/lib/avr51/atmega128rfr2/Makefile avr/lib/avr51/atmega1284rfr2/Makefile avr/lib/avr51/at90can128/Makefile avr/lib/avr51/at90usb1286/Makefile avr/lib/avr51/at90usb1287/Makefile" + + +#avr6 +ac_config_files="$ac_config_files avr/lib/avr6/Makefile avr/lib/avr6/atmega2560/Makefile avr/lib/avr6/atmega2561/Makefile avr/lib/avr6/atmega256rfr2/Makefile avr/lib/avr6/atmega2564rfr2/Makefile" + + +# avrxmega2 +ac_config_files="$ac_config_files avr/lib/avrxmega2/Makefile avr/lib/avrxmega2/atxmega8e5/Makefile avr/lib/avrxmega2/atxmega16a4/Makefile avr/lib/avrxmega2/atxmega16a4u/Makefile avr/lib/avrxmega2/atxmega16c4/Makefile avr/lib/avrxmega2/atxmega16d4/Makefile avr/lib/avrxmega2/atxmega16e5/Makefile avr/lib/avrxmega2/atxmega32a4/Makefile avr/lib/avrxmega2/atxmega32a4u/Makefile avr/lib/avrxmega2/atxmega32c3/Makefile avr/lib/avrxmega2/atxmega32c4/Makefile avr/lib/avrxmega2/atxmega32d3/Makefile avr/lib/avrxmega2/atxmega32d4/Makefile avr/lib/avrxmega2/atxmega32e5/Makefile" + + +# avrxmega3 +ac_config_files="$ac_config_files avr/lib/avrxmega3/Makefile" + + +# avrxmega3/short-calls +ac_config_files="$ac_config_files avr/lib/avrxmega3/short-calls/Makefile" + + +# avrxmega4 +ac_config_files="$ac_config_files avr/lib/avrxmega4/Makefile avr/lib/avrxmega4/atxmega64a3/Makefile avr/lib/avrxmega4/atxmega64a3u/Makefile avr/lib/avrxmega4/atxmega64a4u/Makefile avr/lib/avrxmega4/atxmega64b1/Makefile avr/lib/avrxmega4/atxmega64b3/Makefile avr/lib/avrxmega4/atxmega64c3/Makefile avr/lib/avrxmega4/atxmega64d3/Makefile avr/lib/avrxmega4/atxmega64d4/Makefile" + + +# avrxmega5 +ac_config_files="$ac_config_files avr/lib/avrxmega5/Makefile avr/lib/avrxmega5/atxmega64a1/Makefile avr/lib/avrxmega5/atxmega64a1u/Makefile" + + +# avrxmega6 +ac_config_files="$ac_config_files avr/lib/avrxmega6/Makefile avr/lib/avrxmega6/atxmega128a3/Makefile avr/lib/avrxmega6/atxmega128a3u/Makefile avr/lib/avrxmega6/atxmega128b1/Makefile avr/lib/avrxmega6/atxmega128b3/Makefile avr/lib/avrxmega6/atxmega128c3/Makefile avr/lib/avrxmega6/atxmega128d3/Makefile avr/lib/avrxmega6/atxmega128d4/Makefile avr/lib/avrxmega6/atxmega192a3/Makefile avr/lib/avrxmega6/atxmega192a3u/Makefile avr/lib/avrxmega6/atxmega192c3/Makefile avr/lib/avrxmega6/atxmega192d3/Makefile avr/lib/avrxmega6/atxmega256a3/Makefile avr/lib/avrxmega6/atxmega256a3u/Makefile avr/lib/avrxmega6/atxmega256a3b/Makefile avr/lib/avrxmega6/atxmega256a3bu/Makefile avr/lib/avrxmega6/atxmega256c3/Makefile avr/lib/avrxmega6/atxmega256d3/Makefile avr/lib/avrxmega6/atxmega384c3/Makefile avr/lib/avrxmega6/atxmega384d3/Makefile" + + +# avrxmega7 +ac_config_files="$ac_config_files avr/lib/avrxmega7/Makefile avr/lib/avrxmega7/atxmega128a1/Makefile avr/lib/avrxmega7/atxmega128a1u/Makefile avr/lib/avrxmega7/atxmega128a4u/Makefile" + + + +# avrtiny +ac_config_files="$ac_config_files avr/lib/avrtiny/Makefile avr/lib/avrtiny/attiny4/Makefile avr/lib/avrtiny/attiny5/Makefile avr/lib/avrtiny/attiny9/Makefile avr/lib/avrtiny/attiny10/Makefile avr/lib/avrtiny/attiny20/Makefile avr/lib/avrtiny/attiny40/Makefile" + + + +cat >confcache <<\_ACEOF +# This file is a shell script that caches the results of configure +# tests run on this system so they can be shared between configure +# scripts and configure runs, see configure's option --config-cache. +# It is not useful on other systems. If it contains results you don't +# want to keep, you may remove or edit it. +# +# config.status only pays attention to the cache file if you give it +# the --recheck option to rerun configure. +# +# `ac_cv_env_foo' variables (set or unset) will be overridden when +# loading this file, other *unset* `ac_cv_foo' will be assigned the +# following values. + +_ACEOF + +# The following way of writing the cache mishandles newlines in values, +# but we know of no workaround that is simple, portable, and efficient. +# So, we kill variables containing newlines. +# Ultrix sh set writes to stderr and can't be redirected directly, +# and sets the high bit in the cache file unless we assign to the vars. +( + for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do + eval ac_val=\$$ac_var + case $ac_val in #( + *${as_nl}*) + case $ac_var in #( + *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 +$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; + esac + case $ac_var in #( + _ | IFS | as_nl) ;; #( + BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( + *) { eval $ac_var=; unset $ac_var;} ;; + esac ;; + esac + done + + (set) 2>&1 | + case $as_nl`(ac_space=' '; set) 2>&1` in #( + *${as_nl}ac_space=\ *) + # `set' does not quote correctly, so add quotes: double-quote + # substitution turns \\\\ into \\, and sed turns \\ into \. + sed -n \ + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + ;; #( + *) + # `set' quotes correctly as required by POSIX, so do not add quotes. + sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" + ;; + esac | + sort +) | + sed ' + /^ac_cv_env_/b end + t clear + :clear + s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ + t end + s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ + :end' >>confcache +if diff "$cache_file" confcache >/dev/null 2>&1; then :; else + if test -w "$cache_file"; then + if test "x$cache_file" != "x/dev/null"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 +$as_echo "$as_me: updating cache $cache_file" >&6;} + if test ! -f "$cache_file" || test -h "$cache_file"; then + cat confcache >"$cache_file" + else + case $cache_file in #( + */* | ?:*) + mv -f confcache "$cache_file"$$ && + mv -f "$cache_file"$$ "$cache_file" ;; #( + *) + mv -f confcache "$cache_file" ;; + esac + fi + fi + else + { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 +$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} + fi +fi +rm -f confcache + +test "x$prefix" = xNONE && prefix=$ac_default_prefix +# Let make expand exec_prefix. +test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' + +DEFS=-DHAVE_CONFIG_H + +ac_libobjs= +ac_ltlibobjs= +U= +for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue + # 1. Remove the extension, and $U if already installed. + ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' + ac_i=`$as_echo "$ac_i" | sed "$ac_script"` + # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR + # will be set to the directory where LIBOBJS objects are built. + as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" + as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' +done +LIBOBJS=$ac_libobjs + +LTLIBOBJS=$ac_ltlibobjs + + +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking that generated files are newer than configure" >&5 +$as_echo_n "checking that generated files are newer than configure... " >&6; } + if test -n "$am_sleep_pid"; then + # Hide warnings about reused PIDs. + wait $am_sleep_pid 2>/dev/null + fi + { $as_echo "$as_me:${as_lineno-$LINENO}: result: done" >&5 +$as_echo "done" >&6; } + if test -n "$EXEEXT"; then + am__EXEEXT_TRUE= + am__EXEEXT_FALSE='#' +else + am__EXEEXT_TRUE='#' + am__EXEEXT_FALSE= +fi + +if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then + as_fn_error $? "conditional \"AMDEP\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCC\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then + as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_GCC_5_1_TRUE}" && test -z "${HAS_GCC_5_1_FALSE}"; then + as_fn_error $? "conditional \"HAS_GCC_5_1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_DEV_LIB_TRUE}" && test -z "${HAS_DEV_LIB_FALSE}"; then + as_fn_error $? "conditional \"HAS_DEV_LIB\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr1_TRUE}" && test -z "${HAS_avr1_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s1200_TRUE}" && test -z "${HAS_at90s1200_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s1200\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny11_TRUE}" && test -z "${HAS_attiny11_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny11\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny12_TRUE}" && test -z "${HAS_attiny12_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny12\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny15_TRUE}" && test -z "${HAS_attiny15_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny15\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny28_TRUE}" && test -z "${HAS_attiny28_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny28\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr2_TRUE}" && test -z "${HAS_avr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s2313_TRUE}" && test -z "${HAS_at90s2313_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s2313\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s2323_TRUE}" && test -z "${HAS_at90s2323_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s2323\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s2333_TRUE}" && test -z "${HAS_at90s2333_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s2333\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s2343_TRUE}" && test -z "${HAS_at90s2343_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s2343\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s4414_TRUE}" && test -z "${HAS_at90s4414_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s4414\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s4433_TRUE}" && test -z "${HAS_at90s4433_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s4433\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s4434_TRUE}" && test -z "${HAS_at90s4434_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s4434\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s8515_TRUE}" && test -z "${HAS_at90s8515_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s8515\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90c8534_TRUE}" && test -z "${HAS_at90c8534_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90c8534\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90s8535_TRUE}" && test -z "${HAS_at90s8535_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90s8535\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny22_TRUE}" && test -z "${HAS_attiny22_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny22\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny26_TRUE}" && test -z "${HAS_attiny26_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny26\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr25_TRUE}" && test -z "${HAS_avr25_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr25\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5272_TRUE}" && test -z "${HAS_ata5272_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5272\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6616c_TRUE}" && test -z "${HAS_ata6616c_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6616c\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny13_TRUE}" && test -z "${HAS_attiny13_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny13\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny13a_TRUE}" && test -z "${HAS_attiny13a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny13a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny2313_TRUE}" && test -z "${HAS_attiny2313_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny2313\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny2313a_TRUE}" && test -z "${HAS_attiny2313a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny2313a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny24_TRUE}" && test -z "${HAS_attiny24_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny24\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny24a_TRUE}" && test -z "${HAS_attiny24a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny24a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny25_TRUE}" && test -z "${HAS_attiny25_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny25\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny261_TRUE}" && test -z "${HAS_attiny261_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny261\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny261a_TRUE}" && test -z "${HAS_attiny261a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny261a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny43u_TRUE}" && test -z "${HAS_attiny43u_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny43u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny4313_TRUE}" && test -z "${HAS_attiny4313_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny4313\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny44_TRUE}" && test -z "${HAS_attiny44_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny44\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny441_TRUE}" && test -z "${HAS_attiny441_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny441\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny44a_TRUE}" && test -z "${HAS_attiny44a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny44a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny45_TRUE}" && test -z "${HAS_attiny45_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny45\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny461_TRUE}" && test -z "${HAS_attiny461_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny461\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny461a_TRUE}" && test -z "${HAS_attiny461a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny461a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny48_TRUE}" && test -z "${HAS_attiny48_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny48\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny828_TRUE}" && test -z "${HAS_attiny828_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny828\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny84_TRUE}" && test -z "${HAS_attiny84_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny84\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny841_TRUE}" && test -z "${HAS_attiny841_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny841\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny84a_TRUE}" && test -z "${HAS_attiny84a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny84a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny85_TRUE}" && test -z "${HAS_attiny85_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny85\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny861_TRUE}" && test -z "${HAS_attiny861_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny861\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny861a_TRUE}" && test -z "${HAS_attiny861a_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny861a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny87_TRUE}" && test -z "${HAS_attiny87_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny87\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny88_TRUE}" && test -z "${HAS_attiny88_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny88\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at86rf401_TRUE}" && test -z "${HAS_at86rf401_FALSE}"; then + as_fn_error $? "conditional \"HAS_at86rf401\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr3_TRUE}" && test -z "${HAS_avr3_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at43usb320_TRUE}" && test -z "${HAS_at43usb320_FALSE}"; then + as_fn_error $? "conditional \"HAS_at43usb320\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at43usb355_TRUE}" && test -z "${HAS_at43usb355_FALSE}"; then + as_fn_error $? "conditional \"HAS_at43usb355\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at76c711_TRUE}" && test -z "${HAS_at76c711_FALSE}"; then + as_fn_error $? "conditional \"HAS_at76c711\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr31_TRUE}" && test -z "${HAS_avr31_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr31\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega103_TRUE}" && test -z "${HAS_atmega103_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega103\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr35_TRUE}" && test -z "${HAS_avr35_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr35\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb82_TRUE}" && test -z "${HAS_at90usb82_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb82\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb162_TRUE}" && test -z "${HAS_at90usb162_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb162\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5505_TRUE}" && test -z "${HAS_ata5505_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5505\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6617c_TRUE}" && test -z "${HAS_ata6617c_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6617c\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata664251_TRUE}" && test -z "${HAS_ata664251_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata664251\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8u2_TRUE}" && test -z "${HAS_atmega8u2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8u2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16u2_TRUE}" && test -z "${HAS_atmega16u2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16u2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32u2_TRUE}" && test -z "${HAS_atmega32u2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32u2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny167_TRUE}" && test -z "${HAS_attiny167_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny167\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny1634_TRUE}" && test -z "${HAS_attiny1634_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny1634\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr4_TRUE}" && test -z "${HAS_avr4_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8_TRUE}" && test -z "${HAS_atmega8_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8515_TRUE}" && test -z "${HAS_atmega8515_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8515\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8535_TRUE}" && test -z "${HAS_atmega8535_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8535\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6285_TRUE}" && test -z "${HAS_ata6285_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6285\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6286_TRUE}" && test -z "${HAS_ata6286_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6286\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6289_TRUE}" && test -z "${HAS_ata6289_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6289\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6612c_TRUE}" && test -z "${HAS_ata6612c_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6612c\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8a_TRUE}" && test -z "${HAS_atmega8a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega48_TRUE}" && test -z "${HAS_atmega48_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega48\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega48a_TRUE}" && test -z "${HAS_atmega48a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega48a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega48pa_TRUE}" && test -z "${HAS_atmega48pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega48pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega48pb_TRUE}" && test -z "${HAS_atmega48pb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega48pb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega48p_TRUE}" && test -z "${HAS_atmega48p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega48p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega88_TRUE}" && test -z "${HAS_atmega88_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega88\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega88a_TRUE}" && test -z "${HAS_atmega88a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega88a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega88p_TRUE}" && test -z "${HAS_atmega88p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega88p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega88pa_TRUE}" && test -z "${HAS_atmega88pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega88pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega88pb_TRUE}" && test -z "${HAS_atmega88pb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega88pb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega8hva_TRUE}" && test -z "${HAS_atmega8hva_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega8hva\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm1_TRUE}" && test -z "${HAS_at90pwm1_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm2_TRUE}" && test -z "${HAS_at90pwm2_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm2b_TRUE}" && test -z "${HAS_at90pwm2b_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm2b\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm3_TRUE}" && test -z "${HAS_at90pwm3_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm3b_TRUE}" && test -z "${HAS_at90pwm3b_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm3b\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm81_TRUE}" && test -z "${HAS_at90pwm81_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm81\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr5_TRUE}" && test -z "${HAS_avr5_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90can32_TRUE}" && test -z "${HAS_at90can32_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90can32\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90can64_TRUE}" && test -z "${HAS_at90can64_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90can64\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90scr100_TRUE}" && test -z "${HAS_at90scr100_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90scr100\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb646_TRUE}" && test -z "${HAS_at90usb646_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb646\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb647_TRUE}" && test -z "${HAS_at90usb647_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb647\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm316_TRUE}" && test -z "${HAS_at90pwm316_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm316\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm216_TRUE}" && test -z "${HAS_at90pwm216_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm216\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90pwm161_TRUE}" && test -z "${HAS_at90pwm161_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90pwm161\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at94k_TRUE}" && test -z "${HAS_at94k_FALSE}"; then + as_fn_error $? "conditional \"HAS_at94k\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5702m322_TRUE}" && test -z "${HAS_ata5702m322_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5702m322\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5782_TRUE}" && test -z "${HAS_ata5782_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5782\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5790_TRUE}" && test -z "${HAS_ata5790_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5790\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5790n_TRUE}" && test -z "${HAS_ata5790n_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5790n\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5791_TRUE}" && test -z "${HAS_ata5791_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5791\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5795_TRUE}" && test -z "${HAS_ata5795_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5795\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata5831_TRUE}" && test -z "${HAS_ata5831_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata5831\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6613c_TRUE}" && test -z "${HAS_ata6613c_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6613c\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata6614q_TRUE}" && test -z "${HAS_ata6614q_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata6614q\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata8210_TRUE}" && test -z "${HAS_ata8210_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata8210\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_ata8510_TRUE}" && test -z "${HAS_ata8510_FALSE}"; then + as_fn_error $? "conditional \"HAS_ata8510\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16_TRUE}" && test -z "${HAS_atmega16_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16a_TRUE}" && test -z "${HAS_atmega16a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega161_TRUE}" && test -z "${HAS_atmega161_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega161\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega162_TRUE}" && test -z "${HAS_atmega162_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega162\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega163_TRUE}" && test -z "${HAS_atmega163_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega163\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega164a_TRUE}" && test -z "${HAS_atmega164a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega164a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega164p_TRUE}" && test -z "${HAS_atmega164p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega164p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega164pa_TRUE}" && test -z "${HAS_atmega164pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega164pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega165_TRUE}" && test -z "${HAS_atmega165_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega165\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega165a_TRUE}" && test -z "${HAS_atmega165a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega165a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega165p_TRUE}" && test -z "${HAS_atmega165p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega165p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega165pa_TRUE}" && test -z "${HAS_atmega165pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega165pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega168_TRUE}" && test -z "${HAS_atmega168_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega168\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega168a_TRUE}" && test -z "${HAS_atmega168a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega168a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega168p_TRUE}" && test -z "${HAS_atmega168p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega168p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega168pa_TRUE}" && test -z "${HAS_atmega168pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega168pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega168pb_TRUE}" && test -z "${HAS_atmega168pb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega168pb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega169_TRUE}" && test -z "${HAS_atmega169_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega169\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega169a_TRUE}" && test -z "${HAS_atmega169a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega169a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega169p_TRUE}" && test -z "${HAS_atmega169p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega169p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega169pa_TRUE}" && test -z "${HAS_atmega169pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega169pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16hva_TRUE}" && test -z "${HAS_atmega16hva_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16hva\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16hva2_TRUE}" && test -z "${HAS_atmega16hva2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16hva2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16hvb_TRUE}" && test -z "${HAS_atmega16hvb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16hvb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16hvbrevb_TRUE}" && test -z "${HAS_atmega16hvbrevb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16hvbrevb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16m1_TRUE}" && test -z "${HAS_atmega16m1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16m1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega16u4_TRUE}" && test -z "${HAS_atmega16u4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega16u4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32_TRUE}" && test -z "${HAS_atmega32_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32a_TRUE}" && test -z "${HAS_atmega32a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega323_TRUE}" && test -z "${HAS_atmega323_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega323\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega324a_TRUE}" && test -z "${HAS_atmega324a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega324a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega324p_TRUE}" && test -z "${HAS_atmega324p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega324p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega324pa_TRUE}" && test -z "${HAS_atmega324pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega324pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega325_TRUE}" && test -z "${HAS_atmega325_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega325\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega325a_TRUE}" && test -z "${HAS_atmega325a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega325a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega325p_TRUE}" && test -z "${HAS_atmega325p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega325p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega325pa_TRUE}" && test -z "${HAS_atmega325pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega325pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3250_TRUE}" && test -z "${HAS_atmega3250_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3250\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3250a_TRUE}" && test -z "${HAS_atmega3250a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3250a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3250p_TRUE}" && test -z "${HAS_atmega3250p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3250p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3250pa_TRUE}" && test -z "${HAS_atmega3250pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3250pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega328_TRUE}" && test -z "${HAS_atmega328_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega328\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega328p_TRUE}" && test -z "${HAS_atmega328p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega328p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega329_TRUE}" && test -z "${HAS_atmega329_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega329\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega329a_TRUE}" && test -z "${HAS_atmega329a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega329a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega329p_TRUE}" && test -z "${HAS_atmega329p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega329p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega329pa_TRUE}" && test -z "${HAS_atmega329pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega329pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3290_TRUE}" && test -z "${HAS_atmega3290_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3290\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3290a_TRUE}" && test -z "${HAS_atmega3290a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3290a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3290p_TRUE}" && test -z "${HAS_atmega3290p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3290p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega3290pa_TRUE}" && test -z "${HAS_atmega3290pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega3290pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32c1_TRUE}" && test -z "${HAS_atmega32c1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32c1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32hvb_TRUE}" && test -z "${HAS_atmega32hvb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32hvb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32hvbrevb_TRUE}" && test -z "${HAS_atmega32hvbrevb_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32hvbrevb\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32m1_TRUE}" && test -z "${HAS_atmega32m1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32m1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32u4_TRUE}" && test -z "${HAS_atmega32u4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32u4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega32u6_TRUE}" && test -z "${HAS_atmega32u6_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega32u6\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega406_TRUE}" && test -z "${HAS_atmega406_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega406\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega644rfr2_TRUE}" && test -z "${HAS_atmega644rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega644rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64rfr2_TRUE}" && test -z "${HAS_atmega64rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64_TRUE}" && test -z "${HAS_atmega64_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64a_TRUE}" && test -z "${HAS_atmega64a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega640_TRUE}" && test -z "${HAS_atmega640_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega640\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega644_TRUE}" && test -z "${HAS_atmega644_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega644\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega644a_TRUE}" && test -z "${HAS_atmega644a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega644a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega644p_TRUE}" && test -z "${HAS_atmega644p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega644p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega644pa_TRUE}" && test -z "${HAS_atmega644pa_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega644pa\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega645_TRUE}" && test -z "${HAS_atmega645_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega645\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega645a_TRUE}" && test -z "${HAS_atmega645a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega645a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega645p_TRUE}" && test -z "${HAS_atmega645p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega645p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6450_TRUE}" && test -z "${HAS_atmega6450_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6450\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6450a_TRUE}" && test -z "${HAS_atmega6450a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6450a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6450p_TRUE}" && test -z "${HAS_atmega6450p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6450p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega649_TRUE}" && test -z "${HAS_atmega649_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega649\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega649a_TRUE}" && test -z "${HAS_atmega649a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega649a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega649p_TRUE}" && test -z "${HAS_atmega649p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega649p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6490_TRUE}" && test -z "${HAS_atmega6490_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6490\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6490a_TRUE}" && test -z "${HAS_atmega6490a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6490a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega6490p_TRUE}" && test -z "${HAS_atmega6490p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega6490p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64c1_TRUE}" && test -z "${HAS_atmega64c1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64c1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64hve_TRUE}" && test -z "${HAS_atmega64hve_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64hve\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64hve2_TRUE}" && test -z "${HAS_atmega64hve2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64hve2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega64m1_TRUE}" && test -z "${HAS_atmega64m1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega64m1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega128rfa1_TRUE}" && test -z "${HAS_atmega128rfa1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega128rfa1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_m3000_TRUE}" && test -z "${HAS_m3000_FALSE}"; then + as_fn_error $? "conditional \"HAS_m3000\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr51_TRUE}" && test -z "${HAS_avr51_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr51\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega128_TRUE}" && test -z "${HAS_atmega128_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega128\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega128a_TRUE}" && test -z "${HAS_atmega128a_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega128a\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega1280_TRUE}" && test -z "${HAS_atmega1280_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega1280\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega1281_TRUE}" && test -z "${HAS_atmega1281_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega1281\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega1284_TRUE}" && test -z "${HAS_atmega1284_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega1284\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega1284p_TRUE}" && test -z "${HAS_atmega1284p_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega1284p\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90can128_TRUE}" && test -z "${HAS_at90can128_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90can128\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb1286_TRUE}" && test -z "${HAS_at90usb1286_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb1286\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_at90usb1287_TRUE}" && test -z "${HAS_at90usb1287_FALSE}"; then + as_fn_error $? "conditional \"HAS_at90usb1287\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega1284rfr2_TRUE}" && test -z "${HAS_atmega1284rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega1284rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega128rfr2_TRUE}" && test -z "${HAS_atmega128rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega128rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avr6_TRUE}" && test -z "${HAS_avr6_FALSE}"; then + as_fn_error $? "conditional \"HAS_avr6\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega2560_TRUE}" && test -z "${HAS_atmega2560_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega2560\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega2561_TRUE}" && test -z "${HAS_atmega2561_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega2561\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega2564rfr2_TRUE}" && test -z "${HAS_atmega2564rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega2564rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atmega256rfr2_TRUE}" && test -z "${HAS_atmega256rfr2_FALSE}"; then + as_fn_error $? "conditional \"HAS_atmega256rfr2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega2_TRUE}" && test -z "${HAS_avrxmega2_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega2\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega8e5_TRUE}" && test -z "${HAS_atxmega8e5_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega8e5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega16a4_TRUE}" && test -z "${HAS_atxmega16a4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega16a4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega16a4u_TRUE}" && test -z "${HAS_atxmega16a4u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega16a4u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega16c4_TRUE}" && test -z "${HAS_atxmega16c4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega16c4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega16d4_TRUE}" && test -z "${HAS_atxmega16d4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega16d4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32a4_TRUE}" && test -z "${HAS_atxmega32a4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32a4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32a4u_TRUE}" && test -z "${HAS_atxmega32a4u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32a4u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32c3_TRUE}" && test -z "${HAS_atxmega32c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32c4_TRUE}" && test -z "${HAS_atxmega32c4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32c4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32d3_TRUE}" && test -z "${HAS_atxmega32d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32d4_TRUE}" && test -z "${HAS_atxmega32d4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32d4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega16e5_TRUE}" && test -z "${HAS_atxmega16e5_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega16e5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega32e5_TRUE}" && test -z "${HAS_atxmega32e5_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega32e5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega3_TRUE}" && test -z "${HAS_avrxmega3_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega4_TRUE}" && test -z "${HAS_avrxmega4_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64a3_TRUE}" && test -z "${HAS_atxmega64a3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64a3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64a3u_TRUE}" && test -z "${HAS_atxmega64a3u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64a3u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64a4u_TRUE}" && test -z "${HAS_atxmega64a4u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64a4u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64b1_TRUE}" && test -z "${HAS_atxmega64b1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64b1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64b3_TRUE}" && test -z "${HAS_atxmega64b3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64b3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64c3_TRUE}" && test -z "${HAS_atxmega64c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64d3_TRUE}" && test -z "${HAS_atxmega64d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64d4_TRUE}" && test -z "${HAS_atxmega64d4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64d4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega5_TRUE}" && test -z "${HAS_avrxmega5_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64a1_TRUE}" && test -z "${HAS_atxmega64a1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64a1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega64a1u_TRUE}" && test -z "${HAS_atxmega64a1u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega64a1u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega6_TRUE}" && test -z "${HAS_avrxmega6_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega6\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128a3_TRUE}" && test -z "${HAS_atxmega128a3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128a3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128a3u_TRUE}" && test -z "${HAS_atxmega128a3u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128a3u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128b1_TRUE}" && test -z "${HAS_atxmega128b1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128b1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128b3_TRUE}" && test -z "${HAS_atxmega128b3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128b3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128c3_TRUE}" && test -z "${HAS_atxmega128c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128d3_TRUE}" && test -z "${HAS_atxmega128d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128d4_TRUE}" && test -z "${HAS_atxmega128d4_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128d4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega192a3_TRUE}" && test -z "${HAS_atxmega192a3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega192a3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega192a3u_TRUE}" && test -z "${HAS_atxmega192a3u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega192a3u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega192c3_TRUE}" && test -z "${HAS_atxmega192c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega192c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega192d3_TRUE}" && test -z "${HAS_atxmega192d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega192d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256a3_TRUE}" && test -z "${HAS_atxmega256a3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256a3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256a3u_TRUE}" && test -z "${HAS_atxmega256a3u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256a3u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256a3b_TRUE}" && test -z "${HAS_atxmega256a3b_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256a3b\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256a3bu_TRUE}" && test -z "${HAS_atxmega256a3bu_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256a3bu\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256c3_TRUE}" && test -z "${HAS_atxmega256c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega256d3_TRUE}" && test -z "${HAS_atxmega256d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega256d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega384c3_TRUE}" && test -z "${HAS_atxmega384c3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega384c3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega384d3_TRUE}" && test -z "${HAS_atxmega384d3_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega384d3\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrxmega7_TRUE}" && test -z "${HAS_avrxmega7_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrxmega7\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128a1_TRUE}" && test -z "${HAS_atxmega128a1_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128a1\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128a1u_TRUE}" && test -z "${HAS_atxmega128a1u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128a1u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_atxmega128a4u_TRUE}" && test -z "${HAS_atxmega128a4u_FALSE}"; then + as_fn_error $? "conditional \"HAS_atxmega128a4u\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_avrtiny_TRUE}" && test -z "${HAS_avrtiny_FALSE}"; then + as_fn_error $? "conditional \"HAS_avrtiny\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny4_TRUE}" && test -z "${HAS_attiny4_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny4\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny5_TRUE}" && test -z "${HAS_attiny5_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny5\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny9_TRUE}" && test -z "${HAS_attiny9_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny9\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny10_TRUE}" && test -z "${HAS_attiny10_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny10\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny20_TRUE}" && test -z "${HAS_attiny20_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny20\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi +if test -z "${HAS_attiny40_TRUE}" && test -z "${HAS_attiny40_FALSE}"; then + as_fn_error $? "conditional \"HAS_attiny40\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi + +: "${CONFIG_STATUS=./config.status}" +ac_write_fail=0 +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files $CONFIG_STATUS" +{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} +as_write_fail=0 +cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 +#! $SHELL +# Generated by $as_me. +# Run this file to recreate the current configuration. +# Compiler output produced by configure, useful for debugging +# configure, is in config.log if it exists. + +debug=false +ac_cs_recheck=false +ac_cs_silent=false + +SHELL=\${CONFIG_SHELL-$SHELL} +export SHELL +_ASEOF +cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 +## -------------------- ## +## M4sh Initialization. ## +## -------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in #( + *posix*) : + set -o posix ;; #( + *) : + ;; +esac +fi + + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +# Prefer a ksh shell builtin over an external printf program on Solaris, +# but without wasting forks for bash or zsh. +if test -z "$BASH_VERSION$ZSH_VERSION" \ + && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='print -r --' + as_echo_n='print -rn --' +elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in #( + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + + +# IFS +# We need space, tab and new line, in precisely that order. Quoting is +# there to prevent editors from complaining about space-tab. +# (If _AS_PATH_WALK were called with IFS unset, it would disable word +# splitting by setting IFS to empty value.) +IFS=" "" $as_nl" + +# Find who we are. Look in the path if we contain no directory separator. +as_myself= +case $0 in #(( + *[\\/]* ) as_myself=$0 ;; + *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break + done +IFS=$as_save_IFS + + ;; +esac +# We did not find ourselves, most probably we were run as `sh COMMAND' +# in which case we are not to be found in the path. +if test "x$as_myself" = x; then + as_myself=$0 +fi +if test ! -f "$as_myself"; then + $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 + exit 1 +fi + +# Unset variables that we do not need and which cause bugs (e.g. in +# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" +# suppresses any "Segmentation fault" message there. '((' could +# trigger a bug in pdksh 5.2.14. +for as_var in BASH_ENV ENV MAIL MAILPATH +do eval test x\${$as_var+set} = xset \ + && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : +done +PS1='$ ' +PS2='> ' +PS4='+ ' + +# NLS nuisances. +LC_ALL=C +export LC_ALL +LANGUAGE=C +export LANGUAGE + +# CDPATH. +(unset CDPATH) >/dev/null 2>&1 && unset CDPATH + + +# as_fn_error STATUS ERROR [LINENO LOG_FD] +# ---------------------------------------- +# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are +# provided, also output the error to LOG_FD, referencing LINENO. Then exit the +# script with STATUS, using 1 if that was 0. +as_fn_error () +{ + as_status=$1; test $as_status -eq 0 && as_status=1 + if test "$4"; then + as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack + $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 + fi + $as_echo "$as_me: error: $2" >&2 + as_fn_exit $as_status +} # as_fn_error + + +# as_fn_set_status STATUS +# ----------------------- +# Set $? to STATUS, without forking. +as_fn_set_status () +{ + return $1 +} # as_fn_set_status + +# as_fn_exit STATUS +# ----------------- +# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. +as_fn_exit () +{ + set +e + as_fn_set_status $1 + exit $1 +} # as_fn_exit + +# as_fn_unset VAR +# --------------- +# Portably unset VAR. +as_fn_unset () +{ + { eval $1=; unset $1;} +} +as_unset=as_fn_unset +# as_fn_append VAR VALUE +# ---------------------- +# Append the text in VALUE to the end of the definition contained in VAR. Take +# advantage of any shell optimizations that allow amortized linear growth over +# repeated appends, instead of the typical quadratic growth present in naive +# implementations. +if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : + eval 'as_fn_append () + { + eval $1+=\$2 + }' +else + as_fn_append () + { + eval $1=\$$1\$2 + } +fi # as_fn_append + +# as_fn_arith ARG... +# ------------------ +# Perform arithmetic evaluation on the ARGs, and store the result in the +# global $as_val. Take advantage of shells that can avoid forks. The arguments +# must be portable across $(()) and expr. +if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : + eval 'as_fn_arith () + { + as_val=$(( $* )) + }' +else + as_fn_arith () + { + as_val=`expr "$@" || test $? -eq 1` + } +fi # as_fn_arith + + +if expr a : '\(a\)' >/dev/null 2>&1 && + test "X`expr 00001 : '.*\(...\)'`" = X001; then + as_expr=expr +else + as_expr=false +fi + +if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then + as_basename=basename +else + as_basename=false +fi + +if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then + as_dirname=dirname +else + as_dirname=false +fi + +as_me=`$as_basename -- "$0" || +$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X/"$0" | + sed '/^.*\/\([^/][^/]*\)\/*$/{ + s//\1/ + q + } + /^X\/\(\/\/\)$/{ + s//\1/ + q + } + /^X\/\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +ECHO_C= ECHO_N= ECHO_T= +case `echo -n x` in #((((( +-n*) + case `echo 'xy\c'` in + *c*) ECHO_T=' ';; # ECHO_T is single tab character. + xy) ECHO_C='\c';; + *) echo `echo ksh88 bug on AIX 6.1` > /dev/null + ECHO_T=' ';; + esac;; +*) + ECHO_N='-n';; +esac + +rm -f conf$$ conf$$.exe conf$$.file +if test -d conf$$.dir; then + rm -f conf$$.dir/conf$$.file +else + rm -f conf$$.dir + mkdir conf$$.dir 2>/dev/null +fi +if (echo >conf$$.file) 2>/dev/null; then + if ln -s conf$$.file conf$$ 2>/dev/null; then + as_ln_s='ln -s' + # ... but there are two gotchas: + # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. + # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. + # In both cases, we have to default to `cp -pR'. + ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || + as_ln_s='cp -pR' + elif ln conf$$.file conf$$ 2>/dev/null; then + as_ln_s=ln + else + as_ln_s='cp -pR' + fi +else + as_ln_s='cp -pR' +fi +rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file +rmdir conf$$.dir 2>/dev/null + + +# as_fn_mkdir_p +# ------------- +# Create "$as_dir" as a directory, including parents if necessary. +as_fn_mkdir_p () +{ + + case $as_dir in #( + -*) as_dir=./$as_dir;; + esac + test -d "$as_dir" || eval $as_mkdir_p || { + as_dirs= + while :; do + case $as_dir in #( + *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( + *) as_qdir=$as_dir;; + esac + as_dirs="'$as_qdir' $as_dirs" + as_dir=`$as_dirname -- "$as_dir" || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || +$as_echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ + s//\1/ + q + } + /^X\(\/\/\)[^/].*/{ + s//\1/ + q + } + /^X\(\/\/\)$/{ + s//\1/ + q + } + /^X\(\/\).*/{ + s//\1/ + q + } + s/.*/./; q'` + test -d "$as_dir" && break + done + test -z "$as_dirs" || eval "mkdir $as_dirs" + } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" + + +} # as_fn_mkdir_p +if mkdir -p . 2>/dev/null; then + as_mkdir_p='mkdir -p "$as_dir"' +else + test -d ./-p && rmdir ./-p + as_mkdir_p=false +fi + + +# as_fn_executable_p FILE +# ----------------------- +# Test if FILE is an executable regular file. +as_fn_executable_p () +{ + test -f "$1" && test -x "$1" +} # as_fn_executable_p +as_test_x='test -x' +as_executable_p=as_fn_executable_p + +# Sed expression to map a string onto a valid CPP name. +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" + +# Sed expression to map a string onto a valid variable name. +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" + + +exec 6>&1 +## ----------------------------------- ## +## Main body of $CONFIG_STATUS script. ## +## ----------------------------------- ## +_ASEOF +test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# Save the log message, to keep $0 and so on meaningful, and to +# report actual input values of CONFIG_FILES etc. instead of their +# values after options handling. +ac_log=" +This file was extended by avr-libc $as_me 2.0.0, which was +generated by GNU Autoconf 2.69. Invocation command line was + + CONFIG_FILES = $CONFIG_FILES + CONFIG_HEADERS = $CONFIG_HEADERS + CONFIG_LINKS = $CONFIG_LINKS + CONFIG_COMMANDS = $CONFIG_COMMANDS + $ $0 $@ + +on `(hostname || uname -n) 2>/dev/null | sed 1q` +" + +_ACEOF + +case $ac_config_files in *" +"*) set x $ac_config_files; shift; ac_config_files=$*;; +esac + +case $ac_config_headers in *" +"*) set x $ac_config_headers; shift; ac_config_headers=$*;; +esac + + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# Files that config.status was made for. +config_files="$ac_config_files" +config_headers="$ac_config_headers" +config_commands="$ac_config_commands" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +ac_cs_usage="\ +\`$as_me' instantiates files and other configuration actions +from templates according to the current configuration. Unless the files +and actions are specified as TAGs, all are instantiated by default. + +Usage: $0 [OPTION]... [TAG]... + + -h, --help print this help, then exit + -V, --version print version number and configuration settings, then exit + --config print configuration, then exit + -q, --quiet, --silent + do not print progress messages + -d, --debug don't remove temporary files + --recheck update $as_me by reconfiguring in the same conditions + --file=FILE[:TEMPLATE] + instantiate the configuration file FILE + --header=FILE[:TEMPLATE] + instantiate the configuration header FILE + +Configuration files: +$config_files + +Configuration headers: +$config_headers + +Configuration commands: +$config_commands + +Report bugs to ." + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" +ac_cs_version="\\ +avr-libc config.status 2.0.0 +configured by $0, generated by GNU Autoconf 2.69, + with options \\"\$ac_cs_config\\" + +Copyright (C) 2012 Free Software Foundation, Inc. +This config.status script is free software; the Free Software Foundation +gives unlimited permission to copy, distribute and modify it." + +ac_pwd='$ac_pwd' +srcdir='$srcdir' +INSTALL='$INSTALL' +MKDIR_P='$MKDIR_P' +AWK='$AWK' +test -n "\$AWK" || AWK=awk +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +# The default lists apply if the user does not specify any file. +ac_need_defaults=: +while test $# != 0 +do + case $1 in + --*=?*) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` + ac_shift=: + ;; + --*=) + ac_option=`expr "X$1" : 'X\([^=]*\)='` + ac_optarg= + ac_shift=: + ;; + *) + ac_option=$1 + ac_optarg=$2 + ac_shift=shift + ;; + esac + + case $ac_option in + # Handling of the options. + -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) + ac_cs_recheck=: ;; + --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) + $as_echo "$ac_cs_version"; exit ;; + --config | --confi | --conf | --con | --co | --c ) + $as_echo "$ac_cs_config"; exit ;; + --debug | --debu | --deb | --de | --d | -d ) + debug=: ;; + --file | --fil | --fi | --f ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + '') as_fn_error $? "missing file argument" ;; + esac + as_fn_append CONFIG_FILES " '$ac_optarg'" + ac_need_defaults=false;; + --header | --heade | --head | --hea ) + $ac_shift + case $ac_optarg in + *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; + esac + as_fn_append CONFIG_HEADERS " '$ac_optarg'" + ac_need_defaults=false;; + --he | --h) + # Conflict between --help and --header + as_fn_error $? "ambiguous option: \`$1' +Try \`$0 --help' for more information.";; + --help | --hel | -h ) + $as_echo "$ac_cs_usage"; exit ;; + -q | -quiet | --quiet | --quie | --qui | --qu | --q \ + | -silent | --silent | --silen | --sile | --sil | --si | --s) + ac_cs_silent=: ;; + + # This is an error. + -*) as_fn_error $? "unrecognized option: \`$1' +Try \`$0 --help' for more information." ;; + + *) as_fn_append ac_config_targets " $1" + ac_need_defaults=false ;; + + esac + shift +done + +ac_configure_extra_args= + +if $ac_cs_silent; then + exec 6>/dev/null + ac_configure_extra_args="$ac_configure_extra_args --silent" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +if \$ac_cs_recheck; then + set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion + shift + \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 + CONFIG_SHELL='$SHELL' + export CONFIG_SHELL + exec "\$@" +fi + +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +exec 5>>config.log +{ + echo + sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX +## Running $as_me. ## +_ASBOX + $as_echo "$ac_log" +} >&5 + +_ACEOF +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +# +# INIT-COMMANDS +# +AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir" + +_ACEOF + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + +# Handling of arguments. +for ac_config_target in $ac_config_targets +do + case $ac_config_target in + "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;; + "depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;; + "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; + "avr-libc.spec") CONFIG_FILES="$CONFIG_FILES avr-libc.spec" ;; + "avr/Makefile") CONFIG_FILES="$CONFIG_FILES avr/Makefile" ;; + "avr/lib/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/Makefile" ;; + "common/Makefile") CONFIG_FILES="$CONFIG_FILES common/Makefile" ;; + "crt1/Makefile") CONFIG_FILES="$CONFIG_FILES crt1/Makefile" ;; + "crt1/iosym/Makefile") CONFIG_FILES="$CONFIG_FILES crt1/iosym/Makefile" ;; + "doc/Makefile") CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;; + "doc/api/Makefile") CONFIG_FILES="$CONFIG_FILES doc/api/Makefile" ;; + "doc/examples/Makefile") CONFIG_FILES="$CONFIG_FILES doc/examples/Makefile" ;; + "include/Makefile") CONFIG_FILES="$CONFIG_FILES include/Makefile" ;; + "include/avr/Makefile") CONFIG_FILES="$CONFIG_FILES include/avr/Makefile" ;; + "include/avr/builtins.h") CONFIG_FILES="$CONFIG_FILES include/avr/builtins.h" ;; + "include/compat/Makefile") CONFIG_FILES="$CONFIG_FILES include/compat/Makefile" ;; + "include/util/Makefile") CONFIG_FILES="$CONFIG_FILES include/util/Makefile" ;; + "include/util/delay.h") CONFIG_FILES="$CONFIG_FILES include/util/delay.h" ;; + "include/sys/Makefile") CONFIG_FILES="$CONFIG_FILES include/sys/Makefile" ;; + "libc/Makefile") CONFIG_FILES="$CONFIG_FILES libc/Makefile" ;; + "libc/misc/Makefile") CONFIG_FILES="$CONFIG_FILES libc/misc/Makefile" ;; + "libc/pmstring/Makefile") CONFIG_FILES="$CONFIG_FILES libc/pmstring/Makefile" ;; + "libc/stdio/Makefile") CONFIG_FILES="$CONFIG_FILES libc/stdio/Makefile" ;; + "libc/stdlib/Makefile") CONFIG_FILES="$CONFIG_FILES libc/stdlib/Makefile" ;; + "libc/string/Makefile") CONFIG_FILES="$CONFIG_FILES libc/string/Makefile" ;; + "libc/time/Makefile") CONFIG_FILES="$CONFIG_FILES libc/time/Makefile" ;; + "libm/Makefile") CONFIG_FILES="$CONFIG_FILES libm/Makefile" ;; + "libm/fplib/Makefile") CONFIG_FILES="$CONFIG_FILES libm/fplib/Makefile" ;; + "scripts/Makefile") CONFIG_FILES="$CONFIG_FILES scripts/Makefile" ;; + "devtools/Makefile") CONFIG_FILES="$CONFIG_FILES devtools/Makefile" ;; + "avr/lib/avr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/Makefile" ;; + "avr/lib/avr2/at90s1200/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s1200/Makefile" ;; + "avr/lib/avr2/at90s4414/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s4414/Makefile" ;; + "avr/lib/avr2/at90s4434/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s4434/Makefile" ;; + "avr/lib/avr2/at90s8515/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s8515/Makefile" ;; + "avr/lib/avr2/at90c8534/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90c8534/Makefile" ;; + "avr/lib/avr2/at90s8535/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/at90s8535/Makefile" ;; + "avr/lib/avr2/attiny11/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny11/Makefile" ;; + "avr/lib/avr2/attiny12/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny12/Makefile" ;; + "avr/lib/avr2/attiny15/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny15/Makefile" ;; + "avr/lib/avr2/attiny28/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/attiny28/Makefile" ;; + "avr/lib/avr2/tiny-stack/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/Makefile" ;; + "avr/lib/avr2/tiny-stack/at90s2313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2313/Makefile" ;; + "avr/lib/avr2/tiny-stack/at90s2323/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2323/Makefile" ;; + "avr/lib/avr2/tiny-stack/at90s2333/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2333/Makefile" ;; + "avr/lib/avr2/tiny-stack/at90s2343/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s2343/Makefile" ;; + "avr/lib/avr2/tiny-stack/attiny22/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/attiny22/Makefile" ;; + "avr/lib/avr2/tiny-stack/attiny26/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/attiny26/Makefile" ;; + "avr/lib/avr2/tiny-stack/at90s4433/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr2/tiny-stack/at90s4433/Makefile" ;; + "avr/lib/avr25/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/Makefile" ;; + "avr/lib/avr25/at86rf401/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/at86rf401/Makefile" ;; + "avr/lib/avr25/ata5272/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/ata5272/Makefile" ;; + "avr/lib/avr25/ata6616c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/ata6616c/Makefile" ;; + "avr/lib/avr25/attiny4313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny4313/Makefile" ;; + "avr/lib/avr25/attiny43u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny43u/Makefile" ;; + "avr/lib/avr25/attiny44/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44/Makefile" ;; + "avr/lib/avr25/attiny44a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny44a/Makefile" ;; + "avr/lib/avr25/attiny441/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny441/Makefile" ;; + "avr/lib/avr25/attiny45/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny45/Makefile" ;; + "avr/lib/avr25/attiny461/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461/Makefile" ;; + "avr/lib/avr25/attiny461a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny461a/Makefile" ;; + "avr/lib/avr25/attiny48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny48/Makefile" ;; + "avr/lib/avr25/attiny828/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny828/Makefile" ;; + "avr/lib/avr25/attiny84/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84/Makefile" ;; + "avr/lib/avr25/attiny84a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny84a/Makefile" ;; + "avr/lib/avr25/attiny841/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny841/Makefile" ;; + "avr/lib/avr25/attiny85/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny85/Makefile" ;; + "avr/lib/avr25/attiny861/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861/Makefile" ;; + "avr/lib/avr25/attiny861a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny861a/Makefile" ;; + "avr/lib/avr25/attiny87/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny87/Makefile" ;; + "avr/lib/avr25/attiny88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/attiny88/Makefile" ;; + "avr/lib/avr25/tiny-stack/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny13/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny13/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny13a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny13a/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny2313/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny2313/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny2313a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny2313a/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny24/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny24/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny24a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny24a/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny25/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny25/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny261/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny261/Makefile" ;; + "avr/lib/avr25/tiny-stack/attiny261a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr25/tiny-stack/attiny261a/Makefile" ;; + "avr/lib/avr3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/Makefile" ;; + "avr/lib/avr3/at43usb355/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at43usb355/Makefile" ;; + "avr/lib/avr3/at76c711/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr3/at76c711/Makefile" ;; + "avr/lib/avr31/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/Makefile" ;; + "avr/lib/avr31/atmega103/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/atmega103/Makefile" ;; + "avr/lib/avr31/at43usb320/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr31/at43usb320/Makefile" ;; + "avr/lib/avr35/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/Makefile" ;; + "avr/lib/avr35/at90usb82/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb82/Makefile" ;; + "avr/lib/avr35/at90usb162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/at90usb162/Makefile" ;; + "avr/lib/avr35/ata5505/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata5505/Makefile" ;; + "avr/lib/avr35/ata6617c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata6617c/Makefile" ;; + "avr/lib/avr35/ata664251/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/ata664251/Makefile" ;; + "avr/lib/avr35/atmega8u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega8u2/Makefile" ;; + "avr/lib/avr35/atmega16u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega16u2/Makefile" ;; + "avr/lib/avr35/atmega32u2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/atmega32u2/Makefile" ;; + "avr/lib/avr35/attiny167/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/attiny167/Makefile" ;; + "avr/lib/avr35/attiny1634/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr35/attiny1634/Makefile" ;; + "avr/lib/avr4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/Makefile" ;; + "avr/lib/avr4/ata6285/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6285/Makefile" ;; + "avr/lib/avr4/ata6286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6286/Makefile" ;; + "avr/lib/avr4/ata6289/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6289/Makefile" ;; + "avr/lib/avr4/ata6612c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/ata6612c/Makefile" ;; + "avr/lib/avr4/atmega48/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48/Makefile" ;; + "avr/lib/avr4/atmega48a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48a/Makefile" ;; + "avr/lib/avr4/atmega48pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48pa/Makefile" ;; + "avr/lib/avr4/atmega48pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48pb/Makefile" ;; + "avr/lib/avr4/atmega48p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega48p/Makefile" ;; + "avr/lib/avr4/atmega8/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8/Makefile" ;; + "avr/lib/avr4/atmega8a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8a/Makefile" ;; + "avr/lib/avr4/atmega88/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88/Makefile" ;; + "avr/lib/avr4/atmega88a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88a/Makefile" ;; + "avr/lib/avr4/atmega88p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88p/Makefile" ;; + "avr/lib/avr4/atmega88pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88pa/Makefile" ;; + "avr/lib/avr4/atmega88pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega88pb/Makefile" ;; + "avr/lib/avr4/atmega8515/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8515/Makefile" ;; + "avr/lib/avr4/atmega8535/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8535/Makefile" ;; + "avr/lib/avr4/atmega8hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/atmega8hva/Makefile" ;; + "avr/lib/avr4/at90pwm1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm1/Makefile" ;; + "avr/lib/avr4/at90pwm2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2/Makefile" ;; + "avr/lib/avr4/at90pwm2b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm2b/Makefile" ;; + "avr/lib/avr4/at90pwm3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3/Makefile" ;; + "avr/lib/avr4/at90pwm3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm3b/Makefile" ;; + "avr/lib/avr4/at90pwm81/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr4/at90pwm81/Makefile" ;; + "avr/lib/avr5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/Makefile" ;; + "avr/lib/avr5/at90can32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can32/Makefile" ;; + "avr/lib/avr5/at90can64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90can64/Makefile" ;; + "avr/lib/avr5/at90pwm216/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm216/Makefile" ;; + "avr/lib/avr5/at90pwm316/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm316/Makefile" ;; + "avr/lib/avr5/at90pwm161/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90pwm161/Makefile" ;; + "avr/lib/avr5/at90scr100/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90scr100/Makefile" ;; + "avr/lib/avr5/at90usb646/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb646/Makefile" ;; + "avr/lib/avr5/at90usb647/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at90usb647/Makefile" ;; + "avr/lib/avr5/at94k/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/at94k/Makefile" ;; + "avr/lib/avr5/ata5702m322/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5702m322/Makefile" ;; + "avr/lib/avr5/ata5782/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5782/Makefile" ;; + "avr/lib/avr5/ata5790/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5790/Makefile" ;; + "avr/lib/avr5/ata5790n/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5790n/Makefile" ;; + "avr/lib/avr5/ata5791/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5791/Makefile" ;; + "avr/lib/avr5/ata5795/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5795/Makefile" ;; + "avr/lib/avr5/ata5831/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata5831/Makefile" ;; + "avr/lib/avr5/ata6613c/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata6613c/Makefile" ;; + "avr/lib/avr5/ata6614q/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata6614q/Makefile" ;; + "avr/lib/avr5/ata8210/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata8210/Makefile" ;; + "avr/lib/avr5/ata8510/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/ata8510/Makefile" ;; + "avr/lib/avr5/atmega16/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16/Makefile" ;; + "avr/lib/avr5/atmega16a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16a/Makefile" ;; + "avr/lib/avr5/atmega161/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega161/Makefile" ;; + "avr/lib/avr5/atmega162/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega162/Makefile" ;; + "avr/lib/avr5/atmega163/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega163/Makefile" ;; + "avr/lib/avr5/atmega164a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164a/Makefile" ;; + "avr/lib/avr5/atmega164p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164p/Makefile" ;; + "avr/lib/avr5/atmega164pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega164pa/Makefile" ;; + "avr/lib/avr5/atmega165/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165/Makefile" ;; + "avr/lib/avr5/atmega165a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165a/Makefile" ;; + "avr/lib/avr5/atmega165p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165p/Makefile" ;; + "avr/lib/avr5/atmega165pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega165pa/Makefile" ;; + "avr/lib/avr5/atmega168/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168/Makefile" ;; + "avr/lib/avr5/atmega168a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168a/Makefile" ;; + "avr/lib/avr5/atmega168p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168p/Makefile" ;; + "avr/lib/avr5/atmega168pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168pa/Makefile" ;; + "avr/lib/avr5/atmega168pb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega168pb/Makefile" ;; + "avr/lib/avr5/atmega169/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169/Makefile" ;; + "avr/lib/avr5/atmega169a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169a/Makefile" ;; + "avr/lib/avr5/atmega169p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169p/Makefile" ;; + "avr/lib/avr5/atmega169pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega169pa/Makefile" ;; + "avr/lib/avr5/atmega16hva/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva/Makefile" ;; + "avr/lib/avr5/atmega16hva2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hva2/Makefile" ;; + "avr/lib/avr5/atmega16hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvb/Makefile" ;; + "avr/lib/avr5/atmega16hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16hvbrevb/Makefile" ;; + "avr/lib/avr5/atmega16m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16m1/Makefile" ;; + "avr/lib/avr5/atmega16u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega16u4/Makefile" ;; + "avr/lib/avr5/atmega32/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32/Makefile" ;; + "avr/lib/avr5/atmega32a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32a/Makefile" ;; + "avr/lib/avr5/atmega323/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega323/Makefile" ;; + "avr/lib/avr5/atmega324a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324a/Makefile" ;; + "avr/lib/avr5/atmega324p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324p/Makefile" ;; + "avr/lib/avr5/atmega324pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega324pa/Makefile" ;; + "avr/lib/avr5/atmega325/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325/Makefile" ;; + "avr/lib/avr5/atmega325a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325a/Makefile" ;; + "avr/lib/avr5/atmega325p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325p/Makefile" ;; + "avr/lib/avr5/atmega325pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega325pa/Makefile" ;; + "avr/lib/avr5/atmega3250/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250/Makefile" ;; + "avr/lib/avr5/atmega3250a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250a/Makefile" ;; + "avr/lib/avr5/atmega3250p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250p/Makefile" ;; + "avr/lib/avr5/atmega3250pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3250pa/Makefile" ;; + "avr/lib/avr5/atmega328/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328/Makefile" ;; + "avr/lib/avr5/atmega328p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega328p/Makefile" ;; + "avr/lib/avr5/atmega329/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329/Makefile" ;; + "avr/lib/avr5/atmega329a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329a/Makefile" ;; + "avr/lib/avr5/atmega329p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329p/Makefile" ;; + "avr/lib/avr5/atmega329pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega329pa/Makefile" ;; + "avr/lib/avr5/atmega3290/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290/Makefile" ;; + "avr/lib/avr5/atmega3290a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290a/Makefile" ;; + "avr/lib/avr5/atmega3290p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290p/Makefile" ;; + "avr/lib/avr5/atmega3290pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega3290pa/Makefile" ;; + "avr/lib/avr5/atmega32c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32c1/Makefile" ;; + "avr/lib/avr5/atmega32hvb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvb/Makefile" ;; + "avr/lib/avr5/atmega32hvbrevb/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32hvbrevb/Makefile" ;; + "avr/lib/avr5/atmega32m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32m1/Makefile" ;; + "avr/lib/avr5/atmega32u4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u4/Makefile" ;; + "avr/lib/avr5/atmega32u6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega32u6/Makefile" ;; + "avr/lib/avr5/atmega406/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega406/Makefile" ;; + "avr/lib/avr5/atmega64rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64rfr2/Makefile" ;; + "avr/lib/avr5/atmega644rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644rfr2/Makefile" ;; + "avr/lib/avr5/atmega64/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64/Makefile" ;; + "avr/lib/avr5/atmega64a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64a/Makefile" ;; + "avr/lib/avr5/atmega640/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega640/Makefile" ;; + "avr/lib/avr5/atmega644/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644/Makefile" ;; + "avr/lib/avr5/atmega644a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644a/Makefile" ;; + "avr/lib/avr5/atmega644p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644p/Makefile" ;; + "avr/lib/avr5/atmega644pa/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega644pa/Makefile" ;; + "avr/lib/avr5/atmega645/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645/Makefile" ;; + "avr/lib/avr5/atmega645a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645a/Makefile" ;; + "avr/lib/avr5/atmega645p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega645p/Makefile" ;; + "avr/lib/avr5/atmega6450/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450/Makefile" ;; + "avr/lib/avr5/atmega6450a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450a/Makefile" ;; + "avr/lib/avr5/atmega6450p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6450p/Makefile" ;; + "avr/lib/avr5/atmega649/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649/Makefile" ;; + "avr/lib/avr5/atmega649a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649a/Makefile" ;; + "avr/lib/avr5/atmega649p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega649p/Makefile" ;; + "avr/lib/avr5/atmega6490/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490/Makefile" ;; + "avr/lib/avr5/atmega6490a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490a/Makefile" ;; + "avr/lib/avr5/atmega6490p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega6490p/Makefile" ;; + "avr/lib/avr5/atmega64c1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64c1/Makefile" ;; + "avr/lib/avr5/atmega64hve/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64hve/Makefile" ;; + "avr/lib/avr5/atmega64hve2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64hve2/Makefile" ;; + "avr/lib/avr5/atmega64m1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/atmega64m1/Makefile" ;; + "avr/lib/avr5/m3000/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr5/m3000/Makefile" ;; + "avr/lib/avr51/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/Makefile" ;; + "avr/lib/avr51/atmega128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128/Makefile" ;; + "avr/lib/avr51/atmega128a/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128a/Makefile" ;; + "avr/lib/avr51/atmega1280/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1280/Makefile" ;; + "avr/lib/avr51/atmega1281/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1281/Makefile" ;; + "avr/lib/avr51/atmega1284/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284/Makefile" ;; + "avr/lib/avr51/atmega1284p/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284p/Makefile" ;; + "avr/lib/avr51/atmega128rfa1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128rfa1/Makefile" ;; + "avr/lib/avr51/atmega128rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega128rfr2/Makefile" ;; + "avr/lib/avr51/atmega1284rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/atmega1284rfr2/Makefile" ;; + "avr/lib/avr51/at90can128/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90can128/Makefile" ;; + "avr/lib/avr51/at90usb1286/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1286/Makefile" ;; + "avr/lib/avr51/at90usb1287/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr51/at90usb1287/Makefile" ;; + "avr/lib/avr6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/Makefile" ;; + "avr/lib/avr6/atmega2560/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2560/Makefile" ;; + "avr/lib/avr6/atmega2561/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2561/Makefile" ;; + "avr/lib/avr6/atmega256rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega256rfr2/Makefile" ;; + "avr/lib/avr6/atmega2564rfr2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avr6/atmega2564rfr2/Makefile" ;; + "avr/lib/avrxmega2/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/Makefile" ;; + "avr/lib/avrxmega2/atxmega8e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega8e5/Makefile" ;; + "avr/lib/avrxmega2/atxmega16a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16a4/Makefile" ;; + "avr/lib/avrxmega2/atxmega16a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16a4u/Makefile" ;; + "avr/lib/avrxmega2/atxmega16c4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16c4/Makefile" ;; + "avr/lib/avrxmega2/atxmega16d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16d4/Makefile" ;; + "avr/lib/avrxmega2/atxmega16e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega16e5/Makefile" ;; + "avr/lib/avrxmega2/atxmega32a4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32a4/Makefile" ;; + "avr/lib/avrxmega2/atxmega32a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32a4u/Makefile" ;; + "avr/lib/avrxmega2/atxmega32c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32c3/Makefile" ;; + "avr/lib/avrxmega2/atxmega32c4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32c4/Makefile" ;; + "avr/lib/avrxmega2/atxmega32d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32d3/Makefile" ;; + "avr/lib/avrxmega2/atxmega32d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32d4/Makefile" ;; + "avr/lib/avrxmega2/atxmega32e5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega2/atxmega32e5/Makefile" ;; + "avr/lib/avrxmega3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega3/Makefile" ;; + "avr/lib/avrxmega3/short-calls/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega3/short-calls/Makefile" ;; + "avr/lib/avrxmega4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/Makefile" ;; + "avr/lib/avrxmega4/atxmega64a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a3/Makefile" ;; + "avr/lib/avrxmega4/atxmega64a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a3u/Makefile" ;; + "avr/lib/avrxmega4/atxmega64a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64a4u/Makefile" ;; + "avr/lib/avrxmega4/atxmega64b1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64b1/Makefile" ;; + "avr/lib/avrxmega4/atxmega64b3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64b3/Makefile" ;; + "avr/lib/avrxmega4/atxmega64c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64c3/Makefile" ;; + "avr/lib/avrxmega4/atxmega64d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64d3/Makefile" ;; + "avr/lib/avrxmega4/atxmega64d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega4/atxmega64d4/Makefile" ;; + "avr/lib/avrxmega5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/Makefile" ;; + "avr/lib/avrxmega5/atxmega64a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1/Makefile" ;; + "avr/lib/avrxmega5/atxmega64a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega5/atxmega64a1u/Makefile" ;; + "avr/lib/avrxmega6/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/Makefile" ;; + "avr/lib/avrxmega6/atxmega128a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128a3/Makefile" ;; + "avr/lib/avrxmega6/atxmega128a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128a3u/Makefile" ;; + "avr/lib/avrxmega6/atxmega128b1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128b1/Makefile" ;; + "avr/lib/avrxmega6/atxmega128b3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128b3/Makefile" ;; + "avr/lib/avrxmega6/atxmega128c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128c3/Makefile" ;; + "avr/lib/avrxmega6/atxmega128d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128d3/Makefile" ;; + "avr/lib/avrxmega6/atxmega128d4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega128d4/Makefile" ;; + "avr/lib/avrxmega6/atxmega192a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192a3/Makefile" ;; + "avr/lib/avrxmega6/atxmega192a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192a3u/Makefile" ;; + "avr/lib/avrxmega6/atxmega192c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192c3/Makefile" ;; + "avr/lib/avrxmega6/atxmega192d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega192d3/Makefile" ;; + "avr/lib/avrxmega6/atxmega256a3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3/Makefile" ;; + "avr/lib/avrxmega6/atxmega256a3u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3u/Makefile" ;; + "avr/lib/avrxmega6/atxmega256a3b/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3b/Makefile" ;; + "avr/lib/avrxmega6/atxmega256a3bu/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256a3bu/Makefile" ;; + "avr/lib/avrxmega6/atxmega256c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256c3/Makefile" ;; + "avr/lib/avrxmega6/atxmega256d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega256d3/Makefile" ;; + "avr/lib/avrxmega6/atxmega384c3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega384c3/Makefile" ;; + "avr/lib/avrxmega6/atxmega384d3/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega6/atxmega384d3/Makefile" ;; + "avr/lib/avrxmega7/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/Makefile" ;; + "avr/lib/avrxmega7/atxmega128a1/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1/Makefile" ;; + "avr/lib/avrxmega7/atxmega128a1u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a1u/Makefile" ;; + "avr/lib/avrxmega7/atxmega128a4u/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrxmega7/atxmega128a4u/Makefile" ;; + "avr/lib/avrtiny/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/Makefile" ;; + "avr/lib/avrtiny/attiny4/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny4/Makefile" ;; + "avr/lib/avrtiny/attiny5/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny5/Makefile" ;; + "avr/lib/avrtiny/attiny9/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny9/Makefile" ;; + "avr/lib/avrtiny/attiny10/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny10/Makefile" ;; + "avr/lib/avrtiny/attiny20/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny20/Makefile" ;; + "avr/lib/avrtiny/attiny40/Makefile") CONFIG_FILES="$CONFIG_FILES avr/lib/avrtiny/attiny40/Makefile" ;; + + *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; + esac +done + + +# If the user did not use the arguments to specify the items to instantiate, +# then the envvar interface is used. Set only those that are not. +# We use the long form for the default assignment because of an extremely +# bizarre bug on SunOS 4.1.3. +if $ac_need_defaults; then + test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files + test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers + test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands +fi + +# Have a temporary directory for convenience. Make it in the build tree +# simply because there is no reason against having it here, and in addition, +# creating and moving files from /tmp can sometimes cause problems. +# Hook for its removal unless debugging. +# Note that there is a small window in which the directory will not be cleaned: +# after its creation but before its name has been assigned to `$tmp'. +$debug || +{ + tmp= ac_tmp= + trap 'exit_status=$? + : "${ac_tmp:=$tmp}" + { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status +' 0 + trap 'as_fn_exit 1' 1 2 13 15 +} +# Create a (secure) tmp directory for tmp files. + +{ + tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && + test -d "$tmp" +} || +{ + tmp=./conf$$-$RANDOM + (umask 077 && mkdir "$tmp") +} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 +ac_tmp=$tmp + +# Set up the scripts for CONFIG_FILES section. +# No need to generate them if there are no CONFIG_FILES. +# This happens for instance with `./config.status config.h'. +if test -n "$CONFIG_FILES"; then + + +ac_cr=`echo X | tr X '\015'` +# On cygwin, bash can eat \r inside `` if the user requested igncr. +# But we know of no other shell where ac_cr would be empty at this +# point, so we can use a bashism as a fallback. +if test "x$ac_cr" = x; then + eval ac_cr=\$\'\\r\' +fi +ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` +if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then + ac_cs_awk_cr='\\r' +else + ac_cs_awk_cr=$ac_cr +fi + +echo 'BEGIN {' >"$ac_tmp/subs1.awk" && +_ACEOF + + +{ + echo "cat >conf$$subs.awk <<_ACEOF" && + echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && + echo "_ACEOF" +} >conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 +ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` +ac_delim='%!_!# ' +for ac_last_try in false false false false false :; do + . ./conf$$subs.sh || + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + + ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` + if test $ac_delim_n = $ac_delim_num; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done +rm -f conf$$subs.sh + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && +_ACEOF +sed -n ' +h +s/^/S["/; s/!.*/"]=/ +p +g +s/^[^!]*!// +:repl +t repl +s/'"$ac_delim"'$// +t delim +:nl +h +s/\(.\{148\}\)..*/\1/ +t more1 +s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ +p +n +b repl +:more1 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t nl +:delim +h +s/\(.\{148\}\)..*/\1/ +t more2 +s/["\\]/\\&/g; s/^/"/; s/$/"/ +p +b +:more2 +s/["\\]/\\&/g; s/^/"/; s/$/"\\/ +p +g +s/.\{148\}// +t delim +' >$CONFIG_STATUS || ac_write_fail=1 +rm -f conf$$subs.awk +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 +_ACAWK +cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && + for (key in S) S_is_set[key] = 1 + FS = "" + +} +{ + line = $ 0 + nfields = split(line, field, "@") + substed = 0 + len = length(field[1]) + for (i = 2; i < nfields; i++) { + key = field[i] + keylen = length(key) + if (S_is_set[key]) { + value = S[key] + line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) + len += length(value) + length(field[++i]) + substed = 1 + } else + len += 1 + keylen + } + + print line +} + +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then + sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" +else + cat +fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ + || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 +_ACEOF + +# VPATH may cause trouble with some makes, so we remove sole $(srcdir), +# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and +# trailing colons and then remove the whole line if VPATH becomes empty +# (actually we leave an empty line to preserve line numbers). +if test "x$srcdir" = x.; then + ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ +h +s/// +s/^/:/ +s/[ ]*$/:/ +s/:\$(srcdir):/:/g +s/:\${srcdir}:/:/g +s/:@srcdir@:/:/g +s/^:*// +s/:*$// +x +s/\(=[ ]*\).*/\1/ +G +s/\n// +s/^[^=]*=[ ]*$// +}' +fi + +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 +fi # test -n "$CONFIG_FILES" + +# Set up the scripts for CONFIG_HEADERS section. +# No need to generate them if there are no CONFIG_HEADERS. +# This happens for instance with `./config.status Makefile'. +if test -n "$CONFIG_HEADERS"; then +cat >"$ac_tmp/defines.awk" <<\_ACAWK || +BEGIN { +_ACEOF + +# Transform confdefs.h into an awk script `defines.awk', embedded as +# here-document in config.status, that substitutes the proper values into +# config.h.in to produce config.h. + +# Create a delimiter string that does not exist in confdefs.h, to ease +# handling of long lines. +ac_delim='%!_!# ' +for ac_last_try in false false :; do + ac_tt=`sed -n "/$ac_delim/p" confdefs.h` + if test -z "$ac_tt"; then + break + elif $ac_last_try; then + as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5 + else + ac_delim="$ac_delim!$ac_delim _$ac_delim!! " + fi +done + +# For the awk script, D is an array of macro values keyed by name, +# likewise P contains macro parameters if any. Preserve backslash +# newline sequences. + +ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* +sed -n ' +s/.\{148\}/&'"$ac_delim"'/g +t rset +:rset +s/^[ ]*#[ ]*define[ ][ ]*/ / +t def +d +:def +s/\\$// +t bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3"/p +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p +d +:bsnl +s/["\\]/\\&/g +s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ +D["\1"]=" \3\\\\\\n"\\/p +t cont +s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p +t cont +d +:cont +n +s/.\{148\}/&'"$ac_delim"'/g +t clear +:clear +s/\\$// +t bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/"/p +d +:bsnlc +s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p +b cont +' >$CONFIG_STATUS || ac_write_fail=1 + +cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 + for (key in D) D_is_set[key] = 1 + FS = "" +} +/^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { + line = \$ 0 + split(line, arg, " ") + if (arg[1] == "#") { + defundef = arg[2] + mac1 = arg[3] + } else { + defundef = substr(arg[1], 2) + mac1 = arg[2] + } + split(mac1, mac2, "(") #) + macro = mac2[1] + prefix = substr(line, 1, index(line, defundef) - 1) + if (D_is_set[macro]) { + # Preserve the white space surrounding the "#". + print prefix "define", macro P[macro] D[macro] + next + } else { + # Replace #undef with comments. This is necessary, for example, + # in the case of _POSIX_SOURCE, which is predefined and required + # on some systems where configure will not decide to define it. + if (defundef == "undef") { + print "/*", prefix defundef, macro, "*/" + next + } + } +} +{ print } +_ACAWK +_ACEOF +cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 + as_fn_error $? "could not setup config headers machinery" "$LINENO" 5 +fi # test -n "$CONFIG_HEADERS" + + +eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" +shift +for ac_tag +do + case $ac_tag in + :[FHLC]) ac_mode=$ac_tag; continue;; + esac + case $ac_mode$ac_tag in + :[FHL]*:*);; + :L* | :C*:*) as_fn_error $? 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"write failure creating $CONFIG_STATUS" "$LINENO" 5 + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || as_fn_exit 1 +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/depcomp +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/depcomp @@ -0,0 +1,791 @@ +#! /bin/sh +# depcomp - compile a program generating dependencies as side-effects + +scriptversion=2013-05-30.07; # UTC + +# Copyright (C) 1999-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Originally written by Alexandre Oliva . + +case $1 in + '') + echo "$0: No command. Try '$0 --help' for more information." 1>&2 + exit 1; + ;; + -h | --h*) + cat <<\EOF +Usage: depcomp [--help] [--version] PROGRAM [ARGS] + +Run PROGRAMS ARGS to compile a file, generating dependencies +as side-effects. + +Environment variables: + depmode Dependency tracking mode. + source Source file read by 'PROGRAMS ARGS'. + object Object file output by 'PROGRAMS ARGS'. + DEPDIR directory where to store dependencies. + depfile Dependency file to output. + tmpdepfile Temporary file to use when outputting dependencies. + libtool Whether libtool is used (yes/no). + +Report bugs to . +EOF + exit $? + ;; + -v | --v*) + echo "depcomp $scriptversion" + exit $? + ;; +esac + +# Get the directory component of the given path, and save it in the +# global variables '$dir'. Note that this directory component will +# be either empty or ending with a '/' character. This is deliberate. +set_dir_from () +{ + case $1 in + */*) dir=`echo "$1" | sed -e 's|/[^/]*$|/|'`;; + *) dir=;; + esac +} + +# Get the suffix-stripped basename of the given path, and save it the +# global variable '$base'. +set_base_from () +{ + base=`echo "$1" | sed -e 's|^.*/||' -e 's/\.[^.]*$//'` +} + +# If no dependency file was actually created by the compiler invocation, +# we still have to create a dummy depfile, to avoid errors with the +# Makefile "include basename.Plo" scheme. +make_dummy_depfile () +{ + echo "#dummy" > "$depfile" +} + +# Factor out some common post-processing of the generated depfile. +# Requires the auxiliary global variable '$tmpdepfile' to be set. +aix_post_process_depfile () +{ + # If the compiler actually managed to produce a dependency file, + # post-process it. + if test -f "$tmpdepfile"; then + # Each line is of the form 'foo.o: dependency.h'. + # Do two passes, one to just change these to + # $object: dependency.h + # and one to simply output + # dependency.h: + # which is needed to avoid the deleted-header problem. + { sed -e "s,^.*\.[$lower]*:,$object:," < "$tmpdepfile" + sed -e "s,^.*\.[$lower]*:[$tab ]*,," -e 's,$,:,' < "$tmpdepfile" + } > "$depfile" + rm -f "$tmpdepfile" + else + make_dummy_depfile + fi +} + +# A tabulation character. +tab=' ' +# A newline character. +nl=' +' +# Character ranges might be problematic outside the C locale. +# These definitions help. +upper=ABCDEFGHIJKLMNOPQRSTUVWXYZ +lower=abcdefghijklmnopqrstuvwxyz +digits=0123456789 +alpha=${upper}${lower} + +if test -z "$depmode" || test -z "$source" || test -z "$object"; then + echo "depcomp: Variables source, object and depmode must be set" 1>&2 + exit 1 +fi + +# Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. +depfile=${depfile-`echo "$object" | + sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} +tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} + +rm -f "$tmpdepfile" + +# Avoid interferences from the environment. +gccflag= dashmflag= + +# Some modes work just like other modes, but use different flags. We +# parameterize here, but still list the modes in the big case below, +# to make depend.m4 easier to write. Note that we *cannot* use a case +# here, because this file can only contain one case statement. +if test "$depmode" = hp; then + # HP compiler uses -M and no extra arg. + gccflag=-M + depmode=gcc +fi + +if test "$depmode" = dashXmstdout; then + # This is just like dashmstdout with a different argument. + dashmflag=-xM + depmode=dashmstdout +fi + +cygpath_u="cygpath -u -f -" +if test "$depmode" = msvcmsys; then + # This is just like msvisualcpp but w/o cygpath translation. + # Just convert the backslash-escaped backslashes to single forward + # slashes to satisfy depend.m4 + cygpath_u='sed s,\\\\,/,g' + depmode=msvisualcpp +fi + +if test "$depmode" = msvc7msys; then + # This is just like msvc7 but w/o cygpath translation. + # Just convert the backslash-escaped backslashes to single forward + # slashes to satisfy depend.m4 + cygpath_u='sed s,\\\\,/,g' + depmode=msvc7 +fi + +if test "$depmode" = xlc; then + # IBM C/C++ Compilers xlc/xlC can output gcc-like dependency information. + gccflag=-qmakedep=gcc,-MF + depmode=gcc +fi + +case "$depmode" in +gcc3) +## gcc 3 implements dependency tracking that does exactly what +## we want. Yay! Note: for some reason libtool 1.4 doesn't like +## it if -MD -MP comes after the -MF stuff. Hmm. +## Unfortunately, FreeBSD c89 acceptance of flags depends upon +## the command line argument order; so add the flags where they +## appear in depend2.am. Note that the slowdown incurred here +## affects only configure: in makefiles, %FASTDEP% shortcuts this. + for arg + do + case $arg in + -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; + *) set fnord "$@" "$arg" ;; + esac + shift # fnord + shift # $arg + done + "$@" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + mv "$tmpdepfile" "$depfile" + ;; + +gcc) +## Note that this doesn't just cater to obsosete pre-3.x GCC compilers. +## but also to in-use compilers like IMB xlc/xlC and the HP C compiler. +## (see the conditional assignment to $gccflag above). +## There are various ways to get dependency output from gcc. Here's +## why we pick this rather obscure method: +## - Don't want to use -MD because we'd like the dependencies to end +## up in a subdir. Having to rename by hand is ugly. +## (We might end up doing this anyway to support other compilers.) +## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like +## -MM, not -M (despite what the docs say). Also, it might not be +## supported by the other compilers which use the 'gcc' depmode. +## - Using -M directly means running the compiler twice (even worse +## than renaming). + if test -z "$gccflag"; then + gccflag=-MD, + fi + "$@" -Wp,"$gccflag$tmpdepfile" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + echo "$object : \\" > "$depfile" + # The second -e expression handles DOS-style file names with drive + # letters. + sed -e 's/^[^:]*: / /' \ + -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" +## This next piece of magic avoids the "deleted header file" problem. +## The problem is that when a header file which appears in a .P file +## is deleted, the dependency causes make to die (because there is +## typically no way to rebuild the header). We avoid this by adding +## dummy dependencies for each header file. Too bad gcc doesn't do +## this for us directly. +## Some versions of gcc put a space before the ':'. On the theory +## that the space means something, we add a space to the output as +## well. hp depmode also adds that space, but also prefixes the VPATH +## to the object. Take care to not repeat it in the output. +## Some versions of the HPUX 10.20 sed can't process this invocation +## correctly. Breaking it into two sed invocations is a workaround. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^\\$//' -e '/^$/d' -e "s|.*$object$||" -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +sgi) + if test "$libtool" = yes; then + "$@" "-Wp,-MDupdate,$tmpdepfile" + else + "$@" -MDupdate "$tmpdepfile" + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + + if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files + echo "$object : \\" > "$depfile" + # Clip off the initial element (the dependent). Don't try to be + # clever and replace this with sed code, as IRIX sed won't handle + # lines with more than a fixed number of characters (4096 in + # IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines; + # the IRIX cc adds comments like '#:fec' to the end of the + # dependency line. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' \ + | tr "$nl" ' ' >> "$depfile" + echo >> "$depfile" + # The second pass generates a dummy entry for each header file. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \ + >> "$depfile" + else + make_dummy_depfile + fi + rm -f "$tmpdepfile" + ;; + +xlc) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +aix) + # The C for AIX Compiler uses -M and outputs the dependencies + # in a .u file. In older versions, this file always lives in the + # current directory. Also, the AIX compiler puts '$object:' at the + # start of each line; $object doesn't have directory information. + # Version 6 uses the directory in both cases. + set_dir_from "$object" + set_base_from "$object" + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.u + tmpdepfile2=$base.u + tmpdepfile3=$dir.libs/$base.u + "$@" -Wc,-M + else + tmpdepfile1=$dir$base.u + tmpdepfile2=$dir$base.u + tmpdepfile3=$dir$base.u + "$@" -M + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + do + test -f "$tmpdepfile" && break + done + aix_post_process_depfile + ;; + +tcc) + # tcc (Tiny C Compiler) understand '-MD -MF file' since version 0.9.26 + # FIXME: That version still under development at the moment of writing. + # Make that this statement remains true also for stable, released + # versions. + # It will wrap lines (doesn't matter whether long or short) with a + # trailing '\', as in: + # + # foo.o : \ + # foo.c \ + # foo.h \ + # + # It will put a trailing '\' even on the last line, and will use leading + # spaces rather than leading tabs (at least since its commit 0394caf7 + # "Emit spaces for -MD"). + "$@" -MD -MF "$tmpdepfile" + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + # Each non-empty line is of the form 'foo.o : \' or ' dep.h \'. + # We have to change lines of the first kind to '$object: \'. + sed -e "s|.*:|$object :|" < "$tmpdepfile" > "$depfile" + # And for each line of the second kind, we have to emit a 'dep.h:' + # dummy dependency, to avoid the deleted-header problem. + sed -n -e 's|^ *\(.*\) *\\$|\1:|p' < "$tmpdepfile" >> "$depfile" + rm -f "$tmpdepfile" + ;; + +## The order of this option in the case statement is important, since the +## shell code in configure will try each of these formats in the order +## listed in this file. A plain '-MD' option would be understood by many +## compilers, so we must ensure this comes after the gcc and icc options. +pgcc) + # Portland's C compiler understands '-MD'. + # Will always output deps to 'file.d' where file is the root name of the + # source file under compilation, even if file resides in a subdirectory. + # The object file name does not affect the name of the '.d' file. + # pgcc 10.2 will output + # foo.o: sub/foo.c sub/foo.h + # and will wrap long lines using '\' : + # foo.o: sub/foo.c ... \ + # sub/foo.h ... \ + # ... + set_dir_from "$object" + # Use the source, not the object, to determine the base name, since + # that's sadly what pgcc will do too. + set_base_from "$source" + tmpdepfile=$base.d + + # For projects that build the same source file twice into different object + # files, the pgcc approach of using the *source* file root name can cause + # problems in parallel builds. Use a locking strategy to avoid stomping on + # the same $tmpdepfile. + lockdir=$base.d-lock + trap " + echo '$0: caught signal, cleaning up...' >&2 + rmdir '$lockdir' + exit 1 + " 1 2 13 15 + numtries=100 + i=$numtries + while test $i -gt 0; do + # mkdir is a portable test-and-set. + if mkdir "$lockdir" 2>/dev/null; then + # This process acquired the lock. + "$@" -MD + stat=$? + # Release the lock. + rmdir "$lockdir" + break + else + # If the lock is being held by a different process, wait + # until the winning process is done or we timeout. + while test -d "$lockdir" && test $i -gt 0; do + sleep 1 + i=`expr $i - 1` + done + fi + i=`expr $i - 1` + done + trap - 1 2 13 15 + if test $i -le 0; then + echo "$0: failed to acquire lock after $numtries attempts" >&2 + echo "$0: check lockdir '$lockdir'" >&2 + exit 1 + fi + + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + # Each line is of the form `foo.o: dependent.h', + # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. + # Do two passes, one to just change these to + # `$object: dependent.h' and one to simply `dependent.h:'. + sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process this invocation + # correctly. Breaking it into two sed invocations is a workaround. + sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +hp2) + # The "hp" stanza above does not work with aCC (C++) and HP's ia64 + # compilers, which have integrated preprocessors. The correct option + # to use with these is +Maked; it writes dependencies to a file named + # 'foo.d', which lands next to the object file, wherever that + # happens to be. + # Much of this is similar to the tru64 case; see comments there. + set_dir_from "$object" + set_base_from "$object" + if test "$libtool" = yes; then + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir.libs/$base.d + "$@" -Wc,+Maked + else + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir$base.d + "$@" +Maked + fi + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" + do + test -f "$tmpdepfile" && break + done + if test -f "$tmpdepfile"; then + sed -e "s,^.*\.[$lower]*:,$object:," "$tmpdepfile" > "$depfile" + # Add 'dependent.h:' lines. + sed -ne '2,${ + s/^ *// + s/ \\*$// + s/$/:/ + p + }' "$tmpdepfile" >> "$depfile" + else + make_dummy_depfile + fi + rm -f "$tmpdepfile" "$tmpdepfile2" + ;; + +tru64) + # The Tru64 compiler uses -MD to generate dependencies as a side + # effect. 'cc -MD -o foo.o ...' puts the dependencies into 'foo.o.d'. + # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put + # dependencies in 'foo.d' instead, so we check for that too. + # Subdirectories are respected. + set_dir_from "$object" + set_base_from "$object" + + if test "$libtool" = yes; then + # Libtool generates 2 separate objects for the 2 libraries. These + # two compilations output dependencies in $dir.libs/$base.o.d and + # in $dir$base.o.d. We have to check for both files, because + # one of the two compilations can be disabled. We should prefer + # $dir$base.o.d over $dir.libs/$base.o.d because the latter is + # automatically cleaned when .libs/ is deleted, while ignoring + # the former would cause a distcleancheck panic. + tmpdepfile1=$dir$base.o.d # libtool 1.5 + tmpdepfile2=$dir.libs/$base.o.d # Likewise. + tmpdepfile3=$dir.libs/$base.d # Compaq CCC V6.2-504 + "$@" -Wc,-MD + else + tmpdepfile1=$dir$base.d + tmpdepfile2=$dir$base.d + tmpdepfile3=$dir$base.d + "$@" -MD + fi + + stat=$? + if test $stat -ne 0; then + rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + exit $stat + fi + + for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" + do + test -f "$tmpdepfile" && break + done + # Same post-processing that is required for AIX mode. + aix_post_process_depfile + ;; + +msvc7) + if test "$libtool" = yes; then + showIncludes=-Wc,-showIncludes + else + showIncludes=-showIncludes + fi + "$@" $showIncludes > "$tmpdepfile" + stat=$? + grep -v '^Note: including file: ' "$tmpdepfile" + if test $stat -ne 0; then + rm -f "$tmpdepfile" + exit $stat + fi + rm -f "$depfile" + echo "$object : \\" > "$depfile" + # The first sed program below extracts the file names and escapes + # backslashes for cygpath. The second sed program outputs the file + # name when reading, but also accumulates all include files in the + # hold buffer in order to output them again at the end. This only + # works with sed implementations that can handle large buffers. + sed < "$tmpdepfile" -n ' +/^Note: including file: *\(.*\)/ { + s//\1/ + s/\\/\\\\/g + p +}' | $cygpath_u | sort -u | sed -n ' +s/ /\\ /g +s/\(.*\)/'"$tab"'\1 \\/p +s/.\(.*\) \\/\1:/ +H +$ { + s/.*/'"$tab"'/ + G + p +}' >> "$depfile" + echo >> "$depfile" # make sure the fragment doesn't end with a backslash + rm -f "$tmpdepfile" + ;; + +msvc7msys) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +#nosideeffect) + # This comment above is used by automake to tell side-effect + # dependency tracking mechanisms from slower ones. + +dashmstdout) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout, regardless of -o. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + # Remove '-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + test -z "$dashmflag" && dashmflag=-M + # Require at least two characters before searching for ':' + # in the target name. This is to cope with DOS-style filenames: + # a dependency such as 'c:/foo/bar' could be seen as target 'c' otherwise. + "$@" $dashmflag | + sed "s|^[$tab ]*[^:$tab ][^:][^:]*:[$tab ]*|$object: |" > "$tmpdepfile" + rm -f "$depfile" + cat < "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process this sed invocation + # correctly. Breaking it into two sed invocations is a workaround. + tr ' ' "$nl" < "$tmpdepfile" \ + | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +dashXmstdout) + # This case only exists to satisfy depend.m4. It is never actually + # run, as this mode is specially recognized in the preamble. + exit 1 + ;; + +makedepend) + "$@" || exit $? + # Remove any Libtool call + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + # X makedepend + shift + cleared=no eat=no + for arg + do + case $cleared in + no) + set ""; shift + cleared=yes ;; + esac + if test $eat = yes; then + eat=no + continue + fi + case "$arg" in + -D*|-I*) + set fnord "$@" "$arg"; shift ;; + # Strip any option that makedepend may not understand. Remove + # the object too, otherwise makedepend will parse it as a source file. + -arch) + eat=yes ;; + -*|$object) + ;; + *) + set fnord "$@" "$arg"; shift ;; + esac + done + obj_suffix=`echo "$object" | sed 's/^.*\././'` + touch "$tmpdepfile" + ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@" + rm -f "$depfile" + # makedepend may prepend the VPATH from the source file name to the object. + # No need to regex-escape $object, excess matching of '.' is harmless. + sed "s|^.*\($object *:\)|\1|" "$tmpdepfile" > "$depfile" + # Some versions of the HPUX 10.20 sed can't process the last invocation + # correctly. Breaking it into two sed invocations is a workaround. + sed '1,2d' "$tmpdepfile" \ + | tr ' ' "$nl" \ + | sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' \ + | sed -e 's/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" "$tmpdepfile".bak + ;; + +cpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + # Remove '-o $object'. + IFS=" " + for arg + do + case $arg in + -o) + shift + ;; + $object) + shift + ;; + *) + set fnord "$@" "$arg" + shift # fnord + shift # $arg + ;; + esac + done + + "$@" -E \ + | sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ + -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ + | sed '$ s: \\$::' > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + cat < "$tmpdepfile" >> "$depfile" + sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +msvisualcpp) + # Important note: in order to support this mode, a compiler *must* + # always write the preprocessed file to stdout. + "$@" || exit $? + + # Remove the call to Libtool. + if test "$libtool" = yes; then + while test "X$1" != 'X--mode=compile'; do + shift + done + shift + fi + + IFS=" " + for arg + do + case "$arg" in + -o) + shift + ;; + $object) + shift + ;; + "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI") + set fnord "$@" + shift + shift + ;; + *) + set fnord "$@" "$arg" + shift + shift + ;; + esac + done + "$@" -E 2>/dev/null | + sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::\1:p' | $cygpath_u | sort -u > "$tmpdepfile" + rm -f "$depfile" + echo "$object : \\" > "$depfile" + sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::'"$tab"'\1 \\:p' >> "$depfile" + echo "$tab" >> "$depfile" + sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::\1\::p' >> "$depfile" + rm -f "$tmpdepfile" + ;; + +msvcmsys) + # This case exists only to let depend.m4 do its work. It works by + # looking at the text of this script. This case will never be run, + # since it is checked for above. + exit 1 + ;; + +none) + exec "$@" + ;; + +*) + echo "Unknown depmode $depmode" 1>&2 + exit 1 + ;; +esac + +exit 0 + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/doc/api/Makefile.am +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/doc/api/Makefile.am @@ -201,6 +201,8 @@ sed -e '/renewcommand.*cftchap.*font/s/renew/new/' \ doxygen.sty > tmp.$$ && \ mv -f tmp.$$ doxygen.sty + cd latex_src && sed -e 's/\(longtabu.*\)X\[-1\]/\1l/' -i *.tex *.sty + cd latex_src && sed -e 's/X\[-1,\(.\)\]/\1/g' -i doxygen.sty #doxygen.config: doxygen.config.in $(top_srcdir)/stamp-h1 doxygen.config: doxygen.config.in @@ -227,7 +229,7 @@ dox-pdf: $(USER_MANUAL).pdf $(USER_MANUAL).pdf: latex_src/refman.tex - cd latex_src && ${MAKE} refman.pdf + -cd latex_src && ${MAKE} refman.pdf cp latex_src/refman.pdf $(USER_MANUAL).pdf # Install rules for the various documentation parts. The actual @@ -258,7 +260,7 @@ install-dox-man: dox-html $(mkinstalldirs) $(DESTDIR)$(mandir)/man3 - $(INSTALL_DATA) man/man3/*.3 $(DESTDIR)$(mandir)/man3 + $(INSTALL_DATA) man/man3/*.3avr $(DESTDIR)$(mandir)/man3 .PHONY: html xml latex pdf demo demodox \ dox-html dox-xml dox-pdf install-pdf install-html install-xml \ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/doc/api/doxygen.config.in +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/doc/api/doxygen.config.in @@ -1848,14 +1848,14 @@ # The default value is: .3. # This tag requires that the tag GENERATE_MAN is set to YES. -MAN_EXTENSION = .3 +MAN_EXTENSION = .3avr # The MAN_SUBDIR tag determines the name of the directory created within # MAN_OUTPUT in which the man pages are placed. If defaults to man followed by # MAN_EXTENSION with the initial . removed. # This tag requires that the tag GENERATE_MAN is set to YES. -MAN_SUBDIR = +#MAN_SUBDIR = # If the MAN_LINKS tag is set to YES and doxygen generates man output, then it # will generate one additional man file for each entity documented in the real @@ -2386,3 +2386,4 @@ # This tag requires that the tag HAVE_DOT is set to YES. DOT_CLEANUP = YES +MAN_SUBDIR = man3 --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io1200.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io1200.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io1200.h - definitions for AT90S1200 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io2313.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io2313.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2313.h - definitions for AT90S2313 */ @@ -378,7 +378,6 @@ #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x01 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io2323.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io2323.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2323.h - definitions for AT90S2323 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io2333.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io2333.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2333.h - definitions for AT90S2333 */ @@ -458,5 +458,4 @@ #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_IO2333_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io2343.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io2343.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io2343.h - definitions for AT90S2343 */ @@ -208,9 +208,7 @@ #define SIGNATURE_1 0x91 #define SIGNATURE_2 0x03 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_IO2343_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io43u32x.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io43u32x.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io43u32x.h - definitions for AT43USB32x */ @@ -437,5 +437,4 @@ #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_43USB32X_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io43u35x.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io43u35x.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io43u35x.h - definitions for AT43USB35x */ @@ -429,5 +429,4 @@ #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_43USB355_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io4414.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io4414.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4414.h - definitions for AT90S4414 */ @@ -494,9 +494,7 @@ #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x01 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_IO4414_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io4433.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io4433.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4433.h - definitions for AT90S4433 */ @@ -483,9 +483,7 @@ #define SIGNATURE_1 0x92 #define SIGNATURE_2 0x03 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_IO4433_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io4434.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io4434.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io4434.h - definitions for AT90S4434 */ @@ -580,11 +580,9 @@ #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x03 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - #endif /* _AVR_IO4434_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io76c711.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io76c711.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io76c711.h - definitions for AT76C711 */ @@ -477,6 +477,11 @@ #define E2END 0 #define FLASHEND 0x3FFF +#define SLEEP_MODE_IDLE 0 +#define SLEEP_MODE_ADC _BV(SM0) +#define SLEEP_MODE_PWR_DOWN _BV(SM1) +#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) + /* AT76C711 data space memory map (ranges not listed are reserved): 0x0000 - 0x001F - AVR registers @@ -490,12 +495,5 @@ 0x3000 - 0x37FF - DPRAM 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other AVR devices did that as well (no need to use LPM!) - */ - -#define SLEEP_MODE_IDLE 0 -#define SLEEP_MODE_ADC _BV(SM0) -#define SLEEP_MODE_PWR_DOWN _BV(SM1) -#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - #endif /* _AVR_IO76C711_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io8515.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io8515.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io8515.h - definitions for AT90S8515 */ @@ -495,9 +495,7 @@ #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x01 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_PWR_DOWN _BV(SM) - #endif /* _AVR_IO8515_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io8534.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io8534.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ /* avr/io8534.h - definitions for AT90C8534 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io8535.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io8535.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io8535.h - definitions for AT90S8535 */ @@ -581,11 +581,9 @@ #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x03 - #define SLEEP_MODE_IDLE 0 #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) - #endif /* _AVR_IO8535_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io86r401.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io86r401.h @@ -30,8 +30,6 @@ /* avr/io86r401.h - definitions for AT86RF401 */ -/* $Id$ */ - #ifndef _AVR_IO86RF401_H_ #define _AVR_IO86RF401_H_ 1 @@ -288,7 +286,7 @@ #define ZH r31 /* Constants */ -#define RAMSTART 0x60 +#define RAMSTART 0x60 #define RAMEND 0xDF #define XRAMEND RAMEND #define E2END 0x7F --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm1.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm1.h @@ -29,7 +29,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/iopwm1.h - definitions for AT90PWM1 device */ @@ -1149,11 +1149,9 @@ #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST - #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* _AVR_IOPWM1_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm161.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm161.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_AT90PWM161_H_INCLUDED #define _AVR_AT90PWM161_H_INCLUDED @@ -78,13 +76,29 @@ #define DDRB _SFR_IO8(0x04) #define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 #define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 #define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 #define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 #define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 #define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 #define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 #define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PORTB7 7 @@ -136,13 +150,29 @@ #define DDRD _SFR_IO8(0x0A) #define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 #define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 #define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 #define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 #define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 #define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 #define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 #define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 #define PORTD _SFR_IO8(0x0B) #define PORTD7 7 @@ -161,8 +191,14 @@ #define DDRE _SFR_IO8(0x0D) #define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 #define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 #define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 #define PORTE _SFR_IO8(0x0E) #define PORTE2 2 @@ -721,6 +757,14 @@ +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) + /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* PSC2 Capture Event */ @@ -830,6 +874,8 @@ #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8) + /* High Fuse Byte */ #define FUSE_BOOTRST (unsigned char)~_BV(0) @@ -840,6 +886,8 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + /* Extended Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) @@ -850,6 +898,8 @@ #define FUSE_PSC0RB (unsigned char)~_BV(5) #define FUSE_PSC2RBA (unsigned char)~_BV(6) #define FUSE_PSC2RB (unsigned char)~_BV(7) +#define EFUSE_DEFAULT (FUSE_BODLEVEL1) + /* Lock Bits */ @@ -864,11 +914,5 @@ #define SIGNATURE_2 0x8B - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm216.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm216.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm216.h - definitions for AT90PWM216 */ @@ -1217,11 +1217,9 @@ #define SIGNATURE_1 0x94 #define SIGNATURE_2 0x83 - #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* _AVR_IO90PWM216_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm2b.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm2b.h @@ -29,7 +29,7 @@ POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm2b.h - definitions for AT90PWM2B */ @@ -1458,11 +1458,9 @@ #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x83 - #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* _AVR_IO90PWM2B_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm316.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm316.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm316.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm316.h - definitions for AT90PWM316 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm3b.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm3b.h @@ -29,7 +29,7 @@ POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm3b.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwm3b.h - definitions for AT90PWM3B */ @@ -1458,11 +1458,9 @@ #define SIGNATURE_1 0x93 #define SIGNATURE_2 0x83 - #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* _AVR_IO90PWM3B_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwm81.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwm81.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */ /* avr/io90pwm81.h - definitions for AT90PWM81 */ @@ -1028,11 +1028,9 @@ #define SIGNATURE_2 0x88 - #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_ADC (0x01<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_STANDBY (0x06<<1) - #endif /* _AVR_AT90PWM81_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90pwmx.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90pwmx.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90pwmx.h 2225 2011-03-02 16:27:26Z arcanum $ */ /* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */ @@ -1407,11 +1407,9 @@ #define __BOOT_LOCK_BITS_0_EXIST #define __BOOT_LOCK_BITS_1_EXIST - #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_ADC _BV(SM0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2)) - #endif /* _AVR_IO90PWMX_H_ */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/io90scr100.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/io90scr100.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */ /* avr/io90scr100.h - definitions for AT90SCR100 */ @@ -1709,8 +1709,6 @@ #define SIGNATURE_1 0x96 #define SIGNATURE_2 0xC1 - - #define SLEEP_MODE_IDLE (0) #define SLEEP_MODE_PWR_DOWN _BV(SM1) #define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1)) --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/ioa5272.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/ioa5272.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_ATA5272_H_INCLUDED #define _AVR_ATA5272_H_INCLUDED @@ -62,13 +60,29 @@ #define DDRA _SFR_IO8(0x01) #define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 #define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 #define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 #define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 #define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 #define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 #define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 #define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PORTA7 7 @@ -92,13 +106,29 @@ #define DDRB _SFR_IO8(0x04) #define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 #define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 #define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 #define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 #define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 #define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 #define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 #define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PORTB7 7 @@ -113,6 +143,10 @@ /* Reserved [0x06..0x11] */ #define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 /* Reserved [0x13..0x14] */ @@ -233,8 +267,8 @@ #define MCUCR _SFR_IO8(0x35) #define PUD 4 -#define BODS 5 -#define BODSE 6 +#define BODSE 5 +#define BODS 6 /* Reserved [0x36] */ @@ -617,6 +651,14 @@ +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) + /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ @@ -726,6 +768,8 @@ #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8) + /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) @@ -736,9 +780,13 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + /* Lock Bits */ @@ -751,11 +799,5 @@ #define SIGNATURE_2 0x87 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) - #endif /* #ifdef _AVR_ATA5272_H_INCLUDED */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/ioa5505.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/ioa5505.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_ATA5505_H_INCLUDED #define _AVR_ATA5505_H_INCLUDED @@ -62,13 +60,29 @@ #define DDRA _SFR_IO8(0x01) #define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 #define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 #define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 #define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 #define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 #define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 #define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 #define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 #define PORTA _SFR_IO8(0x02) #define PORTA7 7 @@ -92,13 +106,29 @@ #define DDRB _SFR_IO8(0x04) #define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 #define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 #define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 #define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 #define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 #define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 #define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 #define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 #define PORTB _SFR_IO8(0x05) #define PORTB7 7 @@ -113,6 +143,10 @@ /* Reserved [0x06..0x11] */ #define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 /* Reserved [0x13..0x14] */ @@ -233,8 +267,8 @@ #define MCUCR _SFR_IO8(0x35) #define PUD 4 -#define BODS 5 -#define BODSE 6 +#define BODSE 5 +#define BODS 6 /* Reserved [0x36] */ @@ -617,6 +651,14 @@ +/* Values and associated defines */ + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) + /* Interrupt vectors */ /* Vector 0 is the reset vector */ /* External Interrupt Request 0 */ @@ -726,6 +768,8 @@ #define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) #define FUSE_CKOUT (unsigned char)~_BV(6) #define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_SUT_CKSEL0 & FUSE_SUT_CKSEL2 & FUSE_SUT_CKSEL3 & FUSE_SUT_CKSEL4 & FUSE_CKDIV8) + /* High Fuse Byte */ #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) @@ -736,9 +780,13 @@ #define FUSE_SPIEN (unsigned char)~_BV(5) #define FUSE_DWEN (unsigned char)~_BV(6) #define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + /* Extended Fuse Byte */ #define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + /* Lock Bits */ @@ -751,11 +799,5 @@ #define SIGNATURE_2 0x87 - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_ADC (0x01<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) - #endif /* #ifdef _AVR_ATA5505_H_INCLUDED */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/ioa5702m322.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/ioa5702m322.h @@ -1,2591 +1,2591 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_ATA5702M322_H_INCLUDED -#define _AVR_ATA5702M322_H_INCLUDED - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5702m322.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define GPIOR0 _SFR_IO8(0x00) - -#define PRR1 _SFR_IO8(0x01) -#define PRT1 0 -#define PRT2 1 -#define PRT3 2 -#define PRT4 3 -#define PRT5 4 -#define PRLFR 5 -#define PRLFTP 6 -#define PRLFPH 7 - -#define __AVR_HAVE_PRR1 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5702m322.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define GPIOR0 _SFR_IO8(0x00) + +#define PRR1 _SFR_IO8(0x01) +#define PRT1 0 +#define PRT2 1 +#define PRT3 2 +#define PRT4 3 +#define PRT5 4 +#define PRLFR 5 +#define PRLFTP 6 +#define PRLFPH 7 + +#define __AVR_HAVE_PRR1 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5782.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5782.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5790n.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC7 7 -// Inserted "DDC7" from "DDRC7" due to compatibility -#define DDC7 7 -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define T3CR2 _SFR_IO8(0x0C) -#define T3GRES 0 -#define T3C2TM 1 -#define T3C2RM 2 - -#define TPCR _SFR_IO8(0x0D) -#define TPMA 0 -#define TPMOD 1 -#define TPMS0 2 -#define TPMS1 3 -#define TPMD0 4 -#define TPMD1 5 -#define TPPSD 6 -#define TPD 7 - -#define TPFR _SFR_IO8(0x0E) -#define TPF 0 -#define TPA 1 -#define TPGAP 2 -#define TPPSW 3 - -#define CMCR _SFR_IO8(0x0F) -#define CMM0 0 -#define CMM1 1 -#define SRCD 2 -#define CO32D 3 -#define CCS 4 -#define ECINS 5 -#define CMONEN 6 -#define CMCCE 7 - -#define CMSR _SFR_IO8(0x10) -#define ECF 0 -#define SXF 1 -#define RTCF 2 - -#define T2CR _SFR_IO8(0x11) -#define T2OTM 0 -#define T2CTM 1 -#define T2CRM 2 -#define T2GRM 3 -#define T2TOP 4 -#define T2RES 5 -#define T2TS 6 -#define T2E 7 - -#define T3CR _SFR_IO8(0x12) -#define T3OTM 0 -#define T3CTM 1 -#define T3CRM 2 -#define T3CPRM 3 -#define T3TOP 4 -#define T3RES 5 -#define T3CPTM 6 -#define T3E 7 - -#define AESCR _SFR_IO8(0x13) -#define AESWK 0 -#define AESWD 1 -#define AESIM 2 -#define AESD 3 -#define AESXOR 4 -#define AESRES 5 -#define AESE 7 - -#define AESSR _SFR_IO8(0x14) -#define AESRF 0 -#define AESERF 7 - -#define TMIFR _SFR_IO8(0x15) -#define TMRXF 0 -#define TMTXF 1 -#define TMTCF 2 -#define TMRXS 3 -#define TMTXS 4 - -#define VMSR _SFR_IO8(0x16) -#define VMF 0 - -#define PCIFR _SFR_IO8(0x17) -#define PCIF0 0 -#define PCIF1 1 - -#define LFFR _SFR_IO8(0x18) -#define LFID0F 0 -#define LFID1F 1 -#define LFFEF 2 -#define LFDBF 3 -#define LFRSF 4 -#define LFSDF 5 -#define LFMDF 6 -#define LFCAF 7 - -#define T0IFR _SFR_IO8(0x19) -#define T0F 0 - -#define T1IFR _SFR_IO8(0x1A) -#define T1F 0 - -#define T2IFR _SFR_IO8(0x1B) -#define T2OFF 0 -#define T2COF 1 - -#define T3IFR _SFR_IO8(0x1C) -#define T3OFF 0 -#define T3COF 1 -#define T3ICF 2 -#define T3CO2F 3 - -#define EIFR _SFR_IO8(0x1D) -#define INTF0 0 - -#define GPIOR _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEWE 1 -#define EEMWE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 -#define EELP 6 -#define NVMBSY 7 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define EEPR _SFR_IO8(0x23) -#define EEAP0 0 -#define EEAP1 1 -#define EEAP2 2 -#define EEAP3 3 - -#define EECCR _SFR_IO8(0x24) -#define EEL0 0 -#define EEL1 1 -#define EEL2 2 -#define EEL3 3 - -#define EECR2 _SFR_IO8(0x25) -#define EEBRE 0 -#define EEPAGE 1 - -#define PCICR _SFR_IO8(0x26) -#define PCIE0 0 -#define PCIE1 1 - -#define EIMSK _SFR_IO8(0x27) -#define INT0 0 - -#define TMDR _SFR_IO8(0x28) - -#define AESDR _SFR_IO8(0x29) - -#define AESKR _SFR_IO8(0x2A) -#define AESKR0 0 -#define AESKR1 1 -#define AESKR2 2 -#define AESKR3 3 -#define AESKR4 4 -#define AESKR5 5 -#define AESKR6 6 -#define AESKR7 7 - -#define VMCR _SFR_IO8(0x2B) -#define VMLS0 0 -#define VMLS1 1 -#define VMLS2 2 -#define VMLS3 3 -#define VMIM 4 -#define VMPS 5 -#define BODPD 6 -#define BODLS 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -#define LFCR0 _SFR_IO8(0x2F) -#define LFCE1 0 -#define LFCE2 1 -#define LFCE3 2 -#define LFBRS 3 -#define LFRBS 4 -#define LFMG 5 -#define LFVC0 6 -#define LFVC1 7 - -#define LFCR1 _SFR_IO8(0x30) -#define LFM0 0 -#define LFM1 1 -#define LFFM0 2 -#define LFFM1 3 -#define LFRMS 4 -#define LFRMSA 5 -#define LFQCE 6 -#define LFRE 7 - -/* Reserved [0x31] */ - -#define LFRDB _SFR_IO8(0x32) - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define TPRF 5 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -#define LFSR _SFR_IO8(0x36) -#define LFES 0 -#define LFSD 1 - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -#define T1CR _SFR_IO8(0x38) -#define T1PS0 0 -#define T1PS1 1 -#define T1IE 2 -#define T1CS0 3 -#define T1CS1 4 -#define T1E 7 - -#define T0CR _SFR_IO8(0x39) -#define T0PS0 0 -#define T0PS1 1 -#define T0PS2 2 -#define T0IE 3 -#define T0PR 4 - -/* Reserved [0x3A] */ - -#define CMIMR _SFR_IO8(0x3B) -#define ECIE 0 -#define SXIE 1 -#define RTCIE 2 - -#define CLKPR _SFR_IO8(0x3C) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLTPS0 3 -#define CLTPS1 4 -#define CLTPS2 5 -#define CLKPCE 7 - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDPS0 0 -#define WDPS1 1 -#define WDPS2 2 -#define WDE 3 -#define WDCE 4 - -/* Reserved [0x61..0x62] */ - -#define PRR0 _SFR_MEM8(0x63) -#define PRLFR 0 -#define PRT1 1 -#define PRT2 2 -#define PRT3 3 -#define PRTM 4 -#define PRCU 5 -#define PRDS 6 -#define PRVM 7 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5790n.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define T3CR2 _SFR_IO8(0x0C) +#define T3GRES 0 +#define T3C2TM 1 +#define T3C2RM 2 + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 +#define T3CO2F 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +#define EECR2 _SFR_IO8(0x25) +#define EEBRE 0 +#define EEPAGE 1 + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5791.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define T3CR2 _SFR_IO8(0x0C) +#define T3GRES 0 +#define T3C2TM 1 +#define T3C2RM 2 + +#define TPCR _SFR_IO8(0x0D) +#define TPMA 0 +#define TPMOD 1 +#define TPMS0 2 +#define TPMS1 3 +#define TPMD0 4 +#define TPMD1 5 +#define TPPSD 6 +#define TPD 7 + +#define TPFR _SFR_IO8(0x0E) +#define TPF 0 +#define TPA 1 +#define TPGAP 2 +#define TPPSW 3 + +#define CMCR _SFR_IO8(0x0F) +#define CMM0 0 +#define CMM1 1 +#define SRCD 2 +#define CO32D 3 +#define CCS 4 +#define ECINS 5 +#define CMONEN 6 +#define CMCCE 7 + +#define CMSR _SFR_IO8(0x10) +#define ECF 0 +#define SXF 1 +#define RTCF 2 + +#define T2CR _SFR_IO8(0x11) +#define T2OTM 0 +#define T2CTM 1 +#define T2CRM 2 +#define T2GRM 3 +#define T2TOP 4 +#define T2RES 5 +#define T2TS 6 +#define T2E 7 + +#define T3CR _SFR_IO8(0x12) +#define T3OTM 0 +#define T3CTM 1 +#define T3CRM 2 +#define T3CPRM 3 +#define T3TOP 4 +#define T3RES 5 +#define T3CPTM 6 +#define T3E 7 + +#define AESCR _SFR_IO8(0x13) +#define AESWK 0 +#define AESWD 1 +#define AESIM 2 +#define AESD 3 +#define AESXOR 4 +#define AESRES 5 +#define AESE 7 + +#define AESSR _SFR_IO8(0x14) +#define AESRF 0 +#define AESERF 7 + +#define TMIFR _SFR_IO8(0x15) +#define TMRXF 0 +#define TMTXF 1 +#define TMTCF 2 +#define TMRXS 3 +#define TMTXS 4 + +#define VMSR _SFR_IO8(0x16) +#define VMF 0 + +#define PCIFR _SFR_IO8(0x17) +#define PCIF0 0 +#define PCIF1 1 + +#define LFFR _SFR_IO8(0x18) +#define LFID0F 0 +#define LFID1F 1 +#define LFFEF 2 +#define LFDBF 3 +#define LFRSF 4 +#define LFSDF 5 +#define LFMDF 6 +#define LFCAF 7 + +#define T0IFR _SFR_IO8(0x19) +#define T0F 0 + +#define T1IFR _SFR_IO8(0x1A) +#define T1F 0 + +#define T2IFR _SFR_IO8(0x1B) +#define T2OFF 0 +#define T2COF 1 + +#define T3IFR _SFR_IO8(0x1C) +#define T3OFF 0 +#define T3COF 1 +#define T3ICF 2 +#define T3CO2F 3 + +#define EIFR _SFR_IO8(0x1D) +#define INTF0 0 + +#define GPIOR _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 +#define EELP 6 +#define NVMBSY 7 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define EEPR _SFR_IO8(0x23) +#define EEAP0 0 +#define EEAP1 1 +#define EEAP2 2 +#define EEAP3 3 + +#define EECCR _SFR_IO8(0x24) +#define EEL0 0 +#define EEL1 1 +#define EEL2 2 +#define EEL3 3 + +#define EECR2 _SFR_IO8(0x25) +#define EEBRE 0 +#define EEPAGE 1 + +#define PCICR _SFR_IO8(0x26) +#define PCIE0 0 +#define PCIE1 1 + +#define EIMSK _SFR_IO8(0x27) +#define INT0 0 + +#define TMDR _SFR_IO8(0x28) + +#define AESDR _SFR_IO8(0x29) + +#define AESKR _SFR_IO8(0x2A) +#define AESKR0 0 +#define AESKR1 1 +#define AESKR2 2 +#define AESKR3 3 +#define AESKR4 4 +#define AESKR5 5 +#define AESKR6 6 +#define AESKR7 7 + +#define VMCR _SFR_IO8(0x2B) +#define VMLS0 0 +#define VMLS1 1 +#define VMLS2 2 +#define VMLS3 3 +#define VMIM 4 +#define VMPS 5 +#define BODPD 6 +#define BODLS 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define LFCR0 _SFR_IO8(0x2F) +#define LFCE1 0 +#define LFCE2 1 +#define LFCE3 2 +#define LFBRS 3 +#define LFRBS 4 +#define LFMG 5 +#define LFVC0 6 +#define LFVC1 7 + +#define LFCR1 _SFR_IO8(0x30) +#define LFM0 0 +#define LFM1 1 +#define LFFM0 2 +#define LFFM1 3 +#define LFRMS 4 +#define LFRMSA 5 +#define LFQCE 6 +#define LFRE 7 + +/* Reserved [0x31] */ + +#define LFRDB _SFR_IO8(0x32) + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 +#define TPRF 5 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +#define LFSR _SFR_IO8(0x36) +#define LFES 0 +#define LFSD 1 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +#define T1CR _SFR_IO8(0x38) +#define T1PS0 0 +#define T1PS1 1 +#define T1IE 2 +#define T1CS0 3 +#define T1CS1 4 +#define T1E 7 + +#define T0CR _SFR_IO8(0x39) +#define T0PS0 0 +#define T0PS1 1 +#define T0PS2 2 +#define T0IE 3 +#define T0PR 4 + +/* Reserved [0x3A] */ + +#define CMIMR _SFR_IO8(0x3B) +#define ECIE 0 +#define SXIE 1 +#define RTCIE 2 + +#define CLKPR _SFR_IO8(0x3C) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLTPS0 3 +#define CLTPS1 4 +#define CLTPS2 5 +#define CLKPCE 7 + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDPS0 0 +#define WDPS1 1 +#define WDPS2 2 +#define WDE 3 +#define WDCE 4 + +/* Reserved [0x61..0x62] */ + +#define PRR0 _SFR_MEM8(0x63) +#define PRLFR 0 +#define PRT1 1 +#define PRT2 2 +#define PRT3 3 +#define PRTM 4 +#define PRCU 5 +#define PRDS 6 +#define PRVM 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa5831.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PRR0 _SFR_IO8(0x01) -#define PRSPI 0 -#define PRRXDC 1 -#define PRTXDC 2 -#define PRCRC 3 -#define PRVM 4 -#define PRCO 5 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa5831.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6612c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6612c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6613c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6613c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6614q.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6614q.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6616c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6616c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa6617c.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa6617c.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "ioa664251.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x11] */ - -#define PORTCR _SFR_IO8(0x12) -#define PUDA 0 -#define PUDB 1 -#define BBMA 4 -#define BBMB 5 - -/* Reserved [0x13..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSR1 0 -#define PSR0 1 -#define TSM 7 - -/* Reserved [0x24] */ - -#define TCCR0A _SFR_IO8(0x25) -#define WGM00 0 -#define WGM01 1 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x26) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x27) -#define TCNT00 0 -#define TCNT01 1 -#define TCNT02 2 -#define TCNT03 3 -#define TCNT04 4 -#define TCNT05 5 -#define TCNT06 6 -#define TCNT07 7 - -#define OCR0A _SFR_IO8(0x28) -#define OCR00 0 -#define OCR01 1 -#define OCR02 2 -#define OCR03 3 -#define OCR04 4 -#define OCR05 5 -#define OCR06 6 -#define OCR07 7 - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACIRS 6 -#define ACD 7 - -#define DWDR _SFR_IO8(0x31) -#define DWDR0 0 -#define DWDR1 1 -#define DWDR2 2 -#define DWDR3 3 -#define DWDR4 4 -#define DWDR5 5 -#define DWDR6 6 -#define DWDR7 7 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define SIGRD 5 -#define RWWSB 6 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -#define CLKCSR _SFR_MEM8(0x62) -#define CLKC0 0 -#define CLKC1 1 -#define CLKC2 2 -#define CLKC3 3 -#define CLKRDY 4 -#define CLKCCE 7 - -#define CLKSELR _SFR_MEM8(0x63) -#define CSEL0 0 -#define CSEL1 1 -#define CSEL2 2 -#define CSEL3 3 -#define CSUT0 4 -#define CSUT1 5 -#define COUT 6 - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSI 1 -#define PRTIM0 2 -#define PRTIM1 3 -#define PRSPI 4 -#define PRLIN 5 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa664251.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x11] */ + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define BBMA 4 +#define BBMB 5 + +/* Reserved [0x13..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +/* Reserved [0x24] */ + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa8210.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "ioa8510.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PRR0 _SFR_IO8(0x01) +#define PRSPI 0 +#define PRRXDC 1 +#define PRTXDC 2 +#define PRCRC 3 +#define PRVM 4 +#define PRCO 5 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1189 +46,582 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Extended Z-pointer Register for ELPM/SPM */ -#define RAMPZ _SFR_IO8(0x3B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_RAMPZ { - unsigned int rampz0 : 1; /* Extended Z-Pointer Value */ - unsigned int : 7; -}; - -#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) - -#endif /* __ASSEMBLER__ */ - - /* RAMPZ */ - -#define RAMPZ0 0 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define Res5 6 +#define Res6 7 + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1189 +46,582 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Extended Z-pointer Register for ELPM/SPM */ -#define RAMPZ _SFR_IO8(0x3B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_RAMPZ { - unsigned int rampz0 : 1; /* Extended Z-Pointer Value */ - unsigned int : 7; -}; - -#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) - -#endif /* __ASSEMBLER__ */ - - /* RAMPZ */ - -#define RAMPZ0 0 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define Res5 6 +#define Res6 7 + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom168pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1197 +46,582 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Extended Z-pointer Register for ELPM/SPM */ -#define RAMPZ _SFR_IO8(0x3B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_RAMPZ { - unsigned int rampz : 2; /* Extended Z-Pointer Value */ - unsigned int : 6; -}; - -#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) - -#endif /* __ASSEMBLER__ */ - - /* RAMPZ */ - -#define RAMPZ0 0 -#define RAMPZ1 1 - -/* Extended Indirect Register */ -#define EIND _SFR_IO8(0x3C) - - /* EIND */ - -#define EIND0 0 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define RAMPZ1 1 +#define Res5 7 + +#define EIND _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1197 +46,582 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Extended Z-pointer Register for ELPM/SPM */ -#define RAMPZ _SFR_IO8(0x3B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_RAMPZ { - unsigned int rampz : 2; /* Extended Z-Pointer Value */ - unsigned int : 6; -}; - -#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) - -#endif /* __ASSEMBLER__ */ - - /* RAMPZ */ - -#define RAMPZ0 0 -#define RAMPZ1 1 - -/* Extended Indirect Register */ -#define EIND _SFR_IO8(0x3C) - - /* EIND */ - -#define EIND0 0 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3A] */ + +#define RAMPZ _SFR_IO8(0x3B) +#define RAMPZ0 0 +#define RAMPZ1 1 +#define Res5 7 + +#define EIND _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324a.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom324p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +/* Reserved [0x0C..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR0 _SFR_IO8(0x2C) +#define SPR00 0 +#define SPR10 1 +#define CPHA0 2 +#define CPOL0 3 +#define MSTR0 4 +#define DORD0 5 +#define SPE0 6 +#define SPIE0 7 + +#define SPSR0 _SFR_IO8(0x2D) +#define SPI2X0 0 +#define WCOL0 6 +#define SPIF0 7 + +#define SPDR0 _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRUSART1 4 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom329p.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 + +/* Reserved [0x18..0x1B] */ + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define PCIF0 4 +#define PCIF1 5 +#define PCIF2 6 +#define PCIF3 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define PCIE0 4 +#define PCIE1 5 +#define PCIE2 6 +#define PCIE3 7 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEWE 1 +#define EEMWE 2 +#define EERIE 3 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSR10 0 +#define TSM 7 +#define PSR2 1 + +#define TCCR0A _SFR_IO8(0x24) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM01 3 +#define COM0A0 4 +#define COM0A1 5 +#define WGM00 6 +#define FOC0A 7 + +/* Reserved [0x25] */ + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +/* Reserved [0x28..0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRLCD 4 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom48pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -#define EEARL _SFR_IO8(0x21) - -/* Reserved [0x22] */ - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SELFPRGEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom48pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +#define EEARL _SFR_IO8(0x21) + +/* Reserved [0x22] */ + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom644a.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDA7 7 -#define DDA6 6 -#define DDA5 5 -#define DDA4 4 -#define DDA3 3 -#define DDA2 2 -#define DDA1 1 -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 -// retain PAn macros for backward compatibility -#define PA7 7 -#define PA6 6 -#define PA5 5 -#define PA4 4 -#define PA3 3 -#define PA2 2 -#define PA1 1 -#define PA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDB7 7 -#define DDB6 6 -#define DDB5 5 -#define DDB4 4 -#define DDB3 3 -#define DDB2 2 -#define DDB1 1 -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 -// retain PBn macros for backward compatibility -#define PB7 7 -#define PB6 6 -#define PB5 5 -#define PB4 4 -#define PB3 3 -#define PB2 2 -#define PB1 1 -#define PB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC7 7 -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDC7 7 -#define DDC6 6 -#define DDC5 5 -#define DDC4 4 -#define DDC3 3 -#define DDC2 2 -#define DDC1 1 -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC7 7 -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 -// retain PCn macros for backward compatibility -#define PC7 7 -#define PC6 6 -#define PC5 5 -#define PC4 4 -#define PC3 3 -#define PC2 2 -#define PC1 1 -#define PC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDD7 7 -#define DDD6 6 -#define DDD5 5 -#define DDD4 4 -#define DDD3 3 -#define DDD2 2 -#define DDD1 1 -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 -// retain PDn macros for backward compatibility -#define PD7 7 -#define PD6 6 -#define PD5 5 -#define PD4 4 -#define PD3 3 -#define PD2 2 -#define PD1 1 -#define PD0 0 - -/* Reserved [0x0C..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 -#define PCIF3 3 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 -#define INT2 2 - -#define GPIOR0 _SFR_IO8(0x1E) -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ -#define __EEPROM_REG_LOCATIONS__ 1F2021 -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -#define GPIOR2 _SFR_IO8(0x2B) -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -#define MONDR _SFR_IO8(0x31) -#define OCDR _SFR_IO8(0x31) -#define IDRD 7 -#define OCDR7 7 -#define OCDR6 6 -#define OCDR5 5 -#define OCDR4 4 -#define OCDR3 3 -#define OCDR2 2 -#define OCDR1 1 -#define OCDR0 0 - -/* Reserved [0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define JTRF 4 -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define JTD 7 -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ -#define PRR _SFR_MEM8(0x64) /* for backward compatibility */ -#define PRR0 _SFR_MEM8(0x64) -#define PRADC 0 -#define PRSPI 2 -#define PRTIM1 3 -#define PRUSART0 1 -#define PRUSART1 4 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR0 ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1171 +46,575 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom64hve2.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINA _SFR_IO8(0x00) -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x01) -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x02) -#define PORTA1 1 -#define PORTA0 0 - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -/* Reserved [0x06..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 -#define ICF0 3 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 3 - -/* Reserved [0x17..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define ICS0 3 -#define ICES0 4 -#define ICNC0 5 -#define ICEN0 6 -#define TCW0 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 - -/* Combine TCNT0L and TCNT0H */ -#define TCNT0 _SFR_IO16(0x26) - -#define TCNT0L _SFR_IO8(0x26) -#define TCNT0H _SFR_IO8(0x27) - -#define OCR0A _SFR_IO8(0x28) - -#define OCR0B _SFR_IO8(0x29) - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BODRF 2 -#define WDRF 3 -#define OCDRF 4 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define CKOE 5 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define LBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPCE 7 - -#define WUTCSR _SFR_MEM8(0x62) -#define WUTP0 0 -#define WUTP1 1 -#define WUTP2 2 -#define WUTE 3 -#define WUTR 4 -#define WUTIE 6 -#define WUTIF 7 - -#define WDTCLR _SFR_MEM8(0x63) -#define WDCLE 0 -#define WDCL0 1 -#define WDCL1 2 - -#define PRR0 _SFR_MEM8(0x64) -#define PRTIM0 0 -#define PRTIM1 1 -#define PRSPI 2 -#define PRLIN 3 - -#define __AVR_HAVE_PRR0 ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom64hve2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +/* Reserved [0x06..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 3 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 3 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define ICS0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 + +/* Combine TCNT0L and TCNT0H */ +#define TCNT0 _SFR_IO16(0x26) + +#define TCNT0L _SFR_IO8(0x26) +#define TCNT0H _SFR_IO8(0x27) + +#define OCR0A _SFR_IO8(0x28) + +#define OCR0B _SFR_IO8(0x29) + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BODRF 2 +#define WDRF 3 +#define OCDRF 4 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define CKOE 5 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define LBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPCE 7 + +#define WUTCSR _SFR_MEM8(0x62) +#define WUTP0 0 +#define WUTP1 1 +#define WUTP2 2 +#define WUTE 3 +#define WUTR 4 +#define WUTIE 6 +#define WUTIF 7 + +#define WDTCLR _SFR_MEM8(0x63) +#define WDCLE 0 +#define WDCL0 1 +#define WDCL1 2 + +#define PRR0 _SFR_MEM8(0x64) +#define PRTIM0 0 +#define PRTIM1 1 +#define PRSPI 2 +#define PRLIN 3 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -47,1171 +46,575 @@ # error "Attempt to include more than one file." #endif -#include +/* Registers and associated bit numbers */ -#ifndef __ASSEMBLER__ -# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) -# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) -# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) -#endif /* __ASSEMBLER__ */ - -/* - * USAGE: - * - * simple register assignment: - * TIFR1 = 0x17 - * subregister assignment: - * TIFR1_struct.ocf1a = 1 - * (subregister names are converted to small letters) - */ - - -/* Port A Input Pins Address */ -#define PINA _SFR_IO8(0x00) - - /* PINA */ - -#define PINA0 0 -#define PINA1 1 -#define PINA2 2 -#define PINA3 3 -#define PINA4 4 -#define PINA5 5 -#define PINA6 6 -#define PINA7 7 - -/* Port A Data Direction Register */ -#define DDRA _SFR_IO8(0x01) - - /* DDRA */ - -#define DDA0 0 -#define DDA1 1 -#define DDA2 2 -#define DDA3 3 -#define DDA4 4 -#define DDA5 5 -#define DDA6 6 -#define DDA7 7 - -/* Port A Data Register */ -#define PORTA _SFR_IO8(0x02) - - /* PORTA */ - -#define PORTA0 0 -#define PA0 0 -#define PORTA1 1 -#define PA1 1 -#define PORTA2 2 -#define PA2 2 -#define PORTA3 3 -#define PA3 3 -#define PORTA4 4 -#define PA4 4 -#define PORTA5 5 -#define PA5 5 -#define PORTA6 6 -#define PA6 6 -#define PORTA7 7 -#define PA7 7 - -/* Port B Input Pins Address */ -#define PINB _SFR_IO8(0x03) - - /* PINB */ - -#define PINB0 0 -#define PINB1 1 -#define PINB2 2 -#define PINB3 3 -#define PINB4 4 -#define PINB5 5 -#define PINB6 6 -#define PINB7 7 - -/* Port B Data Direction Register */ -#define DDRB _SFR_IO8(0x04) - - /* DDRB */ - -#define DDB0 0 -#define DDB1 1 -#define DDB2 2 -#define DDB3 3 -#define DDB4 4 -#define DDB5 5 -#define DDB6 6 -#define DDB7 7 - -/* Port B Data Register */ -#define PORTB _SFR_IO8(0x05) - - /* PORTB */ - -#define PORTB0 0 -#define PB0 0 -#define PORTB1 1 -#define PB1 1 -#define PORTB2 2 -#define PB2 2 -#define PORTB3 3 -#define PB3 3 -#define PORTB4 4 -#define PB4 4 -#define PORTB5 5 -#define PB5 5 -#define PORTB6 6 -#define PB6 6 -#define PORTB7 7 -#define PB7 7 - -/* Port C Input Pins Address */ -#define PINC _SFR_IO8(0x06) - - /* PINC */ - -#define PINC0 0 -#define PINC1 1 -#define PINC2 2 -#define PINC3 3 -#define PINC4 4 -#define PINC5 5 -#define PINC6 6 -#define PINC7 7 - -/* Port C Data Direction Register */ -#define DDRC _SFR_IO8(0x07) - - /* DDRC */ - -#define DDC0 0 -#define DDC1 1 -#define DDC2 2 -#define DDC3 3 -#define DDC4 4 -#define DDC5 5 -#define DDC6 6 -#define DDC7 7 - -/* Port C Data Register */ -#define PORTC _SFR_IO8(0x08) - - /* PORTC */ - -#define PORTC0 0 -#define PC0 0 -#define PORTC1 1 -#define PC1 1 -#define PORTC2 2 -#define PC2 2 -#define PORTC3 3 -#define PC3 3 -#define PORTC4 4 -#define PC4 4 -#define PORTC5 5 -#define PC5 5 -#define PORTC6 6 -#define PC6 6 -#define PORTC7 7 -#define PC7 7 - -/* Port D Input Pins Address */ -#define PIND _SFR_IO8(0x09) - - /* PIND */ - -#define PIND0 0 -#define PIND1 1 -#define PIND2 2 -#define PIND3 3 -#define PIND4 4 -#define PIND5 5 -#define PIND6 6 -#define PIND7 7 - -/* Port D Data Direction Register */ -#define DDRD _SFR_IO8(0x0A) - - /* DDRD */ - -#define DDD0 0 -#define DDD1 1 -#define DDD2 2 -#define DDD3 3 -#define DDD4 4 -#define DDD5 5 -#define DDD6 6 -#define DDD7 7 - -/* Port D Data Register */ -#define PORTD _SFR_IO8(0x0B) - - /* PORTD */ - -#define PORTD0 0 -#define PD0 0 -#define PORTD1 1 -#define PD1 1 -#define PORTD2 2 -#define PD2 2 -#define PORTD3 3 -#define PD3 3 -#define PORTD4 4 -#define PD4 4 -#define PORTD5 5 -#define PD5 5 -#define PORTD6 6 -#define PD6 6 -#define PORTD7 7 -#define PD7 7 - -/* Port E Input Pins Address */ -#define PINE _SFR_IO8(0x0C) - - /* PINE */ - -#define PINE0 0 -#define PINE1 1 -#define PINE2 2 -#define PINE3 3 -#define PINE4 4 -#define PINE5 5 -#define PINE6 6 -#define PINE7 7 - -/* Port E Data Direction Register */ -#define DDRE _SFR_IO8(0x0D) - - /* DDRE */ - -#define DDE0 0 -#define DDE1 1 -#define DDE2 2 -#define DDE3 3 -#define DDE4 4 -#define DDE5 5 -#define DDE6 6 -#define DDE7 7 - -/* Port E Data Register */ -#define PORTE _SFR_IO8(0x0E) - - /* PORTE */ - -#define PORTE0 0 -#define PE0 0 -#define PORTE1 1 -#define PE1 1 -#define PORTE2 2 -#define PE2 2 -#define PORTE3 3 -#define PE3 3 -#define PORTE4 4 -#define PE4 4 -#define PORTE5 5 -#define PE5 5 -#define PORTE6 6 -#define PE6 6 -#define PORTE7 7 -#define PE7 7 - -/* Port F Input Pins Address */ -#define PINF _SFR_IO8(0x0F) - - /* PINF */ - -#define PINF0 0 -#define PINF1 1 -#define PINF2 2 -#define PINF3 3 -#define PINF4 4 -#define PINF5 5 -#define PINF6 6 -#define PINF7 7 - -/* Port F Data Direction Register */ -#define DDRF _SFR_IO8(0x10) - - /* DDRF */ - -#define DDF0 0 -#define DDF1 1 -#define DDF2 2 -#define DDF3 3 -#define DDF4 4 -#define DDF5 5 -#define DDF6 6 -#define DDF7 7 - -/* Port F Data Register */ -#define PORTF _SFR_IO8(0x11) - - /* PORTF */ - -#define PORTF0 0 -#define PF0 0 -#define PORTF1 1 -#define PF1 1 -#define PORTF2 2 -#define PF2 2 -#define PORTF3 3 -#define PF3 3 -#define PORTF4 4 -#define PF4 4 -#define PORTF5 5 -#define PF5 5 -#define PORTF6 6 -#define PF6 6 -#define PORTF7 7 -#define PF7 7 - -/* Port G Input Pins Address */ -#define PING _SFR_IO8(0x12) - - /* PING */ - -#define PING0 0 -#define PING1 1 -#define PING2 2 -#define PING3 3 -#define PING4 4 -#define PING5 5 - -/* Port G Data Direction Register */ -#define DDRG _SFR_IO8(0x13) - - /* DDRG */ - -#define DDG0 0 -#define DDG1 1 -#define DDG2 2 -#define DDG3 3 -#define DDG4 4 -#define DDG5 5 - -/* Port G Data Register */ -#define PORTG _SFR_IO8(0x14) - - /* PORTG */ - -#define PORTG0 0 -#define PG0 0 -#define PORTG1 1 -#define PG1 1 -#define PORTG2 2 -#define PG2 2 -#define PORTG3 3 -#define PG3 3 -#define PORTG4 4 -#define PG4 4 -#define PORTG5 5 -#define PG5 5 - -/* Timer/Counter0 Interrupt Flag Register */ -#define TIFR0 _SFR_IO8(0x15) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR0 { - unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ - unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ - unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ - unsigned int : 5; -}; - -#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) - -#endif /* __ASSEMBLER__ */ - - /* TIFR0 */ - -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -/* Timer/Counter1 Interrupt Flag Register */ -#define TIFR1 _SFR_IO8(0x16) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR1 { - unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ - unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ - unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ - unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) - -#endif /* __ASSEMBLER__ */ - - /* TIFR1 */ - -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define OCF1C 3 -#define ICF1 5 - -/* Timer/Counter Interrupt Flag Register */ -#define TIFR2 _SFR_IO8(0x17) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR2 { - unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ - unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ - unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ - unsigned int : 5; -}; - -#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) - -#endif /* __ASSEMBLER__ */ - - /* TIFR2 */ - -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Timer/Counter3 Interrupt Flag Register */ -#define TIFR3 _SFR_IO8(0x18) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR3 { - unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ - unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ - unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ - unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) - -#endif /* __ASSEMBLER__ */ - - /* TIFR3 */ - -#define TOV3 0 -#define OCF3A 1 -#define OCF3B 2 -#define OCF3C 3 -#define ICF3 5 - -/* Timer/Counter4 Interrupt Flag Register */ -#define TIFR4 _SFR_IO8(0x19) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR4 { - unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ - unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ - unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ - unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) - -#endif /* __ASSEMBLER__ */ - - /* TIFR4 */ - -#define TOV4 0 -#define OCF4A 1 -#define OCF4B 2 -#define OCF4C 3 -#define ICF4 5 - -/* Timer/Counter5 Interrupt Flag Register */ -#define TIFR5 _SFR_IO8(0x1A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TIFR5 { - unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ - unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ - unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ - unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ - unsigned int : 1; - unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ - unsigned int : 2; -}; - -#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) - -#endif /* __ASSEMBLER__ */ - - /* TIFR5 */ - -#define TOV5 0 -#define OCF5A 1 -#define OCF5B 2 -#define OCF5C 3 -#define ICF5 5 - -/* Pin Change Interrupt Flag Register */ -#define PCIFR _SFR_IO8(0x1B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PCIFR { - unsigned int pcif : 3; /* Pin Change Interrupt Flags */ - unsigned int : 5; -}; - -#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) - -#endif /* __ASSEMBLER__ */ - - /* PCIFR */ - -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -/* External Interrupt Flag Register */ -#define EIFR _SFR_IO8(0x1C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIFR { - unsigned int intf : 8; /* External Interrupt Flag */ -}; - -#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) - -#endif /* __ASSEMBLER__ */ - - /* EIFR */ - -#define INTF0 0 -#define INTF1 1 -#define INTF2 2 -#define INTF3 3 -#define INTF4 4 -#define INTF5 5 -#define INTF6 6 -#define INTF7 7 - -/* External Interrupt Mask Register */ -#define EIMSK _SFR_IO8(0x1D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EIMSK { - unsigned int intm : 8; /* External Interrupt Request Enable */ -}; - -#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) - -#endif /* __ASSEMBLER__ */ - - /* EIMSK */ - -#define INT0 0 -#define INT1 1 -#define INT2 2 -#define INT3 3 -#define INT4 4 -#define INT5 5 -#define INT6 6 -#define INT7 7 - -/* General Purpose IO Register 0 */ -#define GPIOR0 _SFR_IO8(0x1E) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR0 { - unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ - unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ -}; - -#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR0 */ - -#define GPIOR00 0 -#define GPIOR01 1 -#define GPIOR02 2 -#define GPIOR03 3 -#define GPIOR04 4 -#define GPIOR05 5 -#define GPIOR06 6 -#define GPIOR07 7 - -/* 6-char sequence denoting where to find the EEPROM registers in memory space. - Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM - subroutines. - First two letters: EECR address. - Second two letters: EEDR address. - Last two letters: EEAR address. */ - -#define __EEPROM_REG_LOCATIONS__ 1F2021 - -/* EEPROM Control Register */ -#define EECR _SFR_IO8(0x1F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_EECR { - unsigned int eere : 1; /* EEPROM Read Enable */ - unsigned int eepe : 1; /* EEPROM Programming Enable */ - unsigned int eempe : 1; /* EEPROM Master Write Enable */ - unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ - unsigned int eepm : 2; /* EEPROM Programming Mode */ - unsigned int : 2; -}; - -#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) - -#endif /* __ASSEMBLER__ */ - - /* EECR */ - -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -/* EEPROM Data Register */ -#define EEDR _SFR_IO8(0x20) - - /* EEDR */ - -#define EEDR0 0 -#define EEDR1 1 -#define EEDR2 2 -#define EEDR3 3 -#define EEDR4 4 -#define EEDR5 5 -#define EEDR6 6 -#define EEDR7 7 - -/* EEPROM Address Register Bytes */ -#define EEAR _SFR_IO16(0x21) -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -/* General Timer/Counter Control Register */ -#define GTCCR _SFR_IO8(0x23) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GTCCR { - unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ - unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ - unsigned int : 5; - unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ -}; - -#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) - -#endif /* __ASSEMBLER__ */ - - /* GTCCR */ - -#define PSRSYNC 0 -#define PSR10 0 -#define PSRASY 1 -#define PSR2 1 -#define TSM 7 - -/* Timer/Counter0 Control Register A */ -#define TCCR0A _SFR_IO8(0x24) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0A { - unsigned int wgm0 : 2; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int com0b : 2; /* Compare Match Output B Mode */ - unsigned int com0a : 2; /* Compare Match Output A Mode */ -}; - -#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0A */ - -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Timer/Counter0 Control Register B */ -#define TCCR0B _SFR_IO8(0x25) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_TCCR0B { - unsigned int cs0 : 3; /* Clock Select */ - unsigned int wgm02 : 1; /* Waveform Generation Mode */ - unsigned int : 2; - unsigned int foc0b : 1; /* Force Output Compare B */ - unsigned int foc0a : 1; /* Force Output Compare A */ -}; - -#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) - -#endif /* __ASSEMBLER__ */ - - /* TCCR0B */ - -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -/* Timer/Counter0 Register */ -#define TCNT0 _SFR_IO8(0x26) - - /* TCNT0 */ - -#define TCNT0_0 0 -#define TCNT0_1 1 -#define TCNT0_2 2 -#define TCNT0_3 3 -#define TCNT0_4 4 -#define TCNT0_5 5 -#define TCNT0_6 6 -#define TCNT0_7 7 - -/* Timer/Counter0 Output Compare Register */ -#define OCR0A _SFR_IO8(0x27) - - /* OCR0A */ - -#define OCR0A_0 0 -#define OCR0A_1 1 -#define OCR0A_2 2 -#define OCR0A_3 3 -#define OCR0A_4 4 -#define OCR0A_5 5 -#define OCR0A_6 6 -#define OCR0A_7 7 - -/* Timer/Counter0 Output Compare Register B */ -#define OCR0B _SFR_IO8(0x28) - - /* OCR0B */ - -#define OCR0B_0 0 -#define OCR0B_1 1 -#define OCR0B_2 2 -#define OCR0B_3 3 -#define OCR0B_4 4 -#define OCR0B_5 5 -#define OCR0B_6 6 -#define OCR0B_7 7 - -/* General Purpose IO Register 1 */ -#define GPIOR1 _SFR_IO8(0x2A) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR1 { - unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ -}; - -#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR1 */ - -#define GPIOR10 0 -#define GPIOR11 1 -#define GPIOR12 2 -#define GPIOR13 3 -#define GPIOR14 4 -#define GPIOR15 5 -#define GPIOR16 6 -#define GPIOR17 7 - -/* General Purpose I/O Register 2 */ -#define GPIOR2 _SFR_IO8(0x2B) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_GPIOR2 { - unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ -}; - -#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) - -#endif /* __ASSEMBLER__ */ - - /* GPIOR2 */ - -#define GPIOR20 0 -#define GPIOR21 1 -#define GPIOR22 2 -#define GPIOR23 3 -#define GPIOR24 4 -#define GPIOR25 5 -#define GPIOR26 6 -#define GPIOR27 7 - -/* SPI Control Register */ -#define SPCR _SFR_IO8(0x2C) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPCR { - unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ - unsigned int cpha : 1; /* Clock Phase */ - unsigned int cpol : 1; /* Clock polarity */ - unsigned int mstr : 1; /* Master/Slave Select */ - unsigned int dord : 1; /* Data Order */ - unsigned int spe : 1; /* SPI Enable */ - unsigned int spie : 1; /* SPI Interrupt Enable */ -}; - -#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) - -#endif /* __ASSEMBLER__ */ - - /* SPCR */ - -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -/* SPI Status Register */ -#define SPSR _SFR_IO8(0x2D) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPSR { - unsigned int spi2x : 1; /* Double SPI Speed Bit */ - unsigned int : 5; - unsigned int wcol : 1; /* Write Collision Flag */ - unsigned int spif : 1; /* SPI Interrupt Flag */ -}; - -#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) - -#endif /* __ASSEMBLER__ */ - - /* SPSR */ - -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -/* SPI Data Register */ -#define SPDR _SFR_IO8(0x2E) - - /* SPDR */ - -#define SPDR0 0 -#define SPDR1 1 -#define SPDR2 2 -#define SPDR3 3 -#define SPDR4 4 -#define SPDR5 5 -#define SPDR6 6 -#define SPDR7 7 - -/* Analog Comparator Control And Status Register */ -#define ACSR _SFR_IO8(0x30) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_ACSR { - unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ - unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ - unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ - unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ - unsigned int aco : 1; /* Analog Compare Output */ - unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ - unsigned int acd : 1; /* Analog Comparator Disable */ -}; - -#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) - -#endif /* __ASSEMBLER__ */ - - /* ACSR */ - -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* On-Chip Debug Register */ -#define OCDR _SFR_IO8(0x31) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_OCDR { - unsigned int ocdr : 8; /* On-Chip Debug Register Data */ -}; - -#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) - -#endif /* __ASSEMBLER__ */ - - /* OCDR */ - -#define OCDR0 0 -#define OCDR1 1 -#define OCDR2 2 -#define OCDR3 3 -#define OCDR4 4 -#define OCDR5 5 -#define OCDR6 6 -#define OCDR7 7 -#define IDRD 7 - -/* Sleep Mode Control Register */ -#define SMCR _SFR_IO8(0x33) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SMCR { - unsigned int se : 1; /* Sleep Enable */ - unsigned int sm : 3; /* Sleep Mode Select bits */ - unsigned int : 4; -}; - -#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) - -#endif /* __ASSEMBLER__ */ - - /* SMCR */ - -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -/* MCU Status Register */ -#define MCUSR _SFR_IO8(0x34) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUSR { - unsigned int porf : 1; /* Power-on Reset Flag */ - unsigned int extrf : 1; /* External Reset Flag */ - unsigned int borf : 1; /* Brown-out Reset Flag */ - unsigned int wdrf : 1; /* Watchdog Reset Flag */ - unsigned int jtrf : 1; /* JTAG Reset Flag */ - unsigned int : 3; -}; - -#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) - -#endif /* __ASSEMBLER__ */ - - /* MCUSR */ - -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 -#define JTRF 4 - -/* MCU Control Register */ -#define MCUCR _SFR_IO8(0x35) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_MCUCR { - unsigned int ivce : 1; /* Interrupt Vector Change Enable */ - unsigned int ivsel : 1; /* Interrupt Vector Select */ - unsigned int : 2; - unsigned int pud : 1; /* Pull-up Disable */ - unsigned int : 2; - unsigned int jtd : 1; /* JTAG Interface Disable */ -}; - -#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) - -#endif /* __ASSEMBLER__ */ - - /* MCUCR */ - -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define JTD 7 - -/* Store Program Memory Control Register */ -#define SPMCSR _SFR_IO8(0x37) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SPMCSR { - unsigned int spmen : 1; /* Store Program Memory Enable */ - unsigned int pgers : 1; /* Page Erase */ - unsigned int pgwrt : 1; /* Page Write */ - unsigned int blbset : 1; /* Boot Lock Bit Set */ - unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ - unsigned int sigrd : 1; /* Signature Row Read */ - unsigned int rwwsb : 1; /* Read While Write Section Busy */ - unsigned int spmie : 1; /* SPM Interrupt Enable */ -}; - -#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) - -#endif /* __ASSEMBLER__ */ - - /* SPMCSR */ - -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Stack Pointer */ -#define SP _SFR_IO16(0x3D) -#define SPL _SFR_IO8(0x3D) -#define SPH _SFR_IO8(0x3E) - -/* Status Register */ -#define SREG _SFR_IO8(0x3F) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_SREG { - unsigned int c : 1; /* Carry Flag */ - unsigned int z : 1; /* Zero Flag */ - unsigned int n : 1; /* Negative Flag */ - unsigned int v : 1; /* Two's Complement Overflow Flag */ - unsigned int s : 1; /* Sign Bit */ - unsigned int h : 1; /* Half Carry Flag */ - unsigned int t : 1; /* Bit Copy Storage */ - unsigned int i : 1; /* Global Interrupt Enable */ -}; - -#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) - -#endif /* __ASSEMBLER__ */ - - /* SREG */ - -#define SREG_C 0 -#define SREG_Z 1 -#define SREG_N 2 -#define SREG_V 3 -#define SREG_S 4 -#define SREG_H 5 -#define SREG_T 6 -#define SREG_I 7 - -/* Watchdog Timer Control Register */ -#define WDTCSR _SFR_MEM8(0x60) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_WDTCSR { - unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ - unsigned int wde : 1; /* Watch Dog Enable */ - unsigned int wdce : 1; /* Watchdog Change Enable */ - unsigned int : 1; - unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ - unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ -}; - -#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) - -#endif /* __ASSEMBLER__ */ - - /* WDTCSR */ - -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDE 3 -#define WDCE 4 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -/* Clock Prescale Register */ -#define CLKPR _SFR_MEM8(0x61) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_CLKPR { - unsigned int clkps : 4; /* Clock Prescaler Select Bits */ - unsigned int : 3; - unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ -}; - -#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) - -#endif /* __ASSEMBLER__ */ - - /* CLKPR */ - -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Power Reduction Register 2 */ -#define PRR2 _SFR_MEM8(0x63) - -#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) - -struct __reg_PRR2 { - unsigned int prram : 4; /* Power Reduction SRAMs */ - unsigned int : 4; -}; - -#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) - -#endif /* __ASSEMBLER__ */ - - /* PRR2 */ - -#define PRRAM0 0 -#define PRRAM1 1 -#define PRRAM2 2 -#define PRRAM3 3 +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE7 7 +// Inserted "DDE7" from "DDRE7" due to compatibility +#define DDE7 7 +#define DDRE6 6 +// Inserted "DDE6" from "DDRE6" due to compatibility +#define DDE6 6 +#define DDRE5 5 +// Inserted "DDE5" from "DDRE5" due to compatibility +#define DDE5 5 +#define DDRE4 4 +// Inserted "DDE4" from "DDRE4" due to compatibility +#define DDE4 4 +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE7 7 +#define PORTE6 6 +#define PORTE5 5 +#define PORTE4 4 +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDRF7 7 +// Inserted "DDF7" from "DDRF7" due to compatibility +#define DDF7 7 +#define DDRF6 6 +// Inserted "DDF6" from "DDRF6" due to compatibility +#define DDF6 6 +#define DDRF5 5 +// Inserted "DDF5" from "DDRF5" due to compatibility +#define DDF5 5 +#define DDRF4 4 +// Inserted "DDF4" from "DDRF4" due to compatibility +#define DDF4 4 +#define DDRF3 3 +// Inserted "DDF3" from "DDRF3" due to compatibility +#define DDF3 3 +#define DDRF2 2 +// Inserted "DDF2" from "DDRF2" due to compatibility +#define DDF2 2 +#define DDRF1 1 +// Inserted "DDF1" from "DDRF1" due to compatibility +#define DDF1 1 +#define DDRF0 0 +// Inserted "DDF0" from "DDRF0" due to compatibility +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PORTF7 7 +#define PORTF6 6 +#define PORTF5 5 +#define PORTF4 4 +#define PORTF3 3 +#define PORTF2 2 +#define PORTF1 1 +#define PORTF0 0 + +#define PING _SFR_IO8(0x12) +#define PING7 7 +#define PING6 6 +#define PING5 5 +#define PING4 4 +#define PING3 3 +#define PING2 2 +#define PING1 1 +#define PING0 0 + +#define DDRG _SFR_IO8(0x13) +#define DDRG7 7 +// Inserted "DDG7" from "DDRG7" due to compatibility +#define DDG7 7 +#define DDRG6 6 +// Inserted "DDG6" from "DDRG6" due to compatibility +#define DDG6 6 +#define DDRG5 5 +// Inserted "DDG5" from "DDRG5" due to compatibility +#define DDG5 5 +#define DDRG4 4 +// Inserted "DDG4" from "DDRG4" due to compatibility +#define DDG4 4 +#define DDRG3 3 +// Inserted "DDG3" from "DDRG3" due to compatibility +#define DDG3 3 +#define DDRG2 2 +// Inserted "DDG2" from "DDRG2" due to compatibility +#define DDG2 2 +#define DDRG1 1 +// Inserted "DDG1" from "DDRG1" due to compatibility +#define DDG1 1 +#define DDRG0 0 +// Inserted "DDG0" from "DDRG0" due to compatibility +#define DDG0 0 + +#define PORTG _SFR_IO8(0x14) +#define PORTG7 7 +#define PORTG6 6 +#define PORTG5 5 +#define PORTG4 4 +#define PORTG3 3 +#define PORTG2 2 +#define PORTG1 1 +#define PORTG0 0 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define Res0 3 +#define Res1 4 +#define Res2 5 +#define Res3 6 +#define Res4 7 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define OCF1C 3 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +#define TIFR3 _SFR_IO8(0x18) +#define TOV3 0 +#define OCF3A 1 +#define OCF3B 2 +#define OCF3C 3 +#define ICF3 5 + +#define TIFR4 _SFR_IO8(0x19) +#define TOV4 0 +#define OCF4A 1 +#define OCF4B 2 +#define OCF4C 3 +#define ICF4 5 + +#define TIFR5 _SFR_IO8(0x1A) +#define TOV5 0 +#define OCF5A 1 +#define OCF5B 2 +#define OCF5C 3 +#define ICF5 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 +#define INTF2 2 +#define INTF3 3 +#define INTF4 4 +#define INTF5 5 +#define INTF6 6 +#define INTF7 7 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 +#define INT2 2 +#define INT3 3 +#define INT4 4 +#define INT5 5 +#define INT6 6 +#define INT7 7 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define PSRASY 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define OCDR _SFR_IO8(0x31) +#define OCDR0 0 +#define OCDR1 1 +#define OCDR2 2 +#define OCDR3 3 +#define OCDR4 4 +#define OCDR5 5 +#define OCDR6 6 +#define OCDR7 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62] */ + +#define PRR2 _SFR_MEM8(0x63) +#define PRRAM0 0 +#define PRRAM1 1 +#define PRRAM2 2 +#define PRRAM3 3 #define __AVR_HAVE_PRR2 ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iom88pb.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define PINB _SFR_IO8(0x03) -#define PINB7 7 -#define PINB6 6 -#define PINB5 5 -#define PINB4 4 -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x04) -#define DDRB7 7 -// Inserted "DDB7" from "DDRB7" due to compatibility -#define DDB7 7 -#define DDRB6 6 -// Inserted "DDB6" from "DDRB6" due to compatibility -#define DDB6 6 -#define DDRB5 5 -// Inserted "DDB5" from "DDRB5" due to compatibility -#define DDB5 5 -#define DDRB4 4 -// Inserted "DDB4" from "DDRB4" due to compatibility -#define DDB4 4 -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x05) -#define PORTB7 7 -#define PORTB6 6 -#define PORTB5 5 -#define PORTB4 4 -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINC _SFR_IO8(0x06) -#define PINC6 6 -#define PINC5 5 -#define PINC4 4 -#define PINC3 3 -#define PINC2 2 -#define PINC1 1 -#define PINC0 0 - -#define DDRC _SFR_IO8(0x07) -#define DDRC6 6 -// Inserted "DDC6" from "DDRC6" due to compatibility -#define DDC6 6 -#define DDRC5 5 -// Inserted "DDC5" from "DDRC5" due to compatibility -#define DDC5 5 -#define DDRC4 4 -// Inserted "DDC4" from "DDRC4" due to compatibility -#define DDC4 4 -#define DDRC3 3 -// Inserted "DDC3" from "DDRC3" due to compatibility -#define DDC3 3 -#define DDRC2 2 -// Inserted "DDC2" from "DDRC2" due to compatibility -#define DDC2 2 -#define DDRC1 1 -// Inserted "DDC1" from "DDRC1" due to compatibility -#define DDC1 1 -#define DDRC0 0 -// Inserted "DDC0" from "DDRC0" due to compatibility -#define DDC0 0 - -#define PORTC _SFR_IO8(0x08) -#define PORTC6 6 -#define PORTC5 5 -#define PORTC4 4 -#define PORTC3 3 -#define PORTC2 2 -#define PORTC1 1 -#define PORTC0 0 - -#define PIND _SFR_IO8(0x09) -#define PIND7 7 -#define PIND6 6 -#define PIND5 5 -#define PIND4 4 -#define PIND3 3 -#define PIND2 2 -#define PIND1 1 -#define PIND0 0 - -#define DDRD _SFR_IO8(0x0A) -#define DDRD7 7 -// Inserted "DDD7" from "DDRD7" due to compatibility -#define DDD7 7 -#define DDRD6 6 -// Inserted "DDD6" from "DDRD6" due to compatibility -#define DDD6 6 -#define DDRD5 5 -// Inserted "DDD5" from "DDRD5" due to compatibility -#define DDD5 5 -#define DDRD4 4 -// Inserted "DDD4" from "DDRD4" due to compatibility -#define DDD4 4 -#define DDRD3 3 -// Inserted "DDD3" from "DDRD3" due to compatibility -#define DDD3 3 -#define DDRD2 2 -// Inserted "DDD2" from "DDRD2" due to compatibility -#define DDD2 2 -#define DDRD1 1 -// Inserted "DDD1" from "DDRD1" due to compatibility -#define DDD1 1 -#define DDRD0 0 -// Inserted "DDD0" from "DDRD0" due to compatibility -#define DDD0 0 - -#define PORTD _SFR_IO8(0x0B) -#define PORTD7 7 -#define PORTD6 6 -#define PORTD5 5 -#define PORTD4 4 -#define PORTD3 3 -#define PORTD2 2 -#define PORTD1 1 -#define PORTD0 0 - -#define PINE _SFR_IO8(0x0C) -#define PINE3 3 -#define PINE2 2 -#define PINE1 1 -#define PINE0 0 - -#define DDRE _SFR_IO8(0x0D) -#define DDRE3 3 -// Inserted "DDE3" from "DDRE3" due to compatibility -#define DDE3 3 -#define DDRE2 2 -// Inserted "DDE2" from "DDRE2" due to compatibility -#define DDE2 2 -#define DDRE1 1 -// Inserted "DDE1" from "DDRE1" due to compatibility -#define DDE1 1 -#define DDRE0 0 -// Inserted "DDE0" from "DDRE0" due to compatibility -#define DDE0 0 - -#define PORTE _SFR_IO8(0x0E) -#define PORTE3 3 -#define PORTE2 2 -#define PORTE1 1 -#define PORTE0 0 - -#define ACSRB _SFR_IO8(0x0F) -#define ACOE 0 - -/* Reserved [0x10..0x14] */ - -#define TIFR0 _SFR_IO8(0x15) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIFR1 _SFR_IO8(0x16) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - -/* Reserved [0x18..0x1A] */ - -#define PCIFR _SFR_IO8(0x1B) -#define PCIF0 0 -#define PCIF1 1 -#define PCIF2 2 - -#define EIFR _SFR_IO8(0x1C) -#define INTF0 0 -#define INTF1 1 - -#define EIMSK _SFR_IO8(0x1D) -#define INT0 0 -#define INT1 1 - -#define GPIOR0 _SFR_IO8(0x1E) - -#define EECR _SFR_IO8(0x1F) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x20) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x21) - -#define EEARL _SFR_IO8(0x21) -#define EEARH _SFR_IO8(0x22) - -#define GTCCR _SFR_IO8(0x23) -#define PSRSYNC 0 -#define TSM 7 -#define PSRASY 1 - -#define TCCR0A _SFR_IO8(0x24) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -#define TCCR0B _SFR_IO8(0x25) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define TCNT0 _SFR_IO8(0x26) - -#define OCR0A _SFR_IO8(0x27) - -#define OCR0B _SFR_IO8(0x28) - -/* Reserved [0x29] */ - -#define GPIOR1 _SFR_IO8(0x2A) - -#define GPIOR2 _SFR_IO8(0x2B) - -#define SPCR _SFR_IO8(0x2C) -#define SPR0 0 -#define SPR1 1 -#define CPHA 2 -#define CPOL 3 -#define MSTR 4 -#define DORD 5 -#define SPE 6 -#define SPIE 7 - -#define SPSR _SFR_IO8(0x2D) -#define SPI2X 0 -#define WCOL 6 -#define SPIF 7 - -#define SPDR _SFR_IO8(0x2E) - -/* Reserved [0x2F] */ - -#define ACSR _SFR_IO8(0x30) -#define ACIS0 0 -#define ACIS1 1 -#define ACIC 2 -#define ACIE 3 -#define ACI 4 -#define ACO 5 -#define ACBG 6 -#define ACD 7 - -/* Reserved [0x31..0x32] */ - -#define SMCR _SFR_IO8(0x33) -#define SE 0 -#define SM0 1 -#define SM1 2 -#define SM2 3 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define IVCE 0 -#define IVSEL 1 -#define PUD 4 -#define BODSE 5 -#define BODS 6 - -/* Reserved [0x36] */ - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define BLBSET 3 -#define RWWSRE 4 -#define SIGRD 5 -#define RWWSB 6 -#define SPMIE 7 - -/* Reserved [0x38..0x3C] */ - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define WDTCSR _SFR_MEM8(0x60) -#define WDE 3 -#define WDCE 4 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define CLKPR _SFR_MEM8(0x61) -#define CLKPS0 0 -#define CLKPS1 1 -#define CLKPS2 2 -#define CLKPS3 3 -#define CLKPCE 7 - -/* Reserved [0x62..0x63] */ - -#define PRR _SFR_MEM8(0x64) -#define PRADC 0 -#define PRUSART0 1 -#define PRSPI 2 -#define PRTIM1 3 -#define PRTIM0 5 -#define PRTIM2 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iom88pb.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDRD7 7 +// Inserted "DDD7" from "DDRD7" due to compatibility +#define DDD7 7 +#define DDRD6 6 +// Inserted "DDD6" from "DDRD6" due to compatibility +#define DDD6 6 +#define DDRD5 5 +// Inserted "DDD5" from "DDRD5" due to compatibility +#define DDD5 5 +#define DDRD4 4 +// Inserted "DDD4" from "DDRD4" due to compatibility +#define DDD4 4 +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD7 7 +#define PORTD6 6 +#define PORTD5 5 +#define PORTD4 4 +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDRE3 3 +// Inserted "DDE3" from "DDRE3" due to compatibility +#define DDE3 3 +#define DDRE2 2 +// Inserted "DDE2" from "DDRE2" due to compatibility +#define DDE2 2 +#define DDRE1 1 +// Inserted "DDE1" from "DDRE1" due to compatibility +#define DDE1 1 +#define DDRE0 0 +// Inserted "DDE0" from "DDRE0" due to compatibility +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PORTE3 3 +#define PORTE2 2 +#define PORTE1 1 +#define PORTE0 0 + +#define ACSRB _SFR_IO8(0x0F) +#define ACOE 0 + +/* Reserved [0x10..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIFR2 _SFR_IO8(0x17) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 + +/* Reserved [0x18..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 +#define PSRASY 1 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 +#define SM2 3 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVCE 0 +#define IVSEL 1 +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define BLBSET 3 +#define RWWSRE 4 +#define SIGRD 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDCE 4 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTIM2 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn441.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) - -#define PUEA _SFR_MEM8(0x63) - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn441.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) + +#define PUEA _SFR_MEM8(0x63) + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iotn841.h" -#else -# error "Attempt to include more than one file." -#endif - -/* Registers and associated bit numbers */ - -#define ADCSRB _SFR_IO8(0x04) -#define ADTS0 0 -#define ADTS1 1 -#define ADTS2 2 -#define ADLAR 3 - -#define ADCSRA _SFR_IO8(0x05) -#define ADPS0 0 -#define ADPS1 1 -#define ADPS2 2 -#define ADIE 3 -#define ADIF 4 -#define ADATE 5 -#define ADSC 6 -#define ADEN 7 - -/* Combine ADCL and ADCH */ -#ifndef __ASSEMBLER__ -#define ADC _SFR_IO16(0x06) -#endif -#define ADCW _SFR_IO16(0x06) - -#define ADCL _SFR_IO8(0x06) -#define ADCH _SFR_IO8(0x07) - -#define ADMUXB _SFR_IO8(0x08) -#define GSEL0 0 -#define GSEL1 1 -#define REFS0 5 -#define REFS1 6 -#define REFS2 7 - -#define ADMUXA _SFR_IO8(0x09) -#define MUX0 0 -#define MUX1 1 -#define MUX2 2 -#define MUX3 3 -#define MUX4 4 -#define MUX5 5 - -#define ACSR0A _SFR_IO8(0x0A) -#define ACIS00 0 -#define ACIS01 1 -#define ACIC0 2 -#define ACIE0 3 -#define ACI0 4 -#define ACO0 5 -#define ACPMUX2 6 -#define ACD0 7 - -#define ACSR0B _SFR_IO8(0x0B) -#define ACPMUX0 0 -#define ACPMUX1 1 -#define ACNMUX0 2 -#define ACNMUX1 3 -#define ACOE0 4 -#define HLEV0 6 -#define HSEL0 7 - -#define ACSR1A _SFR_IO8(0x0C) -#define ACIS10 0 -#define ACIS11 1 -#define ACIC1 2 -#define ACIE1 3 -#define ACI1 4 -#define ACO1 5 -#define ACBG1 6 -#define ACD1 7 - -#define ACSR1B _SFR_IO8(0x0D) -#define ACME1 2 -#define ACOE1 4 -#define HLEV1 6 -#define HSEL1 7 - -#define TIFR1 _SFR_IO8(0x0E) -#define TOV1 0 -#define OCF1A 1 -#define OCF1B 2 -#define ICF1 5 - -#define TIMSK1 _SFR_IO8(0x0F) -#define TOIE1 0 -#define OCIE1A 1 -#define OCIE1B 2 -#define ICIE1 5 - -#define TIFR2 _SFR_IO8(0x10) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 -#define ICF2 5 - -#define TIMSK2 _SFR_IO8(0x11) -#define TOIE2 0 -#define OCIE2A 1 -#define OCIE2B 2 -#define ICIE2 5 - -#define PCMSK0 _SFR_IO8(0x12) -#define PCINT0 0 -#define PCINT1 1 -#define PCINT2 2 -#define PCINT3 3 -#define PCINT4 4 -#define PCINT5 5 -#define PCINT6 6 -#define PCINT7 7 - -#define GPIOR0 _SFR_IO8(0x13) - -#define GPIOR1 _SFR_IO8(0x14) - -#define GPIOR2 _SFR_IO8(0x15) - -#define PINB _SFR_IO8(0x16) -#define PINB3 3 -#define PINB2 2 -#define PINB1 1 -#define PINB0 0 - -#define DDRB _SFR_IO8(0x17) -#define DDRB3 3 -// Inserted "DDB3" from "DDRB3" due to compatibility -#define DDB3 3 -#define DDRB2 2 -// Inserted "DDB2" from "DDRB2" due to compatibility -#define DDB2 2 -#define DDRB1 1 -// Inserted "DDB1" from "DDRB1" due to compatibility -#define DDB1 1 -#define DDRB0 0 -// Inserted "DDB0" from "DDRB0" due to compatibility -#define DDB0 0 - -#define PORTB _SFR_IO8(0x18) -#define PORTB3 3 -#define PORTB2 2 -#define PORTB1 1 -#define PORTB0 0 - -#define PINA _SFR_IO8(0x19) -#define PINA7 7 -#define PINA6 6 -#define PINA5 5 -#define PINA4 4 -#define PINA3 3 -#define PINA2 2 -#define PINA1 1 -#define PINA0 0 - -#define DDRA _SFR_IO8(0x1A) -#define DDRA7 7 -// Inserted "DDA7" from "DDRA7" due to compatibility -#define DDA7 7 -#define DDRA6 6 -// Inserted "DDA6" from "DDRA6" due to compatibility -#define DDA6 6 -#define DDRA5 5 -// Inserted "DDA5" from "DDRA5" due to compatibility -#define DDA5 5 -#define DDRA4 4 -// Inserted "DDA4" from "DDRA4" due to compatibility -#define DDA4 4 -#define DDRA3 3 -// Inserted "DDA3" from "DDRA3" due to compatibility -#define DDA3 3 -#define DDRA2 2 -// Inserted "DDA2" from "DDRA2" due to compatibility -#define DDA2 2 -#define DDRA1 1 -// Inserted "DDA1" from "DDRA1" due to compatibility -#define DDA1 1 -#define DDRA0 0 -// Inserted "DDA0" from "DDRA0" due to compatibility -#define DDA0 0 - -#define PORTA _SFR_IO8(0x1B) -#define PORTA7 7 -#define PORTA6 6 -#define PORTA5 5 -#define PORTA4 4 -#define PORTA3 3 -#define PORTA2 2 -#define PORTA1 1 -#define PORTA0 0 - -#define EECR _SFR_IO8(0x1C) -#define EERE 0 -#define EEPE 1 -#define EEMPE 2 -#define EERIE 3 -#define EEPM0 4 -#define EEPM1 5 - -#define EEDR _SFR_IO8(0x1D) - -/* Combine EEARL and EEARH */ -#define EEAR _SFR_IO16(0x1E) - -#define EEARL _SFR_IO8(0x1E) -#define EEARH _SFR_IO8(0x1F) - -#define PCMSK1 _SFR_IO8(0x20) -#define PCINT8 0 -#define PCINT9 1 -#define PCINT10 2 -#define PCINT11 3 - -#define WDTCSR _SFR_IO8(0x21) -#define WDE 3 -#define WDP0 0 -#define WDP1 1 -#define WDP2 2 -#define WDP3 5 -#define WDIE 6 -#define WDIF 7 - -#define TCCR1C _SFR_IO8(0x22) -#define FOC1B 6 -#define FOC1A 7 - -#define GTCCR _SFR_IO8(0x23) -#define PSR 0 -#define TSM 7 - -/* Combine ICR1L and ICR1H */ -#define ICR1 _SFR_IO16(0x24) - -#define ICR1L _SFR_IO8(0x24) -#define ICR1H _SFR_IO8(0x25) - -/* Reserved [0x26..0x27] */ - -/* Combine OCR1BL and OCR1BH */ -#define OCR1B _SFR_IO16(0x28) - -#define OCR1BL _SFR_IO8(0x28) -#define OCR1BH _SFR_IO8(0x29) - -/* Combine OCR1AL and OCR1AH */ -#define OCR1A _SFR_IO16(0x2A) - -#define OCR1AL _SFR_IO8(0x2A) -#define OCR1AH _SFR_IO8(0x2B) - -/* Combine TCNT1L and TCNT1H */ -#define TCNT1 _SFR_IO16(0x2C) - -#define TCNT1L _SFR_IO8(0x2C) -#define TCNT1H _SFR_IO8(0x2D) - -#define TCCR1B _SFR_IO8(0x2E) -#define CS10 0 -#define CS11 1 -#define CS12 2 -#define WGM12 3 -#define WGM13 4 -#define ICES1 6 -#define ICNC1 7 - -#define TCCR1A _SFR_IO8(0x2F) -#define WGM10 0 -#define WGM11 1 -#define COM1B0 4 -#define COM1B1 5 -#define COM1A0 6 -#define COM1A1 7 - -#define TCCR0A _SFR_IO8(0x30) -#define WGM00 0 -#define WGM01 1 -#define COM0B0 4 -#define COM0B1 5 -#define COM0A0 6 -#define COM0A1 7 - -/* Reserved [0x31] */ - -#define TCNT0 _SFR_IO8(0x32) - -#define TCCR0B _SFR_IO8(0x33) -#define CS00 0 -#define CS01 1 -#define CS02 2 -#define WGM02 3 -#define FOC0B 6 -#define FOC0A 7 - -#define MCUSR _SFR_IO8(0x34) -#define PORF 0 -#define EXTRF 1 -#define BORF 2 -#define WDRF 3 - -#define MCUCR _SFR_IO8(0x35) -#define ISC00 0 -#define ISC01 1 -#define SM0 3 -#define SM1 4 -#define SE 5 - -#define OCR0A _SFR_IO8(0x36) - -#define SPMCSR _SFR_IO8(0x37) -#define SPMEN 0 -#define PGERS 1 -#define PGWRT 2 -#define RFLB 3 -#define CTPB 4 -#define RSIG 5 - -#define TIFR0 _SFR_IO8(0x38) -#define TOV0 0 -#define OCF0A 1 -#define OCF0B 2 - -#define TIMSK0 _SFR_IO8(0x39) -#define TOIE0 0 -#define OCIE0A 1 -#define OCIE0B 2 - -#define GIFR _SFR_IO8(0x3A) -#define PCIF0 4 -#define PCIF1 5 -#define INTF0 6 - -#define GIMSK _SFR_IO8(0x3B) -#define PCIE0 4 -#define PCIE1 5 -#define INT0 6 - -#define OCR0B _SFR_IO8(0x3C) - -/* SP [0x3D..0x3E] */ - -/* SREG [0x3F] */ - -#define DIDR0 _SFR_MEM8(0x60) -#define ADC0D 0 -#define ADC1D 1 -#define ADC2D 2 -#define ADC3D 3 -#define ADC4D 4 -#define ADC5D 5 -#define ADC6D 6 -#define ADC7D 7 - -#define DIDR1 _SFR_MEM8(0x61) -#define ADC11D 0 -#define ADC10D 1 -#define ADC8D 2 -#define ADC9D 3 - -#define PUEB _SFR_MEM8(0x62) - -#define PUEA _SFR_MEM8(0x63) - -#define PORTCR _SFR_MEM8(0x64) -#define BBMB 1 -#define BBMA 0 - -#define REMAP _SFR_MEM8(0x65) -#define U0MAP 0 -#define SPIMAP 1 - -#define TOCPMCOE _SFR_MEM8(0x66) -#define TOCC0OE 0 -#define TOCC1OE 1 -#define TOCC2OE 2 -#define TOCC3OE 3 -#define TOCC4OE 4 -#define TOCC5OE 5 -#define TOCC6OE 6 -#define TOCC7OE 7 - -#define TOCPMSA0 _SFR_MEM8(0x67) -#define TOCC0S0 0 -#define TOCC0S1 1 -#define TOCC1S0 2 -#define TOCC1S1 3 -#define TOCC2S0 4 -#define TOCC2S1 5 -#define TOCC3S0 6 -#define TOCC3S1 7 - -#define TOCPMSA1 _SFR_MEM8(0x68) -#define TOCC4S0 0 -#define TOCC4S1 1 -#define TOCC5S0 2 -#define TOCC5S1 3 -#define TOCC6S0 4 -#define TOCC6S1 5 -#define TOCC7S0 6 -#define TOCC7S1 7 - -/* Reserved [0x69] */ - -#define PHDE _SFR_MEM8(0x6A) -#define PHDEA0 0 -#define PHDEA1 1 - -/* Reserved [0x6B..0x6F] */ - -#define PRR _SFR_MEM8(0x70) -#define PRADC 0 -#define PRTIM0 1 -#define PRTIM1 2 -#define PRTIM2 3 -#define PRSPI 4 -#define PRUSART0 5 -#define PRUSART1 6 -#define PRTWI 7 - -#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn841.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) + +#define PUEA _SFR_MEM8(0x63) + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -42,12 +40,10 @@ # define _AVR_IOXXX_H_ "iox128a1u.h" #else # error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega128A1U_H_ -#define _AVR_ATxmega128A1U_H_ 1 +#endif +#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED +#define _AVR_ATXMEGA128A1U_H_INCLUDED /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ @@ -67,6 +63,24 @@ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ @@ -77,7 +91,6 @@ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ - /* C Language Only */ #if !defined (__ASSEMBLER__) @@ -156,6 +169,12 @@ } OCD_t; +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + /* CCP signatures */ typedef enum CCP_enum { @@ -180,11 +199,6 @@ register8_t USBCTRL; /* USB Control Register */ } CLK_t; -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ /* Power Reduction */ typedef struct PR_struct @@ -258,6 +272,7 @@ typedef enum CLK_USBSRC_enum { CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ } CLK_USBSRC_t; @@ -284,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -305,7 +319,7 @@ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ + register8_t PLLCTRL; /* PLL Control Register */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; @@ -336,11 +350,19 @@ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; -/* 32 MHz Calibration Reference */ +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ typedef enum OSC_RC32MCREF_enum { OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ } OSC_RC32MCREF_t; @@ -399,9 +421,9 @@ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ @@ -415,9 +437,9 @@ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ @@ -461,6 +483,19 @@ register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; } PMIC_t; @@ -478,6 +513,8 @@ register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ } PORTCFG_t; /* Virtual Port Mapping */ @@ -548,6 +585,44 @@ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + /* -------------------------------------------------------------------------- @@ -584,17 +659,17 @@ /* Cyclic Redundancy Checker */ typedef struct CRC_struct { - register8_t CTRL; /* CRC Control Register */ - register8_t STATUS; /* CRC Status Register */ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ register8_t reserved_0x02; - register8_t DATAIN; /* CRC Data Input */ - register8_t CHECKSUM0; /* CRC Checksum byte 0 */ - register8_t CHECKSUM1; /* CRC Checksum byte 1 */ - register8_t CHECKSUM2; /* CRC Checksum byte 2 */ - register8_t CHECKSUM3; /* CRC Checksum byte 3 */ + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ } CRC_t; -/* CRC Reset */ +/* Reset */ typedef enum CRC_RESET_enum { CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ @@ -602,10 +677,10 @@ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ } CRC_RESET_t; -/* CRC Input Source */ +/* Input Source */ typedef enum CRC_SOURCE_enum { - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ @@ -641,11 +716,6 @@ register8_t reserved_0x0F; } DMA_CH_t; -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ /* DMA Controller */ typedef struct DMA_struct @@ -1038,15 +1108,15 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ @@ -1070,13 +1140,14 @@ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ @@ -1100,36 +1171,36 @@ /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ } NVM_LB_t; @@ -1144,17 +1215,13 @@ { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x7; + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; } ADC_CH_t; -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ /* Analog-to-Digital Converter */ typedef struct ADC_struct @@ -1166,7 +1233,7 @@ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ + register8_t TEMP; /* Temporary Register */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; @@ -1224,14 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -1253,7 +1324,7 @@ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -1265,22 +1336,22 @@ } ADC_RESOLUTION_t; /* Current Limitation Mode */ -typedef enum ADC_CURRENT_enum +typedef enum ADC_CURRLIMIT_enum { - ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ - ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ - ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ - ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ -} ADC_CURRENT_t; + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ } ADC_REFSEL_t; /* Channel sweep selection */ @@ -1314,7 +1385,7 @@ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ } ADC_EVACT_t; /* Interupt mode */ @@ -1370,7 +1441,7 @@ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ + register8_t reserved_0x04; register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; @@ -1424,38 +1495,6 @@ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - /* -------------------------------------------------------------------------- @@ -1556,7 +1595,7 @@ /* -------------------------------------------------------------------------- -RTC - Real-Time Clounter +RTC - Real-Time Counter -------------------------------------------------------------------------- */ @@ -1622,11 +1661,6 @@ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ /* External Bus Interface */ typedef struct EBI_struct @@ -1652,28 +1686,28 @@ } EBI_t; /* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum +typedef enum EBI_CS_ASPACE_enum { - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; + EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASPACE_t; -/* */ +/* SRAM Wait State Selection */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1681,7 +1715,7 @@ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; @@ -1743,7 +1777,7 @@ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; -/* */ +/* SDRAM Load Mode to Active delay */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ @@ -1752,7 +1786,7 @@ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; -/* */ +/* SDRAM Row Cycle Delay */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ @@ -1760,12 +1794,12 @@ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; -/* */ +/* SDRAM Row to Precharge Delay */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1773,12 +1807,12 @@ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; -/* */ +/* SDRAM Write Recovery Delay */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ @@ -1787,7 +1821,7 @@ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; -/* */ +/* SDRAM Exit Self Refresh to Active Delay */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ @@ -1795,12 +1829,12 @@ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; -/* */ +/* SDRAM Row to Column Delay */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1808,7 +1842,7 @@ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; @@ -1832,11 +1866,6 @@ register8_t DATA; /* Data Register */ } TWI_MASTER_t; -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ /* */ typedef struct TWI_SLAVE_struct @@ -1849,11 +1878,6 @@ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ /* Two-Wire Interface */ typedef struct TWI_struct @@ -1916,10 +1940,19 @@ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + /* -------------------------------------------------------------------------- -USB - USB Module +USB - USB -------------------------------------------------------------------------- */ @@ -1928,66 +1961,13 @@ { register8_t STATUS; /* Endpoint Status */ register8_t CTRL; /* Endpoint Control */ - register8_t CNTL; /* USB Endpoint Counter Low Byte */ - register8_t CNTH; /* USB Endpoint Counter High Byte */ - register8_t DATAPTRL; /* Data Pointer Low Byte */ - register8_t DATAPTRH; /* Data Pointer High Byte */ - register8_t AUXDATAL; /* Auxiliary Data Low Byte */ - register8_t AUXDATAH; /* Auxiliary Data High Byte */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ } USB_EP_t; -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ -/* USB Endpoint table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* USB Endpoint 0 Output */ - USB_EP_t EP0IN; /* USB Endpoint 0 Input */ - USB_EP_t EP1OUT; /* USB Endpoint 1 Output */ - USB_EP_t EP1IN; /* USB Endpoint 1 Input */ - USB_EP_t EP2OUT; /* USB Endpoint 2 Output */ - USB_EP_t EP2IN; /* USB Endpoint 2 Input */ - USB_EP_t EP3OUT; /* USB Endpoint 3 Output */ - USB_EP_t EP3IN; /* USB Endpoint 3 Input */ - USB_EP_t EP4OUT; /* USB Endpoint 4 Output */ - USB_EP_t EP4IN; /* USB Endpoint 4 Input */ - USB_EP_t EP5OUT; /* USB Endpoint 5 Output */ - USB_EP_t EP5IN; /* USB Endpoint 5 Input */ - USB_EP_t EP6OUT; /* USB Endpoint 6 Output */ - USB_EP_t EP6IN; /* USB Endpoint 6 Input */ - USB_EP_t EP7OUT; /* USB Endpoint 7 Output */ - USB_EP_t EP7IN; /* USB Endpoint 7 Input */ - USB_EP_t EP8OUT; /* USB Endpoint 8 Output */ - USB_EP_t EP8IN; /* USB Endpoint 8 Input */ - USB_EP_t EP9OUT; /* USB Endpoint 9 Output */ - USB_EP_t EP9IN; /* USB Endpoint 9 Input */ - USB_EP_t EP10OUT; /* USB Endpoint 10 Output */ - USB_EP_t EP10IN; /* USB Endpoint 10 Input */ - USB_EP_t EP11OUT; /* USB Endpoint 11 Output */ - USB_EP_t EP11IN; /* USB Endpoint 11 Input */ - USB_EP_t EP12OUT; /* USB Endpoint 12 Output */ - USB_EP_t EP12IN; /* USB Endpoint 12 Input */ - USB_EP_t EP13OUT; /* USB Endpoint 13 Output */ - USB_EP_t EP13IN; /* USB Endpoint 13 Input */ - USB_EP_t EP14OUT; /* USB Endpoint 14 Output */ - USB_EP_t EP14IN; /* USB Endpoint 14 Input */ - USB_EP_t EP15OUT; /* USB Endpoint 15 Output */ - USB_EP_t EP15IN; /* USB Endpoint 15 Input */ - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ - -/* USB Module */ +/* Universal Serial Bus */ typedef struct USB_struct { register8_t CTRLA; /* Control Register A */ @@ -2051,6 +2031,71 @@ register8_t CAL1; /* Calibration Byte 1 */ } USB_t; + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + /* USB Endpoint Type */ typedef enum USB_EP_TYPE_enum { @@ -2060,27 +2105,18 @@ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ } USB_EP_TYPE_t; -/* USB Endpoint Buffer Size */ -typedef enum USB_EP_SIZE_enum -{ - USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_SIZE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum { - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} USB_INTLVL_t; + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; /* @@ -2224,11 +2260,6 @@ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct @@ -2314,12 +2345,24 @@ { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + /* Event Action */ typedef enum TC_EVACT_enum { @@ -2412,6 +2455,165 @@ /* -------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- AWEX - Timer/Counter Advanced Waveform Extension -------------------------------------------------------------------------- */ @@ -2424,7 +2626,7 @@ register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; + register8_t STATUSSET; /* Status Set Register */ register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ @@ -2613,97 +2815,318 @@ /* -------------------------------------------------------------------------- -PRESC - Prescaler +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits -------------------------------------------------------------------------- */ -/* Prescaler */ -typedef struct PRESC_struct +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct { - register8_t PRESCALER; /* Control Register */ -} PRESC_t; + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; /* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ -#define USB_EP_TABLE (*(USB_EP_TABLE_t *) ) /* Universal Serial Bus Module */ -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define RST (*(RST_t *) 0x0078) /* Reset */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ -#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ -#define PORTK (*(PORT_t *) 0x0720) /* Port K */ -#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ +#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ +#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ +#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ #endif /* !defined (__ASSEMBLER__) */ @@ -2711,266 +3134,6 @@ /* ========== Flattened fully qualified IO register names ========== */ -/* USB_EP_TABLE - Universal Serial Bus Module */ -#define USB_EP_TABLE_EP0OUT_STATUS _SFR_MEM8(0x0000) -#define USB_EP_TABLE_EP0OUT_CTRL _SFR_MEM8(0x0001) -#define USB_EP_TABLE_EP0OUT_CNTL _SFR_MEM8(0x0002) -#define USB_EP_TABLE_EP0OUT_CNTH _SFR_MEM8(0x0003) -#define USB_EP_TABLE_EP0OUT_DATAPTRL _SFR_MEM8(0x0004) -#define USB_EP_TABLE_EP0OUT_DATAPTRH _SFR_MEM8(0x0005) -#define USB_EP_TABLE_EP0OUT_AUXDATAL _SFR_MEM8(0x0006) -#define USB_EP_TABLE_EP0OUT_AUXDATAH _SFR_MEM8(0x0007) -#define USB_EP_TABLE_EP0IN_STATUS _SFR_MEM8(0x0008) -#define USB_EP_TABLE_EP0IN_CTRL _SFR_MEM8(0x0009) -#define USB_EP_TABLE_EP0IN_CNTL _SFR_MEM8(0x000A) -#define USB_EP_TABLE_EP0IN_CNTH _SFR_MEM8(0x000B) -#define USB_EP_TABLE_EP0IN_DATAPTRL _SFR_MEM8(0x000C) -#define USB_EP_TABLE_EP0IN_DATAPTRH _SFR_MEM8(0x000D) -#define USB_EP_TABLE_EP0IN_AUXDATAL _SFR_MEM8(0x000E) -#define USB_EP_TABLE_EP0IN_AUXDATAH _SFR_MEM8(0x000F) -#define USB_EP_TABLE_EP1OUT_STATUS _SFR_MEM8(0x0010) -#define USB_EP_TABLE_EP1OUT_CTRL _SFR_MEM8(0x0011) -#define USB_EP_TABLE_EP1OUT_CNTL _SFR_MEM8(0x0012) -#define USB_EP_TABLE_EP1OUT_CNTH _SFR_MEM8(0x0013) -#define USB_EP_TABLE_EP1OUT_DATAPTRL _SFR_MEM8(0x0014) -#define USB_EP_TABLE_EP1OUT_DATAPTRH _SFR_MEM8(0x0015) -#define USB_EP_TABLE_EP1OUT_AUXDATAL _SFR_MEM8(0x0016) -#define USB_EP_TABLE_EP1OUT_AUXDATAH _SFR_MEM8(0x0017) -#define USB_EP_TABLE_EP1IN_STATUS _SFR_MEM8(0x0018) -#define USB_EP_TABLE_EP1IN_CTRL _SFR_MEM8(0x0019) -#define USB_EP_TABLE_EP1IN_CNTL _SFR_MEM8(0x001A) -#define USB_EP_TABLE_EP1IN_CNTH _SFR_MEM8(0x001B) -#define USB_EP_TABLE_EP1IN_DATAPTRL _SFR_MEM8(0x001C) -#define USB_EP_TABLE_EP1IN_DATAPTRH _SFR_MEM8(0x001D) -#define USB_EP_TABLE_EP1IN_AUXDATAL _SFR_MEM8(0x001E) -#define USB_EP_TABLE_EP1IN_AUXDATAH _SFR_MEM8(0x001F) -#define USB_EP_TABLE_EP2OUT_STATUS _SFR_MEM8(0x0020) -#define USB_EP_TABLE_EP2OUT_CTRL _SFR_MEM8(0x0021) -#define USB_EP_TABLE_EP2OUT_CNTL _SFR_MEM8(0x0022) -#define USB_EP_TABLE_EP2OUT_CNTH _SFR_MEM8(0x0023) -#define USB_EP_TABLE_EP2OUT_DATAPTRL _SFR_MEM8(0x0024) -#define USB_EP_TABLE_EP2OUT_DATAPTRH _SFR_MEM8(0x0025) -#define USB_EP_TABLE_EP2OUT_AUXDATAL _SFR_MEM8(0x0026) -#define USB_EP_TABLE_EP2OUT_AUXDATAH _SFR_MEM8(0x0027) -#define USB_EP_TABLE_EP2IN_STATUS _SFR_MEM8(0x0028) -#define USB_EP_TABLE_EP2IN_CTRL _SFR_MEM8(0x0029) -#define USB_EP_TABLE_EP2IN_CNTL _SFR_MEM8(0x002A) -#define USB_EP_TABLE_EP2IN_CNTH _SFR_MEM8(0x002B) -#define USB_EP_TABLE_EP2IN_DATAPTRL _SFR_MEM8(0x002C) -#define USB_EP_TABLE_EP2IN_DATAPTRH _SFR_MEM8(0x002D) -#define USB_EP_TABLE_EP2IN_AUXDATAL _SFR_MEM8(0x002E) -#define USB_EP_TABLE_EP2IN_AUXDATAH _SFR_MEM8(0x002F) -#define USB_EP_TABLE_EP3OUT_STATUS _SFR_MEM8(0x0030) -#define USB_EP_TABLE_EP3OUT_CTRL _SFR_MEM8(0x0031) -#define USB_EP_TABLE_EP3OUT_CNTL _SFR_MEM8(0x0032) -#define USB_EP_TABLE_EP3OUT_CNTH _SFR_MEM8(0x0033) -#define USB_EP_TABLE_EP3OUT_DATAPTRL _SFR_MEM8(0x0034) -#define USB_EP_TABLE_EP3OUT_DATAPTRH _SFR_MEM8(0x0035) -#define USB_EP_TABLE_EP3OUT_AUXDATAL _SFR_MEM8(0x0036) -#define USB_EP_TABLE_EP3OUT_AUXDATAH _SFR_MEM8(0x0037) -#define USB_EP_TABLE_EP3IN_STATUS _SFR_MEM8(0x0038) -#define USB_EP_TABLE_EP3IN_CTRL _SFR_MEM8(0x0039) -#define USB_EP_TABLE_EP3IN_CNTL _SFR_MEM8(0x003A) -#define USB_EP_TABLE_EP3IN_CNTH _SFR_MEM8(0x003B) -#define USB_EP_TABLE_EP3IN_DATAPTRL _SFR_MEM8(0x003C) -#define USB_EP_TABLE_EP3IN_DATAPTRH _SFR_MEM8(0x003D) -#define USB_EP_TABLE_EP3IN_AUXDATAL _SFR_MEM8(0x003E) -#define USB_EP_TABLE_EP3IN_AUXDATAH _SFR_MEM8(0x003F) -#define USB_EP_TABLE_EP4OUT_STATUS _SFR_MEM8(0x0040) -#define USB_EP_TABLE_EP4OUT_CTRL _SFR_MEM8(0x0041) -#define USB_EP_TABLE_EP4OUT_CNTL _SFR_MEM8(0x0042) -#define USB_EP_TABLE_EP4OUT_CNTH _SFR_MEM8(0x0043) -#define USB_EP_TABLE_EP4OUT_DATAPTRL _SFR_MEM8(0x0044) -#define USB_EP_TABLE_EP4OUT_DATAPTRH _SFR_MEM8(0x0045) -#define USB_EP_TABLE_EP4OUT_AUXDATAL _SFR_MEM8(0x0046) -#define USB_EP_TABLE_EP4OUT_AUXDATAH _SFR_MEM8(0x0047) -#define USB_EP_TABLE_EP4IN_STATUS _SFR_MEM8(0x0048) -#define USB_EP_TABLE_EP4IN_CTRL _SFR_MEM8(0x0049) -#define USB_EP_TABLE_EP4IN_CNTL _SFR_MEM8(0x004A) -#define USB_EP_TABLE_EP4IN_CNTH _SFR_MEM8(0x004B) -#define USB_EP_TABLE_EP4IN_DATAPTRL _SFR_MEM8(0x004C) -#define USB_EP_TABLE_EP4IN_DATAPTRH _SFR_MEM8(0x004D) -#define USB_EP_TABLE_EP4IN_AUXDATAL _SFR_MEM8(0x004E) -#define USB_EP_TABLE_EP4IN_AUXDATAH _SFR_MEM8(0x004F) -#define USB_EP_TABLE_EP5OUT_STATUS _SFR_MEM8(0x0050) -#define USB_EP_TABLE_EP5OUT_CTRL _SFR_MEM8(0x0051) -#define USB_EP_TABLE_EP5OUT_CNTL _SFR_MEM8(0x0052) -#define USB_EP_TABLE_EP5OUT_CNTH _SFR_MEM8(0x0053) -#define USB_EP_TABLE_EP5OUT_DATAPTRL _SFR_MEM8(0x0054) -#define USB_EP_TABLE_EP5OUT_DATAPTRH _SFR_MEM8(0x0055) -#define USB_EP_TABLE_EP5OUT_AUXDATAL _SFR_MEM8(0x0056) -#define USB_EP_TABLE_EP5OUT_AUXDATAH _SFR_MEM8(0x0057) -#define USB_EP_TABLE_EP5IN_STATUS _SFR_MEM8(0x0058) -#define USB_EP_TABLE_EP5IN_CTRL _SFR_MEM8(0x0059) -#define USB_EP_TABLE_EP5IN_CNTL _SFR_MEM8(0x005A) -#define USB_EP_TABLE_EP5IN_CNTH _SFR_MEM8(0x005B) -#define USB_EP_TABLE_EP5IN_DATAPTRL _SFR_MEM8(0x005C) -#define USB_EP_TABLE_EP5IN_DATAPTRH _SFR_MEM8(0x005D) -#define USB_EP_TABLE_EP5IN_AUXDATAL _SFR_MEM8(0x005E) -#define USB_EP_TABLE_EP5IN_AUXDATAH _SFR_MEM8(0x005F) -#define USB_EP_TABLE_EP6OUT_STATUS _SFR_MEM8(0x0060) -#define USB_EP_TABLE_EP6OUT_CTRL _SFR_MEM8(0x0061) -#define USB_EP_TABLE_EP6OUT_CNTL _SFR_MEM8(0x0062) -#define USB_EP_TABLE_EP6OUT_CNTH _SFR_MEM8(0x0063) -#define USB_EP_TABLE_EP6OUT_DATAPTRL _SFR_MEM8(0x0064) -#define USB_EP_TABLE_EP6OUT_DATAPTRH _SFR_MEM8(0x0065) -#define USB_EP_TABLE_EP6OUT_AUXDATAL _SFR_MEM8(0x0066) -#define USB_EP_TABLE_EP6OUT_AUXDATAH _SFR_MEM8(0x0067) -#define USB_EP_TABLE_EP6IN_STATUS _SFR_MEM8(0x0068) -#define USB_EP_TABLE_EP6IN_CTRL _SFR_MEM8(0x0069) -#define USB_EP_TABLE_EP6IN_CNTL _SFR_MEM8(0x006A) -#define USB_EP_TABLE_EP6IN_CNTH _SFR_MEM8(0x006B) -#define USB_EP_TABLE_EP6IN_DATAPTRL _SFR_MEM8(0x006C) -#define USB_EP_TABLE_EP6IN_DATAPTRH _SFR_MEM8(0x006D) -#define USB_EP_TABLE_EP6IN_AUXDATAL _SFR_MEM8(0x006E) -#define USB_EP_TABLE_EP6IN_AUXDATAH _SFR_MEM8(0x006F) -#define USB_EP_TABLE_EP7OUT_STATUS _SFR_MEM8(0x0070) -#define USB_EP_TABLE_EP7OUT_CTRL _SFR_MEM8(0x0071) -#define USB_EP_TABLE_EP7OUT_CNTL _SFR_MEM8(0x0072) -#define USB_EP_TABLE_EP7OUT_CNTH _SFR_MEM8(0x0073) -#define USB_EP_TABLE_EP7OUT_DATAPTRL _SFR_MEM8(0x0074) -#define USB_EP_TABLE_EP7OUT_DATAPTRH _SFR_MEM8(0x0075) -#define USB_EP_TABLE_EP7OUT_AUXDATAL _SFR_MEM8(0x0076) -#define USB_EP_TABLE_EP7OUT_AUXDATAH _SFR_MEM8(0x0077) -#define USB_EP_TABLE_EP7IN_STATUS _SFR_MEM8(0x0078) -#define USB_EP_TABLE_EP7IN_CTRL _SFR_MEM8(0x0079) -#define USB_EP_TABLE_EP7IN_CNTL _SFR_MEM8(0x007A) -#define USB_EP_TABLE_EP7IN_CNTH _SFR_MEM8(0x007B) -#define USB_EP_TABLE_EP7IN_DATAPTRL _SFR_MEM8(0x007C) -#define USB_EP_TABLE_EP7IN_DATAPTRH _SFR_MEM8(0x007D) -#define USB_EP_TABLE_EP7IN_AUXDATAL _SFR_MEM8(0x007E) -#define USB_EP_TABLE_EP7IN_AUXDATAH _SFR_MEM8(0x007F) -#define USB_EP_TABLE_EP8OUT_STATUS _SFR_MEM8(0x0080) -#define USB_EP_TABLE_EP8OUT_CTRL _SFR_MEM8(0x0081) -#define USB_EP_TABLE_EP8OUT_CNTL _SFR_MEM8(0x0082) -#define USB_EP_TABLE_EP8OUT_CNTH _SFR_MEM8(0x0083) -#define USB_EP_TABLE_EP8OUT_DATAPTRL _SFR_MEM8(0x0084) -#define USB_EP_TABLE_EP8OUT_DATAPTRH _SFR_MEM8(0x0085) -#define USB_EP_TABLE_EP8OUT_AUXDATAL _SFR_MEM8(0x0086) -#define USB_EP_TABLE_EP8OUT_AUXDATAH _SFR_MEM8(0x0087) -#define USB_EP_TABLE_EP8IN_STATUS _SFR_MEM8(0x0088) -#define USB_EP_TABLE_EP8IN_CTRL _SFR_MEM8(0x0089) -#define USB_EP_TABLE_EP8IN_CNTL _SFR_MEM8(0x008A) -#define USB_EP_TABLE_EP8IN_CNTH _SFR_MEM8(0x008B) -#define USB_EP_TABLE_EP8IN_DATAPTRL _SFR_MEM8(0x008C) -#define USB_EP_TABLE_EP8IN_DATAPTRH _SFR_MEM8(0x008D) -#define USB_EP_TABLE_EP8IN_AUXDATAL _SFR_MEM8(0x008E) -#define USB_EP_TABLE_EP8IN_AUXDATAH _SFR_MEM8(0x008F) -#define USB_EP_TABLE_EP9OUT_STATUS _SFR_MEM8(0x0090) -#define USB_EP_TABLE_EP9OUT_CTRL _SFR_MEM8(0x0091) -#define USB_EP_TABLE_EP9OUT_CNTL _SFR_MEM8(0x0092) -#define USB_EP_TABLE_EP9OUT_CNTH _SFR_MEM8(0x0093) -#define USB_EP_TABLE_EP9OUT_DATAPTRL _SFR_MEM8(0x0094) -#define USB_EP_TABLE_EP9OUT_DATAPTRH _SFR_MEM8(0x0095) -#define USB_EP_TABLE_EP9OUT_AUXDATAL _SFR_MEM8(0x0096) -#define USB_EP_TABLE_EP9OUT_AUXDATAH _SFR_MEM8(0x0097) -#define USB_EP_TABLE_EP9IN_STATUS _SFR_MEM8(0x0098) -#define USB_EP_TABLE_EP9IN_CTRL _SFR_MEM8(0x0099) -#define USB_EP_TABLE_EP9IN_CNTL _SFR_MEM8(0x009A) -#define USB_EP_TABLE_EP9IN_CNTH _SFR_MEM8(0x009B) -#define USB_EP_TABLE_EP9IN_DATAPTRL _SFR_MEM8(0x009C) -#define USB_EP_TABLE_EP9IN_DATAPTRH _SFR_MEM8(0x009D) -#define USB_EP_TABLE_EP9IN_AUXDATAL _SFR_MEM8(0x009E) -#define USB_EP_TABLE_EP9IN_AUXDATAH _SFR_MEM8(0x009F) -#define USB_EP_TABLE_EP10OUT_STATUS _SFR_MEM8(0x00A0) -#define USB_EP_TABLE_EP10OUT_CTRL _SFR_MEM8(0x00A1) -#define USB_EP_TABLE_EP10OUT_CNTL _SFR_MEM8(0x00A2) -#define USB_EP_TABLE_EP10OUT_CNTH _SFR_MEM8(0x00A3) -#define USB_EP_TABLE_EP10OUT_DATAPTRL _SFR_MEM8(0x00A4) -#define USB_EP_TABLE_EP10OUT_DATAPTRH _SFR_MEM8(0x00A5) -#define USB_EP_TABLE_EP10OUT_AUXDATAL _SFR_MEM8(0x00A6) -#define USB_EP_TABLE_EP10OUT_AUXDATAH _SFR_MEM8(0x00A7) -#define USB_EP_TABLE_EP10IN_STATUS _SFR_MEM8(0x00A8) -#define USB_EP_TABLE_EP10IN_CTRL _SFR_MEM8(0x00A9) -#define USB_EP_TABLE_EP10IN_CNTL _SFR_MEM8(0x00AA) -#define USB_EP_TABLE_EP10IN_CNTH _SFR_MEM8(0x00AB) -#define USB_EP_TABLE_EP10IN_DATAPTRL _SFR_MEM8(0x00AC) -#define USB_EP_TABLE_EP10IN_DATAPTRH _SFR_MEM8(0x00AD) -#define USB_EP_TABLE_EP10IN_AUXDATAL _SFR_MEM8(0x00AE) -#define USB_EP_TABLE_EP10IN_AUXDATAH _SFR_MEM8(0x00AF) -#define USB_EP_TABLE_EP11OUT_STATUS _SFR_MEM8(0x00B0) -#define USB_EP_TABLE_EP11OUT_CTRL _SFR_MEM8(0x00B1) -#define USB_EP_TABLE_EP11OUT_CNTL _SFR_MEM8(0x00B2) -#define USB_EP_TABLE_EP11OUT_CNTH _SFR_MEM8(0x00B3) -#define USB_EP_TABLE_EP11OUT_DATAPTRL _SFR_MEM8(0x00B4) -#define USB_EP_TABLE_EP11OUT_DATAPTRH _SFR_MEM8(0x00B5) -#define USB_EP_TABLE_EP11OUT_AUXDATAL _SFR_MEM8(0x00B6) -#define USB_EP_TABLE_EP11OUT_AUXDATAH _SFR_MEM8(0x00B7) -#define USB_EP_TABLE_EP11IN_STATUS _SFR_MEM8(0x00B8) -#define USB_EP_TABLE_EP11IN_CTRL _SFR_MEM8(0x00B9) -#define USB_EP_TABLE_EP11IN_CNTL _SFR_MEM8(0x00BA) -#define USB_EP_TABLE_EP11IN_CNTH _SFR_MEM8(0x00BB) -#define USB_EP_TABLE_EP11IN_DATAPTRL _SFR_MEM8(0x00BC) -#define USB_EP_TABLE_EP11IN_DATAPTRH _SFR_MEM8(0x00BD) -#define USB_EP_TABLE_EP11IN_AUXDATAL _SFR_MEM8(0x00BE) -#define USB_EP_TABLE_EP11IN_AUXDATAH _SFR_MEM8(0x00BF) -#define USB_EP_TABLE_EP12OUT_STATUS _SFR_MEM8(0x00C0) -#define USB_EP_TABLE_EP12OUT_CTRL _SFR_MEM8(0x00C1) -#define USB_EP_TABLE_EP12OUT_CNTL _SFR_MEM8(0x00C2) -#define USB_EP_TABLE_EP12OUT_CNTH _SFR_MEM8(0x00C3) -#define USB_EP_TABLE_EP12OUT_DATAPTRL _SFR_MEM8(0x00C4) -#define USB_EP_TABLE_EP12OUT_DATAPTRH _SFR_MEM8(0x00C5) -#define USB_EP_TABLE_EP12OUT_AUXDATAL _SFR_MEM8(0x00C6) -#define USB_EP_TABLE_EP12OUT_AUXDATAH _SFR_MEM8(0x00C7) -#define USB_EP_TABLE_EP12IN_STATUS _SFR_MEM8(0x00C8) -#define USB_EP_TABLE_EP12IN_CTRL _SFR_MEM8(0x00C9) -#define USB_EP_TABLE_EP12IN_CNTL _SFR_MEM8(0x00CA) -#define USB_EP_TABLE_EP12IN_CNTH _SFR_MEM8(0x00CB) -#define USB_EP_TABLE_EP12IN_DATAPTRL _SFR_MEM8(0x00CC) -#define USB_EP_TABLE_EP12IN_DATAPTRH _SFR_MEM8(0x00CD) -#define USB_EP_TABLE_EP12IN_AUXDATAL _SFR_MEM8(0x00CE) -#define USB_EP_TABLE_EP12IN_AUXDATAH _SFR_MEM8(0x00CF) -#define USB_EP_TABLE_EP13OUT_STATUS _SFR_MEM8(0x00D0) -#define USB_EP_TABLE_EP13OUT_CTRL _SFR_MEM8(0x00D1) -#define USB_EP_TABLE_EP13OUT_CNTL _SFR_MEM8(0x00D2) -#define USB_EP_TABLE_EP13OUT_CNTH _SFR_MEM8(0x00D3) -#define USB_EP_TABLE_EP13OUT_DATAPTRL _SFR_MEM8(0x00D4) -#define USB_EP_TABLE_EP13OUT_DATAPTRH _SFR_MEM8(0x00D5) -#define USB_EP_TABLE_EP13OUT_AUXDATAL _SFR_MEM8(0x00D6) -#define USB_EP_TABLE_EP13OUT_AUXDATAH _SFR_MEM8(0x00D7) -#define USB_EP_TABLE_EP13IN_STATUS _SFR_MEM8(0x00D8) -#define USB_EP_TABLE_EP13IN_CTRL _SFR_MEM8(0x00D9) -#define USB_EP_TABLE_EP13IN_CNTL _SFR_MEM8(0x00DA) -#define USB_EP_TABLE_EP13IN_CNTH _SFR_MEM8(0x00DB) -#define USB_EP_TABLE_EP13IN_DATAPTRL _SFR_MEM8(0x00DC) -#define USB_EP_TABLE_EP13IN_DATAPTRH _SFR_MEM8(0x00DD) -#define USB_EP_TABLE_EP13IN_AUXDATAL _SFR_MEM8(0x00DE) -#define USB_EP_TABLE_EP13IN_AUXDATAH _SFR_MEM8(0x00DF) -#define USB_EP_TABLE_EP14OUT_STATUS _SFR_MEM8(0x00E0) -#define USB_EP_TABLE_EP14OUT_CTRL _SFR_MEM8(0x00E1) -#define USB_EP_TABLE_EP14OUT_CNTL _SFR_MEM8(0x00E2) -#define USB_EP_TABLE_EP14OUT_CNTH _SFR_MEM8(0x00E3) -#define USB_EP_TABLE_EP14OUT_DATAPTRL _SFR_MEM8(0x00E4) -#define USB_EP_TABLE_EP14OUT_DATAPTRH _SFR_MEM8(0x00E5) -#define USB_EP_TABLE_EP14OUT_AUXDATAL _SFR_MEM8(0x00E6) -#define USB_EP_TABLE_EP14OUT_AUXDATAH _SFR_MEM8(0x00E7) -#define USB_EP_TABLE_EP14IN_STATUS _SFR_MEM8(0x00E8) -#define USB_EP_TABLE_EP14IN_CTRL _SFR_MEM8(0x00E9) -#define USB_EP_TABLE_EP14IN_CNTL _SFR_MEM8(0x00EA) -#define USB_EP_TABLE_EP14IN_CNTH _SFR_MEM8(0x00EB) -#define USB_EP_TABLE_EP14IN_DATAPTRL _SFR_MEM8(0x00EC) -#define USB_EP_TABLE_EP14IN_DATAPTRH _SFR_MEM8(0x00ED) -#define USB_EP_TABLE_EP14IN_AUXDATAL _SFR_MEM8(0x00EE) -#define USB_EP_TABLE_EP14IN_AUXDATAH _SFR_MEM8(0x00EF) -#define USB_EP_TABLE_EP15OUT_STATUS _SFR_MEM8(0x00F0) -#define USB_EP_TABLE_EP15OUT_CTRL _SFR_MEM8(0x00F1) -#define USB_EP_TABLE_EP15OUT_CNTL _SFR_MEM8(0x00F2) -#define USB_EP_TABLE_EP15OUT_CNTH _SFR_MEM8(0x00F3) -#define USB_EP_TABLE_EP15OUT_DATAPTRL _SFR_MEM8(0x00F4) -#define USB_EP_TABLE_EP15OUT_DATAPTRH _SFR_MEM8(0x00F5) -#define USB_EP_TABLE_EP15OUT_AUXDATAL _SFR_MEM8(0x00F6) -#define USB_EP_TABLE_EP15OUT_AUXDATAH _SFR_MEM8(0x00F7) -#define USB_EP_TABLE_EP15IN_STATUS _SFR_MEM8(0x00F8) -#define USB_EP_TABLE_EP15IN_CTRL _SFR_MEM8(0x00F9) -#define USB_EP_TABLE_EP15IN_CNTL _SFR_MEM8(0x00FA) -#define USB_EP_TABLE_EP15IN_CNTH _SFR_MEM8(0x00FB) -#define USB_EP_TABLE_EP15IN_DATAPTRL _SFR_MEM8(0x00FC) -#define USB_EP_TABLE_EP15IN_DATAPTRH _SFR_MEM8(0x00FD) -#define USB_EP_TABLE_EP15IN_AUXDATAL _SFR_MEM8(0x00FE) -#define USB_EP_TABLE_EP15IN_AUXDATAH _SFR_MEM8(0x00FF) -#define USB_EP_TABLE_FRAMENUML _SFR_MEM8(0x0110) -#define USB_EP_TABLE_FRAMENUMH _SFR_MEM8(0x0111) - /* GPIO - General Purpose IO Registers */ #define GPIO_GPIOR0 _SFR_MEM8(0x0000) #define GPIO_GPIOR1 _SFR_MEM8(0x0001) @@ -2989,25 +3152,89 @@ #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) -/* VPORT0 - Virtual Port 0 */ +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -/* VPORT1 - Virtual Port 1 */ +/* VPORT - Virtual Port */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -/* VPORT2 - Virtual Port 2 */ +/* VPORT - Virtual Port */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -/* VPORT3 - Virtual Port 3 */ +/* VPORT - Virtual Port */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) @@ -3017,7 +3244,7 @@ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) -/* CPU - CPU Registers */ +/* CPU - CPU registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) @@ -3038,16 +3265,16 @@ /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) -/* OSC - Oscillator Control */ +/* OSC - Oscillator */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x005F) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +/* DFLL - DFLL */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) @@ -3055,7 +3282,7 @@ #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +/* DFLL - DFLL */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) @@ -3072,7 +3299,7 @@ #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) -/* RST - Reset Controller */ +/* RST - Reset */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) @@ -3092,25 +3319,27 @@ #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) -/* PMIC - Programmable Interrupt Controller */ +/* PMIC - Programmable Multi-level Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) -/* PORTCFG - Port Configuration */ +/* PORTCFG - I/O port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -/* AES - AES Crypto Module */ +/* AES - AES Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) -/* CRC - CRC Module */ +/* CRC - Cyclic Redundancy Checker */ #define CRC_CTRL _SFR_MEM8(0x00D0) #define CRC_STATUS _SFR_MEM8(0x00D1) #define CRC_DATAIN _SFR_MEM8(0x00D3) @@ -3193,7 +3422,7 @@ #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) -/* NVM - Non Volatile Memory Controller */ +/* NVM - Non-volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) @@ -3207,7 +3436,7 @@ #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) -/* ADCA - Analog to Digital Converter A */ +/* ADC - Analog-to-Digital Converter */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) @@ -3226,23 +3455,27 @@ #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -/* ADCB - Analog to Digital Converter B */ +/* ADC - Analog-to-Digital Converter */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) @@ -3261,28 +3494,31 @@ #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -/* DACA - Digital to Analog Converter A */ +/* DAC - Digital-to-Analog Converter */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) @@ -3291,12 +3527,11 @@ #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) -/* DACB - Digital to Analog Converter B */ +/* DAC - Digital-to-Analog Converter */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) @@ -3305,7 +3540,7 @@ #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) -/* ACA - Analog Comparator A */ +/* AC - Analog Comparator */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) @@ -3315,7 +3550,7 @@ #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) -/* ACB - Analog Comparator B */ +/* AC - Analog Comparator */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) @@ -3355,7 +3590,7 @@ #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) -/* TWIC - Two-Wire Interface C */ +/* TWI - Two-Wire Interface */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) @@ -3371,7 +3606,7 @@ #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -/* TWID - Two-Wire Interface D */ +/* TWI - Two-Wire Interface */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) @@ -3387,7 +3622,7 @@ #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) -/* TWIE - Two-Wire Interface E */ +/* TWI - Two-Wire Interface */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) @@ -3403,7 +3638,7 @@ #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -/* TWIF - Two-Wire Interface F */ +/* TWI - Two-Wire Interface */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) @@ -3419,7 +3654,7 @@ #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) -/* USB - Universal Serial Bus Module */ +/* USB - Universal Serial Bus */ #define USB_CTRLA _SFR_MEM8(0x04C0) #define USB_CTRLB _SFR_MEM8(0x04C1) #define USB_STATUS _SFR_MEM8(0x04C2) @@ -3436,7 +3671,7 @@ #define USB_CAL0 _SFR_MEM8(0x04FA) #define USB_CAL1 _SFR_MEM8(0x04FB) -/* PORTA - Port A */ +/* PORT - I/O Ports */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) @@ -3450,6 +3685,7 @@ #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) @@ -3459,7 +3695,7 @@ #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -/* PORTB - Port B */ +/* PORT - I/O Ports */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) @@ -3473,6 +3709,7 @@ #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) @@ -3482,7 +3719,7 @@ #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -/* PORTC - Port C */ +/* PORT - I/O Ports */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) @@ -3496,6 +3733,7 @@ #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) @@ -3505,7 +3743,7 @@ #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -/* PORTD - Port D */ +/* PORT - I/O Ports */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) @@ -3519,6 +3757,7 @@ #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) @@ -3528,7 +3767,7 @@ #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -/* PORTE - Port E */ +/* PORT - I/O Ports */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) @@ -3542,6 +3781,7 @@ #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) @@ -3551,7 +3791,7 @@ #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -/* PORTF - Port F */ +/* PORT - I/O Ports */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) @@ -3565,6 +3805,7 @@ #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) @@ -3574,7 +3815,7 @@ #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -/* PORTH - Port H */ +/* PORT - I/O Ports */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) @@ -3588,6 +3829,7 @@ #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_REMAP _SFR_MEM8(0x06EE) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) @@ -3597,7 +3839,7 @@ #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) -/* PORTJ - Port J */ +/* PORT - I/O Ports */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) @@ -3611,6 +3853,7 @@ #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_REMAP _SFR_MEM8(0x070E) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) @@ -3620,7 +3863,7 @@ #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) -/* PORTK - Port K */ +/* PORT - I/O Ports */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) @@ -3634,6 +3877,7 @@ #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_REMAP _SFR_MEM8(0x072E) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) @@ -3643,7 +3887,7 @@ #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) -/* PORTQ - Port Q */ +/* PORT - I/O Ports */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) @@ -3657,6 +3901,7 @@ #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_REMAP _SFR_MEM8(0x07CE) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) @@ -3666,7 +3911,7 @@ #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) -/* PORTR - Port R */ +/* PORT - I/O Ports */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) @@ -3680,6 +3925,7 @@ #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) @@ -3689,7 +3935,7 @@ #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -/* TCC0 - Timer/Counter C0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) @@ -3715,7 +3961,29 @@ #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) -/* TCC1 - Timer/Counter C1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) @@ -3737,11 +4005,12 @@ #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) -/* AWEXC - Advanced Waveform Extension C */ +/* AWEX - Advanced Waveform Extension */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) @@ -3750,10 +4019,10 @@ #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -/* HIRESC - High-Resolution Extension C */ +/* HIRES - High-Resolution Extension */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) @@ -3762,7 +4031,7 @@ #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) @@ -3771,7 +4040,7 @@ #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -/* SPIC - Serial Peripheral Interface C */ +/* SPI - Serial Peripheral Interface */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) @@ -3782,7 +4051,7 @@ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -/* TCD0 - Timer/Counter D0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) @@ -3808,7 +4077,29 @@ #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) -/* TCD1 - Timer/Counter D1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) @@ -3830,10 +4121,10 @@ #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) -/* HIRESD - High-Resolution Extension D */ +/* HIRES - High-Resolution Extension */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) @@ -3842,7 +4133,7 @@ #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) @@ -3851,13 +4142,13 @@ #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -/* SPID - Serial Peripheral Interface D */ +/* SPI - Serial Peripheral Interface */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) -/* TCE0 - Timer/Counter E0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) @@ -3883,7 +4174,29 @@ #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -/* TCE1 - Timer/Counter E1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) @@ -3905,11 +4218,12 @@ #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -/* AWEXE - Advanced Waveform Extension E */ +/* AWEX - Advanced Waveform Extension */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) @@ -3918,10 +4232,10 @@ #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -/* HIRESE - High-Resolution Extension E */ +/* HIRES - High-Resolution Extension */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) @@ -3930,7 +4244,7 @@ #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) @@ -3939,13 +4253,13 @@ #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -/* SPIE - Serial Peripheral Interface E */ +/* SPI - Serial Peripheral Interface */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) -/* TCF0 - Timer/Counter F0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) @@ -3971,7 +4285,29 @@ #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -/* TCF1 - Timer/Counter F1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) @@ -3993,10 +4329,10 @@ #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) -/* HIRESF - High-Resolution Extension F */ +/* HIRES - High-Resolution Extension */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) @@ -4005,7 +4341,7 @@ #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) @@ -4014,7 +4350,7 @@ #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) -/* SPIF - Serial Peripheral Interface F */ +/* SPI - Serial Peripheral Interface */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) @@ -4032,12 +4368,30 @@ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - /* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ @@ -4060,7 +4414,6 @@ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ @@ -4086,7 +4439,6 @@ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ - /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ @@ -4098,7 +4450,6 @@ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ @@ -4120,12 +4471,10 @@ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ @@ -4139,7 +4488,6 @@ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - /* CLK.USBCTRL bit masks and bit positions */ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ @@ -4157,9 +4505,8 @@ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ - +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_USB_bm 0x40 /* USB bit mask. */ @@ -4180,7 +4527,6 @@ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ - /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ @@ -4191,17 +4537,15 @@ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - /* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ @@ -4225,75 +4569,71 @@ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - /* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ @@ -4309,7 +4649,6 @@ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ @@ -4327,7 +4666,6 @@ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ @@ -4344,7 +4682,6 @@ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ @@ -4356,6 +4693,9 @@ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ @@ -4367,7 +4707,6 @@ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ @@ -4381,7 +4720,6 @@ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ @@ -4390,6 +4728,9 @@ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ @@ -4403,25 +4744,22 @@ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - /* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ @@ -4440,7 +4778,6 @@ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ @@ -4457,7 +4794,6 @@ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ @@ -4481,12 +4817,10 @@ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ - /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ @@ -4506,7 +4840,6 @@ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ - /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ @@ -4525,33 +4858,29 @@ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - /* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ - +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ @@ -4560,15 +4889,19 @@ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - /* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ @@ -4583,6 +4916,25 @@ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ @@ -4600,7 +4952,6 @@ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - /* PORTCFG - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ @@ -4625,7 +4976,6 @@ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ @@ -4649,7 +4999,6 @@ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ @@ -4678,6 +5027,30 @@ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ @@ -4696,7 +5069,6 @@ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ @@ -4704,7 +5076,6 @@ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ @@ -4713,38 +5084,35 @@ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - /* CRC - Cyclic Redundancy Checker */ /* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ -#define CRC_RESET_gp 6 /* CRC Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ - +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ /* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Enable bit mask. */ -#define CRC_BUSY_bp 0 /* Enable bit position. */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ @@ -4770,7 +5138,6 @@ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ @@ -4798,7 +5165,6 @@ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ @@ -4828,7 +5194,6 @@ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ @@ -4849,7 +5214,6 @@ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ @@ -4871,7 +5235,6 @@ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ @@ -4897,7 +5260,6 @@ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ @@ -4923,7 +5285,6 @@ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ @@ -4945,153 +5306,33 @@ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - /* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ @@ -5116,109 +5357,51 @@ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - /* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ @@ -5239,12 +5422,10 @@ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ - /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ @@ -5258,7 +5439,6 @@ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ @@ -5274,7 +5454,6 @@ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ @@ -5288,7 +5467,6 @@ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ @@ -5318,7 +5496,6 @@ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ @@ -5340,7 +5517,6 @@ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ @@ -5364,13 +5540,14 @@ #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ @@ -5387,11 +5564,32 @@ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ @@ -5419,17 +5617,16 @@ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - /* ADC.CTRLB bit masks and bit positions */ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRENT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ @@ -5444,7 +5641,6 @@ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ @@ -5461,7 +5657,6 @@ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ @@ -5488,7 +5683,6 @@ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ @@ -5499,7 +5693,6 @@ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ @@ -5513,7 +5706,6 @@ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ @@ -5531,7 +5723,6 @@ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ - /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ @@ -5546,7 +5737,6 @@ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ @@ -5558,7 +5748,6 @@ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ @@ -5572,29 +5761,6 @@ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ @@ -5602,7 +5768,6 @@ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - /* DAC.CH0GAINCAL bit masks and bit positions */ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ @@ -5621,7 +5786,6 @@ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - /* DAC.CH0OFFSETCAL bit masks and bit positions */ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ @@ -5640,7 +5804,6 @@ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - /* DAC.CH1GAINCAL bit masks and bit positions */ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ @@ -5659,7 +5822,6 @@ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - /* DAC.CH1OFFSETCAL bit masks and bit positions */ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ @@ -5678,7 +5840,6 @@ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ @@ -5708,35 +5869,21 @@ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ - /* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ @@ -5757,32 +5904,20 @@ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - /* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ /* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ @@ -5799,7 +5934,6 @@ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ @@ -5818,7 +5952,6 @@ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ @@ -5842,8 +5975,7 @@ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Clounter */ +/* RTC - Real-Time Counter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ @@ -5854,12 +5986,10 @@ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ @@ -5875,7 +6005,6 @@ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ @@ -5883,21 +6012,20 @@ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ +#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ +#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ +#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ +#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ +#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ +#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ +#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ +#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ +#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ +#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ +#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ @@ -5906,7 +6034,6 @@ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ @@ -5930,7 +6057,6 @@ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ @@ -5960,7 +6086,6 @@ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ @@ -5975,7 +6100,6 @@ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ @@ -6002,7 +6126,6 @@ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ @@ -6029,7 +6152,6 @@ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ @@ -6048,14 +6170,13 @@ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - /* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ @@ -6063,7 +6184,6 @@ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ @@ -6075,7 +6195,6 @@ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ @@ -6102,7 +6221,6 @@ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ @@ -6129,7 +6247,6 @@ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ @@ -6141,7 +6258,6 @@ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ @@ -6167,7 +6283,6 @@ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ @@ -6189,31 +6304,36 @@ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - /* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB Module */ +/* USB - USB */ /* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ @@ -6230,7 +6350,6 @@ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - /* USB_EP.CTRL bit masks and bit positions */ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ @@ -6248,30 +6367,21 @@ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -/* USB_EP_STALL_bm Predefined. */ -/* USB_EP_STALL_bp Predefined. */ - -#define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - - -/* USB_EP.CNTH bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ - -#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ -#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ -#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ -#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ -#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ -#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ /* USB.CTRLA bit masks and bit positions */ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ @@ -6297,7 +6407,6 @@ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - /* USB.CTRLB bit masks and bit positions */ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ @@ -6311,7 +6420,6 @@ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ #define USB_ATTACH_bp 0 /* Attach bit position. */ - /* USB.STATUS bit masks and bit positions */ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ @@ -6325,7 +6433,6 @@ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - /* USB.ADDR bit masks and bit positions */ #define USB_ADDR_gm 0x7F /* Device Address group mask. */ #define USB_ADDR_gp 0 /* Device Address group position. */ @@ -6344,7 +6451,6 @@ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - /* USB.FIFOWP bit masks and bit positions */ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ @@ -6359,7 +6465,6 @@ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - /* USB.FIFORP bit masks and bit positions */ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ @@ -6374,7 +6479,6 @@ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - /* USB.INTCTRLA bit masks and bit positions */ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ @@ -6395,7 +6499,6 @@ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - /* USB.INTCTRLB bit masks and bit positions */ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ @@ -6403,7 +6506,6 @@ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - /* USB.INTFLAGSACLR bit masks and bit positions */ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ @@ -6429,32 +6531,30 @@ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - /* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF_bm Predefined. */ -/* USB_SOFIF_bp Predefined. */ - -/* USB_SUSPENDIF_bm Predefined. */ -/* USB_SUSPENDIF_bp Predefined. */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ -/* USB_RESUMEIF_bm Predefined. */ -/* USB_RESUMEIF_bp Predefined. */ +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ -/* USB_RSTIF_bm Predefined. */ -/* USB_RSTIF_bp Predefined. */ +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ -/* USB_CRCIF_bm Predefined. */ -/* USB_CRCIF_bp Predefined. */ +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ -/* USB_UNFIF_bm Predefined. */ -/* USB_UNFIF_bp Predefined. */ +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ -/* USB_OVFIF_bm Predefined. */ -/* USB_OVFIF_bp Predefined. */ +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ -/* USB_STALLIF_bm Predefined. */ -/* USB_STALLIF_bp Predefined. */ +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ /* USB.INTFLAGSBCLR bit masks and bit positions */ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ @@ -6463,14 +6563,12 @@ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - /* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF_bm Predefined. */ -/* USB_TRNIF_bp Predefined. */ - -/* USB_SETUPIF_bm Predefined. */ -/* USB_SETUPIF_bp Predefined. */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ /* PORT - I/O Port Configuration */ /* PORT.INTCTRL bit masks and bit positions */ @@ -6488,7 +6586,6 @@ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ @@ -6496,6 +6593,24 @@ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ @@ -6522,188 +6637,96 @@ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - /* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ @@ -6718,7 +6741,6 @@ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ @@ -6741,7 +6763,6 @@ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ @@ -6755,7 +6776,6 @@ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ @@ -6780,11 +6800,13 @@ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - /* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ @@ -6801,7 +6823,6 @@ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ @@ -6831,7 +6852,6 @@ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ @@ -6846,21 +6866,15 @@ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ - /* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ - -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ @@ -6878,23 +6892,21 @@ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - /* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ - -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ @@ -6915,7 +6927,6 @@ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ @@ -6928,7 +6939,6 @@ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ @@ -6945,7 +6955,6 @@ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ @@ -6953,7 +6962,6 @@ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ @@ -6978,12 +6986,10 @@ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ @@ -6999,7 +7005,6 @@ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ @@ -7015,7 +7020,6 @@ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ @@ -7030,21 +7034,15 @@ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ - /* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ @@ -7056,17 +7054,15 @@ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - /* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ @@ -7081,6 +7077,154 @@ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ /* AWEX - Timer/Counter Advanced Waveform Extension */ /* AWEX.CTRL bit masks and bit positions */ @@ -7102,7 +7246,6 @@ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ @@ -7117,7 +7260,6 @@ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ @@ -7128,6 +7270,15 @@ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ /* HIRES - Timer/Counter High-Resolution Extension */ /* HIRES.CTRLA bit masks and bit positions */ @@ -7138,7 +7289,6 @@ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ @@ -7162,7 +7312,6 @@ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ @@ -7185,7 +7334,6 @@ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ @@ -7202,7 +7350,6 @@ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ @@ -7230,7 +7377,6 @@ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ @@ -7251,7 +7397,6 @@ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ @@ -7264,17 +7409,8 @@ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ @@ -7304,7 +7440,6 @@ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ @@ -7313,7 +7448,6 @@ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ @@ -7321,7 +7455,6 @@ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ @@ -7335,34 +7468,152 @@ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* PRESC - Prescaler */ -/* PRESC.PRESCALER bit masks and bit positions */ -#define PRESC_RESET_bm 0x01 /* Reset bit mask. */ -#define PRESC_RESET_bp 0 /* Reset bit position. */ +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 - /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ @@ -7407,17 +7658,51 @@ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ @@ -7497,17 +7782,51 @@ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ @@ -7577,17 +7896,51 @@ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ @@ -7657,17 +8010,51 @@ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ @@ -7710,12 +8097,11 @@ /* ========== Constants ========== */ -#define PROGMEM_START (0x00000) +#define PROGMEM_START (0x0000) #define PROGMEM_SIZE (139264) -#define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -#define APP_SECTION_START (0x00000) +#define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (131072) #define APP_SECTION_PAGE_SIZE (512) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) @@ -7730,14 +8116,8 @@ #define BOOT_SECTION_PAGE_SIZE (512) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) @@ -7755,51 +8135,96 @@ #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -#define EXTERNAL_SRAM_START (0x4000) -#define EXTERNAL_SRAM_SIZE (16760832) -#define EXTERNAL_SRAM_PAGE_SIZE (0) -#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + #define USER_SIGNATURES_START (0x0000) #define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_PAGE_SIZE (512) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +#define FLASHSTART PROGMEM_START #define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define SPM_PAGESIZE 512 #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 0 +#define FUSE_MEMORY_SIZE 6 +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST @@ -7807,7 +8232,6 @@ #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST - /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x97 @@ -7876,5 +8300,6 @@ #define __AVR_HAVE_PRPF_TC1 #define __AVR_HAVE_PRPF_TC0 -#endif /* _AVR_ATxmega128A1U_H_ */ + +#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128a3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128a3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox128a3.h - definitions for ATxmega128A3 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128a3u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128a3u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -7007,14 +7004,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7613,9 +7610,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128a4u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128a4u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6765,14 +6762,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7225,9 +7222,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128b1.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128b1.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -264,13 +262,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -958,7 +955,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2529,7 +2526,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2552,7 +2549,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6386,14 +6383,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6816,9 +6813,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128b3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128b3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -264,13 +262,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -958,7 +955,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2374,7 +2371,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2397,7 +2394,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5916,14 +5913,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6232,9 +6229,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128c3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5699,14 +5696,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6201,9 +6198,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128d3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox128d3.h - definitions for ATxmega128D3 */ @@ -886,12 +886,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox128d4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox128d4.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -259,13 +257,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -772,7 +769,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1310,7 +1307,7 @@ /* -------------------------------------------------------------------------- -PORT - I/O Port Configuration +PORT - Port Configuration -------------------------------------------------------------------------- */ @@ -1331,7 +1328,7 @@ register8_t INT1MASK; /* Port Interrupt 1 Mask */ register8_t INTFLAGS; /* Interrupt Flag Register */ register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ register8_t reserved_0x0F; register8_t PIN0CTRL; /* Pin 0 Control Register */ register8_t PIN1CTRL; /* Pin 1 Control Register */ @@ -2073,7 +2070,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2096,7 +2093,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -4127,7 +4124,14 @@ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -/* PORT - I/O Port Configuration */ +/* PORT - Port Configuration */ +/* VPORT.INTFLAGS bit masks and bit positions */ +/* VPORT_INT1IF Predefined. */ +/* VPORT_INT1IF Predefined. */ + +/* VPORT_INT0IF Predefined. */ +/* VPORT_INT0IF Predefined. */ + /* PORT.INTCTRL bit masks and bit positions */ #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ @@ -4151,11 +4155,11 @@ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ /* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ +#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ +#define PORT_SPI_bp 5 /* SPI Remap bit position. */ -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ +#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ +#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ #define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ #define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ @@ -5088,14 +5092,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -5496,9 +5500,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox16a4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox16a4.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox16a4.h - definitions for ATxmega16A4 */ @@ -1094,12 +1094,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ + BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ + BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ + BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ } BODLVL_t; --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox16a4u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox16a4u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6765,14 +6762,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7225,9 +7222,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox16c4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox16c4.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5601,14 +5598,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6015,9 +6012,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox16d4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox16d4.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox16d4.h - definitions for ATxmega16D4 */ @@ -900,12 +900,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; @@ -1068,14 +1069,14 @@ /* Positive input multiplexer selection */ typedef enum ADC_CH_MUXPOS_enum { - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox16e5.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox16e5.h @@ -0,0 +1,7699 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA16E5_H_INCLUDED +#define _AVR_ATXMEGA16E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (512) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (512) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x45 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */ + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox192a3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox192a3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ /* avr/iox192a3.h - definitions for ATxmega192A3 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox192a3u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox192a3u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1391,18 +1388,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -7007,14 +7004,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7613,9 +7610,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox192c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox192c3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5699,14 +5696,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6201,9 +6198,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox192d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox192d3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox192d3.h - definitions for ATxmega192D3 */ @@ -887,12 +887,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ - BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; /* --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256a3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256a3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox256a3.h - definitions for ATxmega256A3 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256a3b.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256a3b.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox256a3b.h - definitions for ATxmega256A3B */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256a3bu.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256a3bu.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1127,7 +1124,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1310,18 +1307,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2701,7 +2698,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2724,7 +2721,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -7028,14 +7025,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7622,9 +7619,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256a3u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256a3u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -7007,14 +7004,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7613,9 +7610,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256c3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5699,14 +5696,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6201,9 +6198,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox256d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox256d3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ /* avr/iox256d3.h - definitions for ATxmega256D3 */ @@ -882,12 +882,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ - BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; @@ -2994,31 +2995,31 @@ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ /* PR.PRPD bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPF bit masks and bit positions */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32a4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32a4.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox32a4.h - definitions for ATxmega32A4 */ @@ -1093,12 +1093,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ + BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ + BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ + BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ } BODLVL_t; --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32a4u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32a4u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6765,14 +6762,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7225,9 +7222,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32c3.h @@ -1,6264 +1,6264 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32c3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32C3_H_INCLUDED -#define _AVR_ATXMEGA32C3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t USBCTRL; /* USB Control Register */ -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - -/* USB Prescaler Division Factor */ -typedef enum CLK_USBPSDIV_enum -{ - CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ - CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ - CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ - CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ - CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ - CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -} CLK_USBPSDIV_t; - -/* USB Clock Source */ -typedef enum CLK_USBSRC_enum -{ - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ - CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -} CLK_USBSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 2 MHz DFLL Calibration Reference */ -typedef enum OSC_RC2MCREF_enum -{ - OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC2MCREF_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ - OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ - register8_t reserved_0x05; - register8_t EVOUTSEL; /* Event Output Select */ -} PORTCFG_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP02MAP_enum -{ - PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP02MAP_t; - -/* Virtual Port Mapping */ -typedef enum PORTCFG_VP13MAP_enum -{ - PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP13MAP_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - - -/* --------------------------------------------------------------------------- -USB - USB --------------------------------------------------------------------------- -*/ - -/* USB Endpoint */ -typedef struct USB_EP_struct -{ - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ - _WORDREGISTER(CNT); /* USB Endpoint Counter */ - _WORDREGISTER(DATAPTR); /* Data Pointer */ - _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -} USB_EP_t; - - -/* Universal Serial Bus */ -typedef struct USB_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t FIFOWP; /* FIFO Write Pointer Register */ - register8_t FIFORP; /* FIFO Read Pointer Register */ - _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ - register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ - register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ - register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t reserved_0x20; - register8_t reserved_0x21; - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t CAL0; /* Calibration Byte 0 */ - register8_t CAL1; /* Calibration Byte 1 */ -} USB_t; - - -/* USB Endpoint Table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* Endpoint 0 */ - USB_EP_t EP0IN; /* Endpoint 0 */ - USB_EP_t EP1OUT; /* Endpoint 1 */ - USB_EP_t EP1IN; /* Endpoint 1 */ - USB_EP_t EP2OUT; /* Endpoint 2 */ - USB_EP_t EP2IN; /* Endpoint 2 */ - USB_EP_t EP3OUT; /* Endpoint 3 */ - USB_EP_t EP3IN; /* Endpoint 3 */ - USB_EP_t EP4OUT; /* Endpoint 4 */ - USB_EP_t EP4IN; /* Endpoint 4 */ - USB_EP_t EP5OUT; /* Endpoint 5 */ - USB_EP_t EP5IN; /* Endpoint 5 */ - USB_EP_t EP6OUT; /* Endpoint 6 */ - USB_EP_t EP6IN; /* Endpoint 6 */ - USB_EP_t EP7OUT; /* Endpoint 7 */ - USB_EP_t EP7IN; /* Endpoint 7 */ - USB_EP_t EP8OUT; /* Endpoint 8 */ - USB_EP_t EP8IN; /* Endpoint 8 */ - USB_EP_t EP9OUT; /* Endpoint 9 */ - USB_EP_t EP9IN; /* Endpoint 9 */ - USB_EP_t EP10OUT; /* Endpoint 10 */ - USB_EP_t EP10IN; /* Endpoint 10 */ - USB_EP_t EP11OUT; /* Endpoint 11 */ - USB_EP_t EP11IN; /* Endpoint 11 */ - USB_EP_t EP12OUT; /* Endpoint 12 */ - USB_EP_t EP12IN; /* Endpoint 12 */ - USB_EP_t EP13OUT; /* Endpoint 13 */ - USB_EP_t EP13IN; /* Endpoint 13 */ - USB_EP_t EP14OUT; /* Endpoint 14 */ - USB_EP_t EP14IN; /* Endpoint 14 */ - USB_EP_t EP15OUT; /* Endpoint 15 */ - USB_EP_t EP15IN; /* Endpoint 15 */ - register8_t reserved_0x100; - register8_t reserved_0x101; - register8_t reserved_0x102; - register8_t reserved_0x103; - register8_t reserved_0x104; - register8_t reserved_0x105; - register8_t reserved_0x106; - register8_t reserved_0x107; - register8_t reserved_0x108; - register8_t reserved_0x109; - register8_t reserved_0x10A; - register8_t reserved_0x10B; - register8_t reserved_0x10C; - register8_t reserved_0x10D; - register8_t reserved_0x10E; - register8_t reserved_0x10F; - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum -{ - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -} USB_INTLVL_t; - -/* USB Endpoint Type */ -typedef enum USB_EP_TYPE_enum -{ - USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ - USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ - USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -} USB_EP_TYPE_t; - -/* USB Endpoint Buffersize */ -typedef enum USB_EP_BUFSIZE_enum -{ - USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_BUFSIZE_t; - - -/* --------------------------------------------------------------------------- -PORT - I/O Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ - TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Byte Mode */ -typedef enum TC_BYTEM_enum -{ - TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ - TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -} TC_BYTEM_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - - -/* --------------------------------------------------------------------------- -TC2 - 16-bit Timer/Counter type 2 --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter type 2 */ -typedef struct TC2_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t reserved_0x03; - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t reserved_0x08; - register8_t CTRLF; /* Control Register F */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t LCNT; /* Low Byte Count */ - register8_t HCNT; /* High Byte Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t LPER; /* Low Byte Period */ - register8_t HPER; /* High Byte Period */ - register8_t LCMPA; /* Low Byte Compare A */ - register8_t HCMPA; /* High Byte Compare A */ - register8_t LCMPB; /* Low Byte Compare B */ - register8_t HCMPB; /* High Byte Compare B */ - register8_t LCMPC; /* Low Byte Compare C */ - register8_t HCMPC; /* High Byte Compare C */ - register8_t LCMPD; /* Low Byte Compare D */ - register8_t HCMPD; /* High Byte Compare D */ -} TC2_t; - -/* Clock Selection */ -typedef enum TC2_CLKSEL_enum -{ - TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -} TC2_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC2_BYTEM_enum -{ - TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ - TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ - TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -} TC2_BYTEM_t; - -/* High Byte Underflow Interrupt Level */ -typedef enum TC2_HUNFINTLVL_enum -{ - TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_HUNFINTLVL_t; - -/* Low Byte Underflow Interrupt Level */ -typedef enum TC2_LUNFINTLVL_enum -{ - TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LUNFINTLVL_t; - -/* Low Byte Compare D Interrupt Level */ -typedef enum TC2_LCMPDINTLVL_enum -{ - TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC2_LCMPDINTLVL_t; - -/* Low Byte Compare C Interrupt Level */ -typedef enum TC2_LCMPCINTLVL_enum -{ - TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC2_LCMPCINTLVL_t; - -/* Low Byte Compare B Interrupt Level */ -typedef enum TC2_LCMPBINTLVL_enum -{ - TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC2_LCMPBINTLVL_t; - -/* Low Byte Compare A Interrupt Level */ -typedef enum TC2_LCMPAINTLVL_enum -{ - TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC2_LCMPAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMD_enum -{ - TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC2_CMD_t; - -/* Timer/Counter Command */ -typedef enum TC2_CMDEN_enum -{ - TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ - TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ - TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -} TC2_CMDEN_t; - - -/* --------------------------------------------------------------------------- -AWEX - Timer/Counter Advanced Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - - -/* --------------------------------------------------------------------------- -HIRES - Timer/Counter High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* Timer Oscillator pin location */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -} BOD_t; - -/* BOD operation */ -typedef enum BODACT_enum -{ - BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BODACT_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WDP_enum -{ - WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ - WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ - WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ - WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ - WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ - WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ - WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ - WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ - WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ - WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ - WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -} WDP_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -LOCKBIT - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ - register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t USBCAL0; /* USB Calibration Byte 0 */ - register8_t USBCAL1; /* USB Calibration Byte 1 */ - register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ - register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) -#define CLK_USBCTRL _SFR_MEM8(0x0044) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* USB - Universal Serial Bus */ -#define USB_CTRLA _SFR_MEM8(0x04C0) -#define USB_CTRLB _SFR_MEM8(0x04C1) -#define USB_STATUS _SFR_MEM8(0x04C2) -#define USB_ADDR _SFR_MEM8(0x04C3) -#define USB_FIFOWP _SFR_MEM8(0x04C4) -#define USB_FIFORP _SFR_MEM8(0x04C5) -#define USB_EPPTR _SFR_MEM16(0x04C6) -#define USB_INTCTRLA _SFR_MEM8(0x04C8) -#define USB_INTCTRLB _SFR_MEM8(0x04C9) -#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -#define USB_CAL0 _SFR_MEM8(0x04FA) -#define USB_CAL1 _SFR_MEM8(0x04FB) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCC2_CTRLA _SFR_MEM8(0x0800) -#define TCC2_CTRLB _SFR_MEM8(0x0801) -#define TCC2_CTRLC _SFR_MEM8(0x0802) -#define TCC2_CTRLE _SFR_MEM8(0x0804) -#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -#define TCC2_CTRLF _SFR_MEM8(0x0809) -#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -#define TCC2_LCNT _SFR_MEM8(0x0820) -#define TCC2_HCNT _SFR_MEM8(0x0821) -#define TCC2_LPER _SFR_MEM8(0x0826) -#define TCC2_HPER _SFR_MEM8(0x0827) -#define TCC2_LCMPA _SFR_MEM8(0x0828) -#define TCC2_HCMPA _SFR_MEM8(0x0829) -#define TCC2_LCMPB _SFR_MEM8(0x082A) -#define TCC2_HCMPB _SFR_MEM8(0x082B) -#define TCC2_LCMPC _SFR_MEM8(0x082C) -#define TCC2_HCMPC _SFR_MEM8(0x082D) -#define TCC2_LCMPD _SFR_MEM8(0x082E) -#define TCC2_HCMPD _SFR_MEM8(0x082F) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCD2_CTRLA _SFR_MEM8(0x0900) -#define TCD2_CTRLB _SFR_MEM8(0x0901) -#define TCD2_CTRLC _SFR_MEM8(0x0902) -#define TCD2_CTRLE _SFR_MEM8(0x0904) -#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -#define TCD2_CTRLF _SFR_MEM8(0x0909) -#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -#define TCD2_LCNT _SFR_MEM8(0x0920) -#define TCD2_HCNT _SFR_MEM8(0x0921) -#define TCD2_LPER _SFR_MEM8(0x0926) -#define TCD2_HPER _SFR_MEM8(0x0927) -#define TCD2_LCMPA _SFR_MEM8(0x0928) -#define TCD2_HCMPA _SFR_MEM8(0x0929) -#define TCD2_LCMPB _SFR_MEM8(0x092A) -#define TCD2_HCMPB _SFR_MEM8(0x092B) -#define TCD2_LCMPC _SFR_MEM8(0x092C) -#define TCD2_HCMPC _SFR_MEM8(0x092D) -#define TCD2_LCMPD _SFR_MEM8(0x092E) -#define TCD2_HCMPD _SFR_MEM8(0x092F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCE2_CTRLA _SFR_MEM8(0x0A00) -#define TCE2_CTRLB _SFR_MEM8(0x0A01) -#define TCE2_CTRLC _SFR_MEM8(0x0A02) -#define TCE2_CTRLE _SFR_MEM8(0x0A04) -#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE2_CTRLF _SFR_MEM8(0x0A09) -#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE2_LCNT _SFR_MEM8(0x0A20) -#define TCE2_HCNT _SFR_MEM8(0x0A21) -#define TCE2_LPER _SFR_MEM8(0x0A26) -#define TCE2_HPER _SFR_MEM8(0x0A27) -#define TCE2_LCMPA _SFR_MEM8(0x0A28) -#define TCE2_HCMPA _SFR_MEM8(0x0A29) -#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -#define TCE2_HCMPD _SFR_MEM8(0x0A2F) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - -/* TC2 - 16-bit Timer/Counter type 2 */ -#define TCF2_CTRLA _SFR_MEM8(0x0B00) -#define TCF2_CTRLB _SFR_MEM8(0x0B01) -#define TCF2_CTRLC _SFR_MEM8(0x0B02) -#define TCF2_CTRLE _SFR_MEM8(0x0B04) -#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF2_CTRLF _SFR_MEM8(0x0B09) -#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF2_LCNT _SFR_MEM8(0x0B20) -#define TCF2_HCNT _SFR_MEM8(0x0B21) -#define TCF2_LPER _SFR_MEM8(0x0B26) -#define TCF2_HPER _SFR_MEM8(0x0B27) -#define TCF2_LCMPA _SFR_MEM8(0x0B28) -#define TCF2_HCMPA _SFR_MEM8(0x0B29) -#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -#define TCF2_HCMPD _SFR_MEM8(0x0B2F) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* CLK.USBCTRL bit masks and bit positions */ -#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ - -#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_USB_bm 0x40 /* USB bit mask. */ -#define PR_USB_bp 6 /* USB bit position. */ - -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ - -#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -/* PORTCFG.EVOUTSEL bit masks and bit positions */ -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB */ -/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ - -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - -#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - -#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - -#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ - -#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ - -#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ - -#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ - -#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - -/* USB_EP.CTRL bit masks and bit positions */ -#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ - -#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ - -#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ - -#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - -#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - -#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -/* USB_EP.CNT bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - -/* USB.CTRLA bit masks and bit positions */ -#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - -#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -#define USB_SPEED_bp 6 /* Speed Select bit position. */ - -#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - -#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - -#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - -/* USB.CTRLB bit masks and bit positions */ -#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - -#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ - -#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -#define USB_GNACK_bp 1 /* Global NACK bit position. */ - -#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -#define USB_ATTACH_bp 0 /* Attach bit position. */ - -/* USB.STATUS bit masks and bit positions */ -#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ - -#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -#define USB_RESUME_bp 2 /* Resume bit position. */ - -#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ - -#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - -/* USB.ADDR bit masks and bit positions */ -#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -#define USB_ADDR_gp 0 /* Device Address group position. */ -#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - -/* USB.FIFOWP bit masks and bit positions */ -#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - -/* USB.FIFORP bit masks and bit positions */ -#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - -/* USB.INTCTRLA bit masks and bit positions */ -#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ - -#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ - -#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ - -#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ - -#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* USB.INTCTRLB bit masks and bit positions */ -#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ - -#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - -/* USB.INTFLAGSACLR bit masks and bit positions */ -#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ - -#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ - -#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ - -#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ - -#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ - -#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ - -#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ - -#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - -/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF Predefined. */ -/* USB_SOFIF Predefined. */ - -/* USB_SUSPENDIF Predefined. */ -/* USB_SUSPENDIF Predefined. */ - -/* USB_RESUMEIF Predefined. */ -/* USB_RESUMEIF Predefined. */ - -/* USB_RSTIF Predefined. */ -/* USB_RSTIF Predefined. */ - -/* USB_CRCIF Predefined. */ -/* USB_CRCIF Predefined. */ - -/* USB_UNFIF Predefined. */ -/* USB_UNFIF Predefined. */ - -/* USB_OVFIF Predefined. */ -/* USB_OVFIF Predefined. */ - -/* USB_STALLIF Predefined. */ -/* USB_STALLIF Predefined. */ - -/* USB.INTFLAGSBCLR bit masks and bit positions */ -#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ - -#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - -/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF Predefined. */ -/* USB_TRNIF Predefined. */ - -/* USB_SETUPIF Predefined. */ -/* USB_SETUPIF Predefined. */ - -/* PORT - I/O Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -#define PORT_SPI_bp 5 /* SPI bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -#define PORT_USART0_bp 4 /* USART0 bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC2 - 16-bit Timer/Counter type 2 */ -/* TC2.CTRLA bit masks and bit positions */ -#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC2.CTRLB bit masks and bit positions */ -#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ - -#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ - -#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ - -#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ - -#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ - -#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ - -#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ - -#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ - -/* TC2.CTRLC bit masks and bit positions */ -#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ - -#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ - -#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ - -#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ - -#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ - -#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ - -#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ - -#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ - -/* TC2.CTRLE bit masks and bit positions */ -#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - -/* TC2.INTCTRLA bit masks and bit positions */ -#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ - -#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ - -/* TC2.INTCTRLB bit masks and bit positions */ -#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ - -#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ - -#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ - -#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ - -/* TC2.CTRLF bit masks and bit positions */ -#define TC2_CMD_gm 0x0C /* Command group mask. */ -#define TC2_CMD_gp 2 /* Command group position. */ -#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC2_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ - -/* TC2.INTFLAGS bit masks and bit positions */ -#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ - -#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ - -#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ - -#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ - -#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ - -#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - -/* AWEX - Timer/Counter Advanced Waveform Extension */ -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* AWEX.STATUSSET bit masks and bit positions */ -/* AWEX_FDF Predefined. */ -/* AWEX_FDF Predefined. */ - -/* AWEX_DTHSBUFV Predefined. */ -/* AWEX_DTHSBUFV Predefined. */ - -/* AWEX_DTLSBUFV Predefined. */ -/* AWEX_DTLSBUFV Predefined. */ - -/* HIRES - Timer/Counter High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* LOCKBIT - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LUNF_vect_num 14 -#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_HUNF_vect_num 15 -#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPA_vect_num 16 -#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPB_vect_num 17 -#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPC_vect_num 18 -#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC2 interrupt vectors */ -#define TCC2_LCMPD_vect_num 19 -#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LUNF_vect_num 47 -#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_HUNF_vect_num 48 -#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPA_vect_num 49 -#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPB_vect_num 50 -#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPC_vect_num 51 -#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* TCE2 interrupt vectors */ -#define TCE2_LCMPD_vect_num 52 -#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LUNF_vect_num 77 -#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_HUNF_vect_num 78 -#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPA_vect_num 79 -#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPB_vect_num 80 -#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPC_vect_num 81 -#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ - -/* TCD0 interrupt vectors */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* TCD2 interrupt vectors */ -#define TCD2_LCMPD_vect_num 82 -#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LUNF_vect_num 108 -#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_HUNF_vect_num 109 -#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPA_vect_num 110 -#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPB_vect_num 111 -#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPC_vect_num 112 -#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ - -/* TCF0 interrupt vectors */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -/* TCF2 interrupt vectors */ -#define TCF2_LCMPD_vect_num 113 -#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ - -/* USB interrupt vectors */ -#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 126 -#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (64) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x49 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) -#define __AVR_HAVE_PRGEN_USB -#define __AVR_HAVE_PRGEN_AES -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_DMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART1 -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32C3_H_INCLUDED +#define _AVR_ATXMEGA32C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x49 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32c4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32c4.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5601,14 +5598,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6015,9 +6012,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32d3.h @@ -1,5105 +1,5105 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32d3.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32D3_H_INCLUDED -#define _AVR_ATXMEGA32D3_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ - register8_t PRPF; /* Power Reduction Port F */ -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ - register8_t DFLLCTRL; /* DFLL Control Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t JTAGUID; /* JTAG User ID */ - register8_t reserved_0x05; - register8_t MCUCR; /* MCU Control */ - register8_t reserved_0x07; - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t AWEXLOCK; /* AWEX Lock */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ -} EVSYS_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ - EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ - EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ - EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ - EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ - EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ - EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ - EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ - EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ - EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ - EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ - EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ - EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ - EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ - EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ - EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ - EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ - EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ - EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ - EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ - EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ - EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ - EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ - EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ - EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ - EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ - EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ - EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ - EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ - EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ - EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ - EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ - EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ - EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ - EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ - EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ - EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ - EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ - EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ - EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ - EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ - EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ - EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ - EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ - EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ - EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ - EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ - EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ - EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ - EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -} EVSYS_CHMUX_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -} NVM_FUSES_t; - - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ - register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t reserved_0x28; - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; -} NVM_PROD_SIGNATURES_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -} NVM_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* 32.768kHz Timer Oscillator Pin Selection */ -typedef enum TOSCSEL_enum -{ - TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ - TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ -} TOSCSEL_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t reserved_0x07; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -} ADC_CH_MUXNEG_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -} ADC_CH_INPUTMODE_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Counter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ -} TWI_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* SDA hold time */ -typedef enum SDA_HOLD_TIME_enum -{ - SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ - SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ - SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ - SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -} SDA_HOLD_TIME_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -} PORTCFG_t; - - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INT0MASK; /* Port Interrupt 0 Mask */ - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Virtual Port 0 Mapping */ -typedef enum PORTCFG_VP0MAP_enum -{ - PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP0MAP_t; - -/* Virtual Port 1 Mapping */ -typedef enum PORTCFG_VP1MAP_enum -{ - PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP1MAP_t; - -/* Virtual Port 2 Mapping */ -typedef enum PORTCFG_VP2MAP_enum -{ - PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ - PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ - PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ - PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ - PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ - PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ - PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ - PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ - PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ - PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ - PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ - PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ - PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ - PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ - PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ - PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -} PORTCFG_VP2MAP_t; - -/* Virtual Port 3 Mapping */ -typedef enum PORTCFG_VP3MAP_enum -{ - PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ - PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ - PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ - PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ - PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ - PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ - PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ - PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ - PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ - PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ - PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ - PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ - PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ - PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ - PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ - PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -} PORTCFG_VP3MAP_t; - -/* Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -} PORTCFG_CLKOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -} PORTCFG_EVOUT_t; - -/* Port Interrupt 0 Level */ -typedef enum PORT_INT0LVL_enum -{ - PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INT0LVL_t; - -/* Port Interrupt 1 Level */ -typedef enum PORT_INT1LVL_enum -{ - PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ - PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ - PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -} PORT_INT1LVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 0 */ -typedef struct TC0_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC0_t; - - -/* 16-bit Timer/Counter 1 */ -typedef struct TC1_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLFCLR; /* Control Register F Clear */ - register8_t CTRLFSET; /* Control Register F Set */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -} TC1_t; - - -/* Advanced Waveform Extension */ -typedef struct AWEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ - register8_t DTHS; /* Dead Time High Side */ - register8_t DTLSBUF; /* Dead Time Low Side Buffer */ - register8_t DTHSBUF; /* Dead Time High Side Buffer */ - register8_t OUTOVEN; /* Output Override Enable */ -} AWEX_t; - - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register */ -} HIRES_t; - -/* Clock Selection */ -typedef enum TC_CLKSEL_enum -{ - TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_CLKSEL_t; - -/* Waveform Generation Mode */ -typedef enum TC_WGMODE_enum -{ - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC_WGMODE_t; - -/* Event Action */ -typedef enum TC_EVACT_enum -{ - TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ - TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ - TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ - TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ - TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ - TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -} TC_EVACT_t; - -/* Event Selection */ -typedef enum TC_EVSEL_enum -{ - TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC_EVSEL_t; - -/* Error Interrupt Level */ -typedef enum TC_ERRINTLVL_enum -{ - TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC_OVFINTLVL_enum -{ - TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_OVFINTLVL_t; - -/* Compare or Capture D Interrupt Level */ -typedef enum TC_CCDINTLVL_enum -{ - TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC_CCDINTLVL_t; - -/* Compare or Capture C Interrupt Level */ -typedef enum TC_CCCINTLVL_enum -{ - TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC_CCCINTLVL_t; - -/* Compare or Capture B Interrupt Level */ -typedef enum TC_CCBINTLVL_enum -{ - TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC_CCBINTLVL_t; - -/* Compare or Capture A Interrupt Level */ -typedef enum TC_CCAINTLVL_enum -{ - TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC_CCAINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC_CMD_enum -{ - TC_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC_CMD_t; - -/* Fault Detect Action */ -typedef enum AWEX_FDACT_enum -{ - AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ - AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ - AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -} AWEX_FDACT_t; - -/* High Resolution Enable */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ - HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ - HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* DFLL - DFLL */ -#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) -#define PR_PRPE _SFR_MEM8(0x0075) -#define PR_PRPF _SFR_MEM8(0x0076) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_JTAGUID _SFR_MEM8(0x0094) -#define MCU_MCUCR _SFR_MEM8(0x0096) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_AWEXLOCK _SFR_MEM8(0x0099) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -/* TWI - Two-Wire Interface */ -#define TWIE_CTRL _SFR_MEM8(0x04A0) -#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INT0MASK _SFR_MEM8(0x060A) -#define PORTA_INT1MASK _SFR_MEM8(0x060B) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTB_DIR _SFR_MEM8(0x0620) -#define PORTB_DIRSET _SFR_MEM8(0x0621) -#define PORTB_DIRCLR _SFR_MEM8(0x0622) -#define PORTB_DIRTGL _SFR_MEM8(0x0623) -#define PORTB_OUT _SFR_MEM8(0x0624) -#define PORTB_OUTSET _SFR_MEM8(0x0625) -#define PORTB_OUTCLR _SFR_MEM8(0x0626) -#define PORTB_OUTTGL _SFR_MEM8(0x0627) -#define PORTB_IN _SFR_MEM8(0x0628) -#define PORTB_INTCTRL _SFR_MEM8(0x0629) -#define PORTB_INT0MASK _SFR_MEM8(0x062A) -#define PORTB_INT1MASK _SFR_MEM8(0x062B) -#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -#define PORTB_REMAP _SFR_MEM8(0x062E) -#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INT0MASK _SFR_MEM8(0x064A) -#define PORTC_INT1MASK _SFR_MEM8(0x064B) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INT0MASK _SFR_MEM8(0x066A) -#define PORTD_INT1MASK _SFR_MEM8(0x066B) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTE_DIR _SFR_MEM8(0x0680) -#define PORTE_DIRSET _SFR_MEM8(0x0681) -#define PORTE_DIRCLR _SFR_MEM8(0x0682) -#define PORTE_DIRTGL _SFR_MEM8(0x0683) -#define PORTE_OUT _SFR_MEM8(0x0684) -#define PORTE_OUTSET _SFR_MEM8(0x0685) -#define PORTE_OUTCLR _SFR_MEM8(0x0686) -#define PORTE_OUTTGL _SFR_MEM8(0x0687) -#define PORTE_IN _SFR_MEM8(0x0688) -#define PORTE_INTCTRL _SFR_MEM8(0x0689) -#define PORTE_INT0MASK _SFR_MEM8(0x068A) -#define PORTE_INT1MASK _SFR_MEM8(0x068B) -#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -#define PORTE_REMAP _SFR_MEM8(0x068E) -#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - -/* PORT - I/O Ports */ -#define PORTF_DIR _SFR_MEM8(0x06A0) -#define PORTF_DIRSET _SFR_MEM8(0x06A1) -#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -#define PORTF_OUT _SFR_MEM8(0x06A4) -#define PORTF_OUTSET _SFR_MEM8(0x06A5) -#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -#define PORTF_IN _SFR_MEM8(0x06A8) -#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -#define PORTF_REMAP _SFR_MEM8(0x06AE) -#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCC0_CTRLA _SFR_MEM8(0x0800) -#define TCC0_CTRLB _SFR_MEM8(0x0801) -#define TCC0_CTRLC _SFR_MEM8(0x0802) -#define TCC0_CTRLD _SFR_MEM8(0x0803) -#define TCC0_CTRLE _SFR_MEM8(0x0804) -#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -#define TCC0_TEMP _SFR_MEM8(0x080F) -#define TCC0_CNT _SFR_MEM16(0x0820) -#define TCC0_PER _SFR_MEM16(0x0826) -#define TCC0_CCA _SFR_MEM16(0x0828) -#define TCC0_CCB _SFR_MEM16(0x082A) -#define TCC0_CCC _SFR_MEM16(0x082C) -#define TCC0_CCD _SFR_MEM16(0x082E) -#define TCC0_PERBUF _SFR_MEM16(0x0836) -#define TCC0_CCABUF _SFR_MEM16(0x0838) -#define TCC0_CCBBUF _SFR_MEM16(0x083A) -#define TCC0_CCCBUF _SFR_MEM16(0x083C) -#define TCC0_CCDBUF _SFR_MEM16(0x083E) - -/* TC1 - 16-bit Timer/Counter 1 */ -#define TCC1_CTRLA _SFR_MEM8(0x0840) -#define TCC1_CTRLB _SFR_MEM8(0x0841) -#define TCC1_CTRLC _SFR_MEM8(0x0842) -#define TCC1_CTRLD _SFR_MEM8(0x0843) -#define TCC1_CTRLE _SFR_MEM8(0x0844) -#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -#define TCC1_TEMP _SFR_MEM8(0x084F) -#define TCC1_CNT _SFR_MEM16(0x0860) -#define TCC1_PER _SFR_MEM16(0x0866) -#define TCC1_CCA _SFR_MEM16(0x0868) -#define TCC1_CCB _SFR_MEM16(0x086A) -#define TCC1_PERBUF _SFR_MEM16(0x0876) -#define TCC1_CCABUF _SFR_MEM16(0x0878) -#define TCC1_CCBBUF _SFR_MEM16(0x087A) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXC_CTRL _SFR_MEM8(0x0880) -#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -#define AWEXC_STATUS _SFR_MEM8(0x0884) -#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -#define AWEXC_DTLS _SFR_MEM8(0x0888) -#define AWEXC_DTHS _SFR_MEM8(0x0889) -#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x0890) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08A0) -#define USARTC0_STATUS _SFR_MEM8(0x08A1) -#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - -/* SPI - Serial Peripheral Interface */ -#define SPIC_CTRL _SFR_MEM8(0x08C0) -#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -#define SPIC_STATUS _SFR_MEM8(0x08C2) -#define SPIC_DATA _SFR_MEM8(0x08C3) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCD0_CTRLA _SFR_MEM8(0x0900) -#define TCD0_CTRLB _SFR_MEM8(0x0901) -#define TCD0_CTRLC _SFR_MEM8(0x0902) -#define TCD0_CTRLD _SFR_MEM8(0x0903) -#define TCD0_CTRLE _SFR_MEM8(0x0904) -#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -#define TCD0_TEMP _SFR_MEM8(0x090F) -#define TCD0_CNT _SFR_MEM16(0x0920) -#define TCD0_PER _SFR_MEM16(0x0926) -#define TCD0_CCA _SFR_MEM16(0x0928) -#define TCD0_CCB _SFR_MEM16(0x092A) -#define TCD0_CCC _SFR_MEM16(0x092C) -#define TCD0_CCD _SFR_MEM16(0x092E) -#define TCD0_PERBUF _SFR_MEM16(0x0936) -#define TCD0_CCABUF _SFR_MEM16(0x0938) -#define TCD0_CCBBUF _SFR_MEM16(0x093A) -#define TCD0_CCCBUF _SFR_MEM16(0x093C) -#define TCD0_CCDBUF _SFR_MEM16(0x093E) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09A0) -#define USARTD0_STATUS _SFR_MEM8(0x09A1) -#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - -/* SPI - Serial Peripheral Interface */ -#define SPID_CTRL _SFR_MEM8(0x09C0) -#define SPID_INTCTRL _SFR_MEM8(0x09C1) -#define SPID_STATUS _SFR_MEM8(0x09C2) -#define SPID_DATA _SFR_MEM8(0x09C3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCE0_CTRLA _SFR_MEM8(0x0A00) -#define TCE0_CTRLB _SFR_MEM8(0x0A01) -#define TCE0_CTRLC _SFR_MEM8(0x0A02) -#define TCE0_CTRLD _SFR_MEM8(0x0A03) -#define TCE0_CTRLE _SFR_MEM8(0x0A04) -#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -#define TCE0_TEMP _SFR_MEM8(0x0A0F) -#define TCE0_CNT _SFR_MEM16(0x0A20) -#define TCE0_PER _SFR_MEM16(0x0A26) -#define TCE0_CCA _SFR_MEM16(0x0A28) -#define TCE0_CCB _SFR_MEM16(0x0A2A) -#define TCE0_CCC _SFR_MEM16(0x0A2C) -#define TCE0_CCD _SFR_MEM16(0x0A2E) -#define TCE0_PERBUF _SFR_MEM16(0x0A36) -#define TCE0_CCABUF _SFR_MEM16(0x0A38) -#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - -/* AWEX - Advanced Waveform Extension */ -#define AWEXE_CTRL _SFR_MEM8(0x0A80) -#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -#define AWEXE_STATUS _SFR_MEM8(0x0A84) -#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -#define AWEXE_DTLS _SFR_MEM8(0x0A88) -#define AWEXE_DTHS _SFR_MEM8(0x0A89) -#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTE0_DATA _SFR_MEM8(0x0AA0) -#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - -/* SPI - Serial Peripheral Interface */ -#define SPIE_CTRL _SFR_MEM8(0x0AC0) -#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -#define SPIE_STATUS _SFR_MEM8(0x0AC2) -#define SPIE_DATA _SFR_MEM8(0x0AC3) - -/* TC0 - 16-bit Timer/Counter 0 */ -#define TCF0_CTRLA _SFR_MEM8(0x0B00) -#define TCF0_CTRLB _SFR_MEM8(0x0B01) -#define TCF0_CTRLC _SFR_MEM8(0x0B02) -#define TCF0_CTRLD _SFR_MEM8(0x0B03) -#define TCF0_CTRLE _SFR_MEM8(0x0B04) -#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -#define TCF0_TEMP _SFR_MEM8(0x0B0F) -#define TCF0_CNT _SFR_MEM16(0x0B20) -#define TCF0_PER _SFR_MEM16(0x0B26) -#define TCF0_CCA _SFR_MEM16(0x0B28) -#define TCF0_CCB _SFR_MEM16(0x0B2A) -#define TCF0_CCC _SFR_MEM16(0x0B2C) -#define TCF0_CCD _SFR_MEM16(0x0B2E) -#define TCF0_PERBUF _SFR_MEM16(0x0B36) -#define TCF0_CCABUF _SFR_MEM16(0x0B38) -#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - - - -/*================== Bitfield Definitions ================== */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - -#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ - -#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_SPI Predefined. */ -/* PR_SPI Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPE bit masks and bit positions */ -/* PR_TWI Predefined. */ -/* PR_TWI Predefined. */ - -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* PR.PRPF bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC0 Predefined. */ -/* PR_TC0 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.MCUCR bit masks and bit positions */ -#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.AWEXLOCK bit masks and bit positions */ -#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0xFF /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -#define NVM_CMD7_bp 7 /* Command bit 7 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ - -#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ - -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ - -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ -#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HSMODE Predefined. */ -/* AC_HSMODE Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ - -#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Counter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TWI - Two-Wire Interface */ -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* PORT - Port Configuration */ -/* PORTCFG.VPCTRLA bit masks and bit positions */ -#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ - -#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - -/* PORTCFG.VPCTRLB bit masks and bit positions */ -#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ - -#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - -/* PORTCFG.CLKEVOUT bit masks and bit positions */ -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ - -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ - -#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ -#define PORT_SPI_bp 5 /* SPI Remap bit position. */ - -#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ -#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ - -#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ - -#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ - -#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ - -#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ - -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN Predefined. */ -/* PORT_SRLEN Predefined. */ - -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC0.CTRLA bit masks and bit positions */ -#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC0.CTRLB bit masks and bit positions */ -#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ - -#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ - -#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC0.CTRLC bit masks and bit positions */ -#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ - -#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ - -#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC0.CTRLD bit masks and bit positions */ -#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC0_EVACT_gp 5 /* Event Action group position. */ -#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC0.INTCTRLA bit masks and bit positions */ -#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC0.INTCTRLB bit masks and bit positions */ -#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ - -#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ - -#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC0.CTRLFCLR bit masks and bit positions */ -#define TC0_CMD_gm 0x0C /* Command group mask. */ -#define TC0_CMD_gp 2 /* Command group position. */ -#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC0_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC0_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -#define TC0_DIR_bp 0 /* Direction bit position. */ - -/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD Predefined. */ -/* TC0_CMD Predefined. */ - -/* TC0_LUPD Predefined. */ -/* TC0_LUPD Predefined. */ - -/* TC0_DIR Predefined. */ -/* TC0_DIR Predefined. */ - -/* TC0.CTRLGCLR bit masks and bit positions */ -#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ - -#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ - -#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV Predefined. */ -/* TC0_CCDBV Predefined. */ - -/* TC0_CCCBV Predefined. */ -/* TC0_CCCBV Predefined. */ - -/* TC0_CCBBV Predefined. */ -/* TC0_CCBBV Predefined. */ - -/* TC0_CCABV Predefined. */ -/* TC0_CCABV Predefined. */ - -/* TC0_PERBV Predefined. */ -/* TC0_PERBV Predefined. */ - -/* TC0.INTFLAGS bit masks and bit positions */ -#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - -#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - -#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* TC1.CTRLA bit masks and bit positions */ -#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* TC1.CTRLB bit masks and bit positions */ -#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ - -#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ - -#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - -/* TC1.CTRLC bit masks and bit positions */ -#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ - -#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - -/* TC1.CTRLD bit masks and bit positions */ -#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC1_EVACT_gp 5 /* Event Action group position. */ -#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC1.CTRLE bit masks and bit positions */ -#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - -/* TC1.INTCTRLA bit masks and bit positions */ -#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - -#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - -/* TC1.INTCTRLB bit masks and bit positions */ -#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ - -#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - -/* TC1.CTRLFCLR bit masks and bit positions */ -#define TC1_CMD_gm 0x0C /* Command group mask. */ -#define TC1_CMD_gp 2 /* Command group position. */ -#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC1_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC1_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -#define TC1_DIR_bp 0 /* Direction bit position. */ - -/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD Predefined. */ -/* TC1_CMD Predefined. */ - -/* TC1_LUPD Predefined. */ -/* TC1_LUPD Predefined. */ - -/* TC1_DIR Predefined. */ -/* TC1_DIR Predefined. */ - -/* TC1.CTRLGCLR bit masks and bit positions */ -#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ - -#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ - -#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV Predefined. */ -/* TC1_CCBBV Predefined. */ - -/* TC1_CCABV Predefined. */ -/* TC1_CCABV Predefined. */ - -/* TC1_PERBV Predefined. */ -/* TC1_PERBV Predefined. */ - -/* TC1.INTFLAGS bit masks and bit positions */ -#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - -#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - -#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* AWEX.CTRL bit masks and bit positions */ -#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ - -#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ - -#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ - -#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ - -#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ - -#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - -/* AWEX.FDCTRL bit masks and bit positions */ -#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ - -#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ - -#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - -/* AWEX.STATUS bit masks and bit positions */ -#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ - -#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ - -#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ - -#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ - -/* PORTC interrupt vectors */ -#define PORTC_INT0_vect_num 2 -#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -#define PORTC_INT1_vect_num 3 -#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ - -/* PORTR interrupt vectors */ -#define PORTR_INT0_vect_num 4 -#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -#define PORTR_INT1_vect_num 5 -#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 10 -#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 11 -#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 12 -#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 13 -#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ - -/* TCC0 interrupt vectors */ -#define TCC0_OVF_vect_num 14 -#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -#define TCC0_ERR_vect_num 15 -#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -#define TCC0_CCA_vect_num 16 -#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -#define TCC0_CCB_vect_num 17 -#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -#define TCC0_CCC_vect_num 18 -#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -#define TCC0_CCD_vect_num 19 -#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -/* TCC1 interrupt vectors */ -#define TCC1_OVF_vect_num 20 -#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -#define TCC1_ERR_vect_num 21 -#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -#define TCC1_CCA_vect_num 22 -#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -#define TCC1_CCB_vect_num 23 -#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 24 -#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 25 -#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 26 -#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 27 -#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 32 -#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -#define NVM_SPM_vect_num 33 -#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - -/* PORTB interrupt vectors */ -#define PORTB_INT0_vect_num 34 -#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -#define PORTB_INT1_vect_num 35 -#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ - -/* PORTE interrupt vectors */ -#define PORTE_INT0_vect_num 43 -#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -#define PORTE_INT1_vect_num 44 -#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -/* TWIE interrupt vectors */ -#define TWIE_TWIS_vect_num 45 -#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -#define TWIE_TWIM_vect_num 46 -#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ - -/* TCE0 interrupt vectors */ -#define TCE0_OVF_vect_num 47 -#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -#define TCE0_ERR_vect_num 48 -#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -#define TCE0_CCA_vect_num 49 -#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -#define TCE0_CCB_vect_num 50 -#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -#define TCE0_CCC_vect_num 51 -#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -#define TCE0_CCD_vect_num 52 -#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -/* USARTE0 interrupt vectors */ -#define USARTE0_RXC_vect_num 58 -#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -#define USARTE0_DRE_vect_num 59 -#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -#define USARTE0_TXC_vect_num 60 -#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT0_vect_num 64 -#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -#define PORTD_INT1_vect_num 65 -#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ - -/* PORTA interrupt vectors */ -#define PORTA_INT0_vect_num 66 -#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -#define PORTA_INT1_vect_num 67 -#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 68 -#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 69 -#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 70 -#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 71 -#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ - -/* TCD0 interrupt vectors */ -#define TCD0_OVF_vect_num 77 -#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -#define TCD0_ERR_vect_num 78 -#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -#define TCD0_CCA_vect_num 79 -#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -#define TCD0_CCB_vect_num 80 -#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -#define TCD0_CCC_vect_num 81 -#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -#define TCD0_CCD_vect_num 82 -#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -/* SPID interrupt vectors */ -#define SPID_INT_vect_num 87 -#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 88 -#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 89 -#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 90 -#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ - -/* PORTF interrupt vectors */ -#define PORTF_INT0_vect_num 104 -#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -#define PORTF_INT1_vect_num 105 -#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ - -/* TCF0 interrupt vectors */ -#define TCF0_OVF_vect_num 108 -#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -#define TCF0_ERR_vect_num 109 -#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -#define TCF0_CCA_vect_num 110 -#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -#define TCF0_CCB_vect_num 111 -#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -#define TCF0_CCC_vect_num 112 -#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -#define TCF0_CCD_vect_num 113 -#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (114 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (256) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (256) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (256) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (6) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (256) -#define USER_SIGNATURES_PAGE_SIZE (256) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (256) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 256 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 6 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4A - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC1 -#define __AVR_HAVE_PRPC_TC0 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_SPI -#define __AVR_HAVE_PRPD_TC0 - -/* PR.PRPE */ -#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPE_TWI -#define __AVR_HAVE_PRPE_USART0 -#define __AVR_HAVE_PRPE_TC0 - -/* PR.PRPF */ -#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) -#define __AVR_HAVE_PRPF_USART0 -#define __AVR_HAVE_PRPF_TC0 - - -#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32d3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32D3_H_INCLUDED +#define _AVR_ATXMEGA32D3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* 32.768kHz Timer Oscillator Pin Selection */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ +#define PORT_SPI_bp 5 /* SPI Remap bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ +#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ + +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4A + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32d4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32d4.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox32d4.h - definitions for ATxmega32D4 */ @@ -884,12 +884,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; /* --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox32e5.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox32e5.h @@ -1,7699 +1,7699 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox32e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA32E5_H_INCLUDED -#define _AVR_ATXMEGA32E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (36864) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (32768) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x7000) -#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x8000) -#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (12288) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (1024) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (4096) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (1024) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x95 -#define SIGNATURE_2 0x4C - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32E5_H_INCLUDED +#define _AVR_ATXMEGA32E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4C + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox384c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox384c3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1023,7 +1020,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2497,7 +2494,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2520,7 +2517,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6245,14 +6242,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6765,9 +6762,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox384d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox384d3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -259,13 +257,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -803,7 +800,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2108,7 +2105,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2131,7 +2128,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5278,14 +5275,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -5774,9 +5771,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64a1.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64a1.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ /* avr/iox64a1.h - definitions for ATxmega64A1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64a1u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64a1u.h @@ -1,38 +1,36 @@ -/* Copyright (c) 2010 Atmel Corporation - All rights reserved. +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - - * Neither the name of the copyright holders nor the names of - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. */ - -/* $Id$ */ - -/* avr/iox64a1u.h - definitions for ATxmega64A1U */ - -/* This file should only be included from , never directly. */ #ifndef _AVR_IO_H_ # error "Include instead of this file." @@ -42,12 +40,10 @@ # define _AVR_IOXXX_H_ "iox64a1u.h" #else # error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega64A1U_H_ -#define _AVR_ATxmega64A1U_H_ 1 +#endif +#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED +#define _AVR_ATXMEGA64A1U_H_INCLUDED /* Ungrouped common registers */ #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ @@ -67,6 +63,24 @@ #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ @@ -77,7 +91,6 @@ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ - /* C Language Only */ #if !defined (__ASSEMBLER__) @@ -156,6 +169,12 @@ } OCD_t; +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + /* CCP signatures */ typedef enum CCP_enum { @@ -180,11 +199,6 @@ register8_t USBCTRL; /* USB Control Register */ } CLK_t; -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ /* Power Reduction */ typedef struct PR_struct @@ -258,6 +272,7 @@ typedef enum CLK_USBSRC_enum { CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ } CLK_USBSRC_t; @@ -284,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -305,7 +319,7 @@ register8_t XOSCCTRL; /* External Oscillator Control Register */ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ + register8_t PLLCTRL; /* PLL Control Register */ register8_t DFLLCTRL; /* DFLL Control Register */ } OSC_t; @@ -336,11 +350,19 @@ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ } OSC_PLLSRC_t; -/* 32 MHz Calibration Reference */ +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ typedef enum OSC_RC32MCREF_enum { OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ } OSC_RC32MCREF_t; @@ -399,9 +421,9 @@ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ @@ -415,9 +437,9 @@ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ @@ -461,6 +483,19 @@ register8_t STATUS; /* Status Register */ register8_t INTPRI; /* Interrupt Priority */ register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; } PMIC_t; @@ -478,6 +513,8 @@ register8_t VPCTRLA; /* Virtual Port Control Register A */ register8_t VPCTRLB; /* Virtual Port Control Register B */ register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ } PORTCFG_t; /* Virtual Port Mapping */ @@ -548,6 +585,44 @@ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ } PORTCFG_EVOUT_t; +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + /* -------------------------------------------------------------------------- @@ -584,17 +659,17 @@ /* Cyclic Redundancy Checker */ typedef struct CRC_struct { - register8_t CTRL; /* CRC Control Register */ - register8_t STATUS; /* CRC Status Register */ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ register8_t reserved_0x02; - register8_t DATAIN; /* CRC Data Input */ - register8_t CHECKSUM0; /* CRC Checksum byte 0 */ - register8_t CHECKSUM1; /* CRC Checksum byte 1 */ - register8_t CHECKSUM2; /* CRC Checksum byte 2 */ - register8_t CHECKSUM3; /* CRC Checksum byte 3 */ + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ } CRC_t; -/* CRC Reset */ +/* Reset */ typedef enum CRC_RESET_enum { CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ @@ -602,10 +677,10 @@ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ } CRC_RESET_t; -/* CRC Input Source */ +/* Input Source */ typedef enum CRC_SOURCE_enum { - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ @@ -641,11 +716,6 @@ register8_t reserved_0x0F; } DMA_CH_t; -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ /* DMA Controller */ typedef struct DMA_struct @@ -1038,15 +1108,15 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ typedef enum NVM_CMD_enum { NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ @@ -1070,13 +1140,14 @@ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ } NVM_CMD_t; /* SPM ready interrupt level */ @@ -1100,36 +1171,36 @@ /* Boot lock bits - boot setcion */ typedef enum NVM_BLBB_enum { - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ } NVM_BLBB_t; /* Boot lock bits - application section */ typedef enum NVM_BLBA_enum { - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ } NVM_BLBA_t; /* Boot lock bits - application table section */ typedef enum NVM_BLBAT_enum { - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ } NVM_BLBAT_t; /* Lock bits */ typedef enum NVM_LB_enum { - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ } NVM_LB_t; @@ -1144,17 +1215,13 @@ { register8_t CTRL; /* Control Register */ register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ register8_t INTFLAGS; /* Interrupt Flags */ _WORDREGISTER(RES); /* Channel Result */ - register8_t reserved_0x7; + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; } ADC_CH_t; -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ /* Analog-to-Digital Converter */ typedef struct ADC_struct @@ -1166,7 +1233,7 @@ register8_t PRESCALER; /* Clock Prescaler */ register8_t reserved_0x05; register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ + register8_t TEMP; /* Temporary Register */ register8_t reserved_0x08; register8_t reserved_0x09; register8_t reserved_0x0A; @@ -1224,14 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -1253,7 +1324,7 @@ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ } ADC_CH_GAIN_t; /* Conversion result resolution */ @@ -1265,22 +1336,22 @@ } ADC_RESOLUTION_t; /* Current Limitation Mode */ -typedef enum ADC_CURRENT_enum +typedef enum ADC_CURRLIMIT_enum { - ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ - ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ - ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ - ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ -} ADC_CURRENT_t; + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; /* Voltage reference selection */ typedef enum ADC_REFSEL_enum { ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ } ADC_REFSEL_t; /* Channel sweep selection */ @@ -1314,7 +1385,7 @@ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ } ADC_EVACT_t; /* Interupt mode */ @@ -1370,7 +1441,7 @@ register8_t CTRLB; /* Control Register B */ register8_t CTRLC; /* Control Register C */ register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ + register8_t reserved_0x04; register8_t STATUS; /* Status */ register8_t reserved_0x06; register8_t reserved_0x07; @@ -1424,38 +1495,6 @@ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ } DAC_EVSEL_t; -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ - DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ - DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ - DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ - DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ - DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ - DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ - DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ - DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ -} DAC_CONINTVAL_t; - -/* Refresh rate */ -typedef enum DAC_REFRESH_enum -{ - DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ - DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ - DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ - DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ - DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ - DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ - DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ - DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ - DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */ - DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ - DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ - DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ - DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - /* -------------------------------------------------------------------------- @@ -1556,7 +1595,7 @@ /* -------------------------------------------------------------------------- -RTC - Real-Time Clounter +RTC - Real-Time Counter -------------------------------------------------------------------------- */ @@ -1622,11 +1661,6 @@ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ } EBI_CS_t; -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ /* External Bus Interface */ typedef struct EBI_struct @@ -1652,28 +1686,28 @@ } EBI_t; /* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum +typedef enum EBI_CS_ASPACE_enum { - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ - EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ - EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ - EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ - EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ - EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ - EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ - EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ - EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ - EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ - EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ - EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ - EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ - EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ - EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ - EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ - EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ -} EBI_CS_ASIZE_t; + EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASPACE_t; -/* */ +/* SRAM Wait State Selection */ typedef enum EBI_CS_SRWS_enum { EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1681,7 +1715,7 @@ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_CS_SRWS_t; @@ -1743,7 +1777,7 @@ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ } EBI_SDCOL_t; -/* */ +/* SDRAM Load Mode to Active delay */ typedef enum EBI_MRDLY_enum { EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ @@ -1752,7 +1786,7 @@ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_MRDLY_t; -/* */ +/* SDRAM Row Cycle Delay */ typedef enum EBI_ROWCYCDLY_enum { EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ @@ -1760,12 +1794,12 @@ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ROWCYCDLY_t; -/* */ +/* SDRAM Row to Precharge Delay */ typedef enum EBI_RPDLY_enum { EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1773,12 +1807,12 @@ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_RPDLY_t; -/* */ +/* SDRAM Write Recovery Delay */ typedef enum EBI_WRDLY_enum { EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ @@ -1787,7 +1821,7 @@ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ } EBI_WRDLY_t; -/* */ +/* SDRAM Exit Self Refresh to Active Delay */ typedef enum EBI_ESRDLY_enum { EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ @@ -1795,12 +1829,12 @@ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ } EBI_ESRDLY_t; -/* */ +/* SDRAM Row to Column Delay */ typedef enum EBI_ROWCOLDLY_enum { EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ @@ -1808,7 +1842,7 @@ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ } EBI_ROWCOLDLY_t; @@ -1832,11 +1866,6 @@ register8_t DATA; /* Data Register */ } TWI_MASTER_t; -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ /* */ typedef struct TWI_SLAVE_struct @@ -1849,11 +1878,6 @@ register8_t ADDRMASK; /* Address Mask Register */ } TWI_SLAVE_t; -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ /* Two-Wire Interface */ typedef struct TWI_struct @@ -1916,10 +1940,19 @@ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ } TWI_SLAVE_CMD_t; +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + /* -------------------------------------------------------------------------- -USB - USB Module +USB - USB -------------------------------------------------------------------------- */ @@ -1928,66 +1961,13 @@ { register8_t STATUS; /* Endpoint Status */ register8_t CTRL; /* Endpoint Control */ - register8_t CNTL; /* USB Endpoint Counter Low Byte */ - register8_t CNTH; /* USB Endpoint Counter High Byte */ - register8_t DATAPTRL; /* Data Pointer Low Byte */ - register8_t DATAPTRH; /* Data Pointer High Byte */ - register8_t AUXDATAL; /* Auxiliary Data Low Byte */ - register8_t AUXDATAH; /* Auxiliary Data High Byte */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ } USB_EP_t; -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ -/* USB Endpoint table */ -typedef struct USB_EP_TABLE_struct -{ - USB_EP_t EP0OUT; /* USB Endpoint 0 Output */ - USB_EP_t EP0IN; /* USB Endpoint 0 Input */ - USB_EP_t EP1OUT; /* USB Endpoint 1 Output */ - USB_EP_t EP1IN; /* USB Endpoint 1 Input */ - USB_EP_t EP2OUT; /* USB Endpoint 2 Output */ - USB_EP_t EP2IN; /* USB Endpoint 2 Input */ - USB_EP_t EP3OUT; /* USB Endpoint 3 Output */ - USB_EP_t EP3IN; /* USB Endpoint 3 Input */ - USB_EP_t EP4OUT; /* USB Endpoint 4 Output */ - USB_EP_t EP4IN; /* USB Endpoint 4 Input */ - USB_EP_t EP5OUT; /* USB Endpoint 5 Output */ - USB_EP_t EP5IN; /* USB Endpoint 5 Input */ - USB_EP_t EP6OUT; /* USB Endpoint 6 Output */ - USB_EP_t EP6IN; /* USB Endpoint 6 Input */ - USB_EP_t EP7OUT; /* USB Endpoint 7 Output */ - USB_EP_t EP7IN; /* USB Endpoint 7 Input */ - USB_EP_t EP8OUT; /* USB Endpoint 8 Output */ - USB_EP_t EP8IN; /* USB Endpoint 8 Input */ - USB_EP_t EP9OUT; /* USB Endpoint 9 Output */ - USB_EP_t EP9IN; /* USB Endpoint 9 Input */ - USB_EP_t EP10OUT; /* USB Endpoint 10 Output */ - USB_EP_t EP10IN; /* USB Endpoint 10 Input */ - USB_EP_t EP11OUT; /* USB Endpoint 11 Output */ - USB_EP_t EP11IN; /* USB Endpoint 11 Input */ - USB_EP_t EP12OUT; /* USB Endpoint 12 Output */ - USB_EP_t EP12IN; /* USB Endpoint 12 Input */ - USB_EP_t EP13OUT; /* USB Endpoint 13 Output */ - USB_EP_t EP13IN; /* USB Endpoint 13 Input */ - USB_EP_t EP14OUT; /* USB Endpoint 14 Output */ - USB_EP_t EP14IN; /* USB Endpoint 14 Input */ - USB_EP_t EP15OUT; /* USB Endpoint 15 Output */ - USB_EP_t EP15IN; /* USB Endpoint 15 Input */ - register8_t FRAMENUML; /* Frame Number Low Byte */ - register8_t FRAMENUMH; /* Frame Number High Byte */ -} USB_EP_TABLE_t; - -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ - -/* USB Module */ +/* Universal Serial Bus */ typedef struct USB_struct { register8_t CTRLA; /* Control Register A */ @@ -2051,6 +2031,71 @@ register8_t CAL1; /* Calibration Byte 1 */ } USB_t; + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + /* USB Endpoint Type */ typedef enum USB_EP_TYPE_enum { @@ -2060,27 +2105,18 @@ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ } USB_EP_TYPE_t; -/* USB Endpoint Buffer Size */ -typedef enum USB_EP_SIZE_enum -{ - USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ - USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ - USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ - USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ - USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ - USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -} USB_EP_SIZE_t; - -/* Interrupt level */ -typedef enum USB_INTLVL_enum +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum { - USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} USB_INTLVL_t; + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; /* @@ -2224,11 +2260,6 @@ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ } TC0_t; -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ /* 16-bit Timer/Counter 1 */ typedef struct TC1_struct @@ -2314,12 +2345,24 @@ { TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ } TC_WGMODE_t; +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + /* Event Action */ typedef enum TC_EVACT_enum { @@ -2412,6 +2455,165 @@ /* -------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- AWEX - Timer/Counter Advanced Waveform Extension -------------------------------------------------------------------------- */ @@ -2424,7 +2626,7 @@ register8_t FDEMASK; /* Fault Detection Event Mask */ register8_t FDCTRL; /* Fault Detection Control Register */ register8_t STATUS; /* Status Register */ - register8_t reserved_0x05; + register8_t STATUSSET; /* Status Set Register */ register8_t DTBOTH; /* Dead Time Both Sides */ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ register8_t DTLS; /* Dead Time Low Side */ @@ -2613,96 +2815,318 @@ /* -------------------------------------------------------------------------- -PRESC - Prescaler +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits -------------------------------------------------------------------------- */ -/* Prescaler */ -typedef struct PRESC_struct +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct { - register8_t PRESCALER; /* Control Register */ -} PRESC_t; + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; /* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* ========================================================================== IO Module Instances. Mapped to memory. ========================================================================== */ -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ #define CLK (*(CLK_t *) 0x0040) /* Clock System */ #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ #define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define RST (*(RST_t *) 0x0078) /* Reset */ #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ -#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ -#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ -#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */ -#define PORTA (*(PORT_t *) 0x0600) /* Port A */ -#define PORTB (*(PORT_t *) 0x0620) /* Port B */ -#define PORTC (*(PORT_t *) 0x0640) /* Port C */ -#define PORTD (*(PORT_t *) 0x0660) /* Port D */ -#define PORTE (*(PORT_t *) 0x0680) /* Port E */ -#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ -#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ -#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ -#define PORTK (*(PORT_t *) 0x0720) /* Port K */ -#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ -#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ -#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ -#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ -#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ -#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ +#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ +#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ +#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ -#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ -#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ -#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ -#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ -#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ -#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ -#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ -#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ -#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ -#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ -#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ -#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ -#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ #endif /* !defined (__ASSEMBLER__) */ @@ -2728,25 +3152,89 @@ #define GPIO_GPIORE _SFR_MEM8(0x000E) #define GPIO_GPIORF _SFR_MEM8(0x000F) -/* VPORT0 - Virtual Port 0 */ +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ #define VPORT0_DIR _SFR_MEM8(0x0010) #define VPORT0_OUT _SFR_MEM8(0x0011) #define VPORT0_IN _SFR_MEM8(0x0012) #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -/* VPORT1 - Virtual Port 1 */ +/* VPORT - Virtual Port */ #define VPORT1_DIR _SFR_MEM8(0x0014) #define VPORT1_OUT _SFR_MEM8(0x0015) #define VPORT1_IN _SFR_MEM8(0x0016) #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -/* VPORT2 - Virtual Port 2 */ +/* VPORT - Virtual Port */ #define VPORT2_DIR _SFR_MEM8(0x0018) #define VPORT2_OUT _SFR_MEM8(0x0019) #define VPORT2_IN _SFR_MEM8(0x001A) #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -/* VPORT3 - Virtual Port 3 */ +/* VPORT - Virtual Port */ #define VPORT3_DIR _SFR_MEM8(0x001C) #define VPORT3_OUT _SFR_MEM8(0x001D) #define VPORT3_IN _SFR_MEM8(0x001E) @@ -2756,7 +3244,7 @@ #define OCD_OCDR0 _SFR_MEM8(0x002E) #define OCD_OCDR1 _SFR_MEM8(0x002F) -/* CPU - CPU Registers */ +/* CPU - CPU registers */ #define CPU_CCP _SFR_MEM8(0x0034) #define CPU_RAMPD _SFR_MEM8(0x0038) #define CPU_RAMPX _SFR_MEM8(0x0039) @@ -2777,16 +3265,16 @@ /* SLEEP - Sleep Controller */ #define SLEEP_CTRL _SFR_MEM8(0x0048) -/* OSC - Oscillator Control */ +/* OSC - Oscillator */ #define OSC_CTRL _SFR_MEM8(0x0050) #define OSC_STATUS _SFR_MEM8(0x0051) #define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x005F) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) #define OSC_RC32KCAL _SFR_MEM8(0x0054) #define OSC_PLLCTRL _SFR_MEM8(0x0055) #define OSC_DFLLCTRL _SFR_MEM8(0x0056) -/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +/* DFLL - DFLL */ #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) #define DFLLRC32M_CALA _SFR_MEM8(0x0062) #define DFLLRC32M_CALB _SFR_MEM8(0x0063) @@ -2794,7 +3282,7 @@ #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +/* DFLL - DFLL */ #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) #define DFLLRC2M_CALA _SFR_MEM8(0x006A) #define DFLLRC2M_CALB _SFR_MEM8(0x006B) @@ -2811,7 +3299,7 @@ #define PR_PRPE _SFR_MEM8(0x0075) #define PR_PRPF _SFR_MEM8(0x0076) -/* RST - Reset Controller */ +/* RST - Reset */ #define RST_STATUS _SFR_MEM8(0x0078) #define RST_CTRL _SFR_MEM8(0x0079) @@ -2831,25 +3319,27 @@ #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) #define MCU_AWEXLOCK _SFR_MEM8(0x0099) -/* PMIC - Programmable Interrupt Controller */ +/* PMIC - Programmable Multi-level Interrupt Controller */ #define PMIC_STATUS _SFR_MEM8(0x00A0) #define PMIC_INTPRI _SFR_MEM8(0x00A1) #define PMIC_CTRL _SFR_MEM8(0x00A2) -/* PORTCFG - Port Configuration */ +/* PORTCFG - I/O port Configuration */ #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -/* AES - AES Crypto Module */ +/* AES - AES Module */ #define AES_CTRL _SFR_MEM8(0x00C0) #define AES_STATUS _SFR_MEM8(0x00C1) #define AES_STATE _SFR_MEM8(0x00C2) #define AES_KEY _SFR_MEM8(0x00C3) #define AES_INTCTRL _SFR_MEM8(0x00C4) -/* CRC - CRC Module */ +/* CRC - Cyclic Redundancy Checker */ #define CRC_CTRL _SFR_MEM8(0x00D0) #define CRC_STATUS _SFR_MEM8(0x00D1) #define CRC_DATAIN _SFR_MEM8(0x00D3) @@ -2932,7 +3422,7 @@ #define EVSYS_STROBE _SFR_MEM8(0x0190) #define EVSYS_DATA _SFR_MEM8(0x0191) -/* NVM - Non Volatile Memory Controller */ +/* NVM - Non-volatile Memory Controller */ #define NVM_ADDR0 _SFR_MEM8(0x01C0) #define NVM_ADDR1 _SFR_MEM8(0x01C1) #define NVM_ADDR2 _SFR_MEM8(0x01C2) @@ -2946,7 +3436,7 @@ #define NVM_STATUS _SFR_MEM8(0x01CF) #define NVM_LOCKBITS _SFR_MEM8(0x01D0) -/* ADCA - Analog to Digital Converter A */ +/* ADC - Analog-to-Digital Converter */ #define ADCA_CTRLA _SFR_MEM8(0x0200) #define ADCA_CTRLB _SFR_MEM8(0x0201) #define ADCA_REFCTRL _SFR_MEM8(0x0202) @@ -2965,23 +3455,27 @@ #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) #define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) #define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) #define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) #define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -/* ADCB - Analog to Digital Converter B */ +/* ADC - Analog-to-Digital Converter */ #define ADCB_CTRLA _SFR_MEM8(0x0240) #define ADCB_CTRLB _SFR_MEM8(0x0241) #define ADCB_REFCTRL _SFR_MEM8(0x0242) @@ -3000,28 +3494,31 @@ #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) #define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) #define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) #define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) #define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -/* DACA - Digital to Analog Converter A */ +/* DAC - Digital-to-Analog Converter */ #define DACA_CTRLA _SFR_MEM8(0x0300) #define DACA_CTRLB _SFR_MEM8(0x0301) #define DACA_CTRLC _SFR_MEM8(0x0302) #define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_TIMCTRL _SFR_MEM8(0x0304) #define DACA_STATUS _SFR_MEM8(0x0305) #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) @@ -3030,12 +3527,11 @@ #define DACA_CH0DATA _SFR_MEM16(0x0318) #define DACA_CH1DATA _SFR_MEM16(0x031A) -/* DACB - Digital to Analog Converter B */ +/* DAC - Digital-to-Analog Converter */ #define DACB_CTRLA _SFR_MEM8(0x0320) #define DACB_CTRLB _SFR_MEM8(0x0321) #define DACB_CTRLC _SFR_MEM8(0x0322) #define DACB_EVCTRL _SFR_MEM8(0x0323) -#define DACB_TIMCTRL _SFR_MEM8(0x0324) #define DACB_STATUS _SFR_MEM8(0x0325) #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) @@ -3044,7 +3540,7 @@ #define DACB_CH0DATA _SFR_MEM16(0x0338) #define DACB_CH1DATA _SFR_MEM16(0x033A) -/* ACA - Analog Comparator A */ +/* AC - Analog Comparator */ #define ACA_AC0CTRL _SFR_MEM8(0x0380) #define ACA_AC1CTRL _SFR_MEM8(0x0381) #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) @@ -3054,7 +3550,7 @@ #define ACA_WINCTRL _SFR_MEM8(0x0386) #define ACA_STATUS _SFR_MEM8(0x0387) -/* ACB - Analog Comparator B */ +/* AC - Analog Comparator */ #define ACB_AC0CTRL _SFR_MEM8(0x0390) #define ACB_AC1CTRL _SFR_MEM8(0x0391) #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) @@ -3094,7 +3590,7 @@ #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) -/* TWIC - Two-Wire Interface C */ +/* TWI - Two-Wire Interface */ #define TWIC_CTRL _SFR_MEM8(0x0480) #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) @@ -3110,7 +3606,7 @@ #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -/* TWID - Two-Wire Interface D */ +/* TWI - Two-Wire Interface */ #define TWID_CTRL _SFR_MEM8(0x0490) #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) @@ -3126,7 +3622,7 @@ #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) -/* TWIE - Two-Wire Interface E */ +/* TWI - Two-Wire Interface */ #define TWIE_CTRL _SFR_MEM8(0x04A0) #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) @@ -3142,7 +3638,7 @@ #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -/* TWIF - Two-Wire Interface F */ +/* TWI - Two-Wire Interface */ #define TWIF_CTRL _SFR_MEM8(0x04B0) #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) @@ -3158,7 +3654,7 @@ #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) -/* USB - Universal Serial Bus Module */ +/* USB - Universal Serial Bus */ #define USB_CTRLA _SFR_MEM8(0x04C0) #define USB_CTRLB _SFR_MEM8(0x04C1) #define USB_STATUS _SFR_MEM8(0x04C2) @@ -3175,7 +3671,7 @@ #define USB_CAL0 _SFR_MEM8(0x04FA) #define USB_CAL1 _SFR_MEM8(0x04FB) -/* PORTA - Port A */ +/* PORT - I/O Ports */ #define PORTA_DIR _SFR_MEM8(0x0600) #define PORTA_DIRSET _SFR_MEM8(0x0601) #define PORTA_DIRCLR _SFR_MEM8(0x0602) @@ -3189,6 +3685,7 @@ #define PORTA_INT0MASK _SFR_MEM8(0x060A) #define PORTA_INT1MASK _SFR_MEM8(0x060B) #define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) @@ -3198,7 +3695,7 @@ #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -/* PORTB - Port B */ +/* PORT - I/O Ports */ #define PORTB_DIR _SFR_MEM8(0x0620) #define PORTB_DIRSET _SFR_MEM8(0x0621) #define PORTB_DIRCLR _SFR_MEM8(0x0622) @@ -3212,6 +3709,7 @@ #define PORTB_INT0MASK _SFR_MEM8(0x062A) #define PORTB_INT1MASK _SFR_MEM8(0x062B) #define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) @@ -3221,7 +3719,7 @@ #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -/* PORTC - Port C */ +/* PORT - I/O Ports */ #define PORTC_DIR _SFR_MEM8(0x0640) #define PORTC_DIRSET _SFR_MEM8(0x0641) #define PORTC_DIRCLR _SFR_MEM8(0x0642) @@ -3235,6 +3733,7 @@ #define PORTC_INT0MASK _SFR_MEM8(0x064A) #define PORTC_INT1MASK _SFR_MEM8(0x064B) #define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) @@ -3244,7 +3743,7 @@ #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -/* PORTD - Port D */ +/* PORT - I/O Ports */ #define PORTD_DIR _SFR_MEM8(0x0660) #define PORTD_DIRSET _SFR_MEM8(0x0661) #define PORTD_DIRCLR _SFR_MEM8(0x0662) @@ -3258,6 +3757,7 @@ #define PORTD_INT0MASK _SFR_MEM8(0x066A) #define PORTD_INT1MASK _SFR_MEM8(0x066B) #define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) @@ -3267,7 +3767,7 @@ #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -/* PORTE - Port E */ +/* PORT - I/O Ports */ #define PORTE_DIR _SFR_MEM8(0x0680) #define PORTE_DIRSET _SFR_MEM8(0x0681) #define PORTE_DIRCLR _SFR_MEM8(0x0682) @@ -3281,6 +3781,7 @@ #define PORTE_INT0MASK _SFR_MEM8(0x068A) #define PORTE_INT1MASK _SFR_MEM8(0x068B) #define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) @@ -3290,7 +3791,7 @@ #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -/* PORTF - Port F */ +/* PORT - I/O Ports */ #define PORTF_DIR _SFR_MEM8(0x06A0) #define PORTF_DIRSET _SFR_MEM8(0x06A1) #define PORTF_DIRCLR _SFR_MEM8(0x06A2) @@ -3304,6 +3805,7 @@ #define PORTF_INT0MASK _SFR_MEM8(0x06AA) #define PORTF_INT1MASK _SFR_MEM8(0x06AB) #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) @@ -3313,7 +3815,7 @@ #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -/* PORTH - Port H */ +/* PORT - I/O Ports */ #define PORTH_DIR _SFR_MEM8(0x06E0) #define PORTH_DIRSET _SFR_MEM8(0x06E1) #define PORTH_DIRCLR _SFR_MEM8(0x06E2) @@ -3327,6 +3829,7 @@ #define PORTH_INT0MASK _SFR_MEM8(0x06EA) #define PORTH_INT1MASK _SFR_MEM8(0x06EB) #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_REMAP _SFR_MEM8(0x06EE) #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) @@ -3336,7 +3839,7 @@ #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) -/* PORTJ - Port J */ +/* PORT - I/O Ports */ #define PORTJ_DIR _SFR_MEM8(0x0700) #define PORTJ_DIRSET _SFR_MEM8(0x0701) #define PORTJ_DIRCLR _SFR_MEM8(0x0702) @@ -3350,6 +3853,7 @@ #define PORTJ_INT0MASK _SFR_MEM8(0x070A) #define PORTJ_INT1MASK _SFR_MEM8(0x070B) #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_REMAP _SFR_MEM8(0x070E) #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) @@ -3359,7 +3863,7 @@ #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) -/* PORTK - Port K */ +/* PORT - I/O Ports */ #define PORTK_DIR _SFR_MEM8(0x0720) #define PORTK_DIRSET _SFR_MEM8(0x0721) #define PORTK_DIRCLR _SFR_MEM8(0x0722) @@ -3373,6 +3877,7 @@ #define PORTK_INT0MASK _SFR_MEM8(0x072A) #define PORTK_INT1MASK _SFR_MEM8(0x072B) #define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_REMAP _SFR_MEM8(0x072E) #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) @@ -3382,7 +3887,7 @@ #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) -/* PORTQ - Port Q */ +/* PORT - I/O Ports */ #define PORTQ_DIR _SFR_MEM8(0x07C0) #define PORTQ_DIRSET _SFR_MEM8(0x07C1) #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) @@ -3396,6 +3901,7 @@ #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_REMAP _SFR_MEM8(0x07CE) #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) @@ -3405,7 +3911,7 @@ #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) -/* PORTR - Port R */ +/* PORT - I/O Ports */ #define PORTR_DIR _SFR_MEM8(0x07E0) #define PORTR_DIRSET _SFR_MEM8(0x07E1) #define PORTR_DIRCLR _SFR_MEM8(0x07E2) @@ -3419,6 +3925,7 @@ #define PORTR_INT0MASK _SFR_MEM8(0x07EA) #define PORTR_INT1MASK _SFR_MEM8(0x07EB) #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) @@ -3428,7 +3935,7 @@ #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -/* TCC0 - Timer/Counter C0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCC0_CTRLA _SFR_MEM8(0x0800) #define TCC0_CTRLB _SFR_MEM8(0x0801) #define TCC0_CTRLC _SFR_MEM8(0x0802) @@ -3454,7 +3961,29 @@ #define TCC0_CCCBUF _SFR_MEM16(0x083C) #define TCC0_CCDBUF _SFR_MEM16(0x083E) -/* TCC1 - Timer/Counter C1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCC1_CTRLA _SFR_MEM8(0x0840) #define TCC1_CTRLB _SFR_MEM8(0x0841) #define TCC1_CTRLC _SFR_MEM8(0x0842) @@ -3476,11 +4005,12 @@ #define TCC1_CCABUF _SFR_MEM16(0x0878) #define TCC1_CCBBUF _SFR_MEM16(0x087A) -/* AWEXC - Advanced Waveform Extension C */ +/* AWEX - Advanced Waveform Extension */ #define AWEXC_CTRL _SFR_MEM8(0x0880) #define AWEXC_FDEMASK _SFR_MEM8(0x0882) #define AWEXC_FDCTRL _SFR_MEM8(0x0883) #define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) #define AWEXC_DTBOTH _SFR_MEM8(0x0886) #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) #define AWEXC_DTLS _SFR_MEM8(0x0888) @@ -3489,10 +4019,10 @@ #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -/* HIRESC - High-Resolution Extension C */ +/* HIRES - High-Resolution Extension */ #define HIRESC_CTRLA _SFR_MEM8(0x0890) -/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTC0_DATA _SFR_MEM8(0x08A0) #define USARTC0_STATUS _SFR_MEM8(0x08A1) #define USARTC0_CTRLA _SFR_MEM8(0x08A3) @@ -3501,7 +4031,7 @@ #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTC1_DATA _SFR_MEM8(0x08B0) #define USARTC1_STATUS _SFR_MEM8(0x08B1) #define USARTC1_CTRLA _SFR_MEM8(0x08B3) @@ -3510,7 +4040,7 @@ #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -/* SPIC - Serial Peripheral Interface C */ +/* SPI - Serial Peripheral Interface */ #define SPIC_CTRL _SFR_MEM8(0x08C0) #define SPIC_INTCTRL _SFR_MEM8(0x08C1) #define SPIC_STATUS _SFR_MEM8(0x08C2) @@ -3521,7 +4051,7 @@ #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -/* TCD0 - Timer/Counter D0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCD0_CTRLA _SFR_MEM8(0x0900) #define TCD0_CTRLB _SFR_MEM8(0x0901) #define TCD0_CTRLC _SFR_MEM8(0x0902) @@ -3547,7 +4077,29 @@ #define TCD0_CCCBUF _SFR_MEM16(0x093C) #define TCD0_CCDBUF _SFR_MEM16(0x093E) -/* TCD1 - Timer/Counter D1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCD1_CTRLA _SFR_MEM8(0x0940) #define TCD1_CTRLB _SFR_MEM8(0x0941) #define TCD1_CTRLC _SFR_MEM8(0x0942) @@ -3569,10 +4121,10 @@ #define TCD1_CCABUF _SFR_MEM16(0x0978) #define TCD1_CCBBUF _SFR_MEM16(0x097A) -/* HIRESD - High-Resolution Extension D */ +/* HIRES - High-Resolution Extension */ #define HIRESD_CTRLA _SFR_MEM8(0x0990) -/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTD0_DATA _SFR_MEM8(0x09A0) #define USARTD0_STATUS _SFR_MEM8(0x09A1) #define USARTD0_CTRLA _SFR_MEM8(0x09A3) @@ -3581,7 +4133,7 @@ #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTD1_DATA _SFR_MEM8(0x09B0) #define USARTD1_STATUS _SFR_MEM8(0x09B1) #define USARTD1_CTRLA _SFR_MEM8(0x09B3) @@ -3590,13 +4142,13 @@ #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -/* SPID - Serial Peripheral Interface D */ +/* SPI - Serial Peripheral Interface */ #define SPID_CTRL _SFR_MEM8(0x09C0) #define SPID_INTCTRL _SFR_MEM8(0x09C1) #define SPID_STATUS _SFR_MEM8(0x09C2) #define SPID_DATA _SFR_MEM8(0x09C3) -/* TCE0 - Timer/Counter E0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCE0_CTRLA _SFR_MEM8(0x0A00) #define TCE0_CTRLB _SFR_MEM8(0x0A01) #define TCE0_CTRLC _SFR_MEM8(0x0A02) @@ -3622,7 +4174,29 @@ #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -/* TCE1 - Timer/Counter E1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCE1_CTRLA _SFR_MEM8(0x0A40) #define TCE1_CTRLB _SFR_MEM8(0x0A41) #define TCE1_CTRLC _SFR_MEM8(0x0A42) @@ -3644,11 +4218,12 @@ #define TCE1_CCABUF _SFR_MEM16(0x0A78) #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -/* AWEXE - Advanced Waveform Extension E */ +/* AWEX - Advanced Waveform Extension */ #define AWEXE_CTRL _SFR_MEM8(0x0A80) #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) #define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) #define AWEXE_DTLS _SFR_MEM8(0x0A88) @@ -3657,10 +4232,10 @@ #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -/* HIRESE - High-Resolution Extension E */ +/* HIRES - High-Resolution Extension */ #define HIRESE_CTRLA _SFR_MEM8(0x0A90) -/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTE0_DATA _SFR_MEM8(0x0AA0) #define USARTE0_STATUS _SFR_MEM8(0x0AA1) #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) @@ -3669,7 +4244,7 @@ #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTE1_DATA _SFR_MEM8(0x0AB0) #define USARTE1_STATUS _SFR_MEM8(0x0AB1) #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) @@ -3678,13 +4253,13 @@ #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -/* SPIE - Serial Peripheral Interface E */ +/* SPI - Serial Peripheral Interface */ #define SPIE_CTRL _SFR_MEM8(0x0AC0) #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) #define SPIE_STATUS _SFR_MEM8(0x0AC2) #define SPIE_DATA _SFR_MEM8(0x0AC3) -/* TCF0 - Timer/Counter F0 */ +/* TC0 - 16-bit Timer/Counter 0 */ #define TCF0_CTRLA _SFR_MEM8(0x0B00) #define TCF0_CTRLB _SFR_MEM8(0x0B01) #define TCF0_CTRLC _SFR_MEM8(0x0B02) @@ -3710,7 +4285,29 @@ #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -/* TCF1 - Timer/Counter F1 */ +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* TC1 - 16-bit Timer/Counter 1 */ #define TCF1_CTRLA _SFR_MEM8(0x0B40) #define TCF1_CTRLB _SFR_MEM8(0x0B41) #define TCF1_CTRLC _SFR_MEM8(0x0B42) @@ -3732,10 +4329,10 @@ #define TCF1_CCABUF _SFR_MEM16(0x0B78) #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) -/* HIRESF - High-Resolution Extension F */ +/* HIRES - High-Resolution Extension */ #define HIRESF_CTRLA _SFR_MEM8(0x0B90) -/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTF0_DATA _SFR_MEM8(0x0BA0) #define USARTF0_STATUS _SFR_MEM8(0x0BA1) #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) @@ -3744,7 +4341,7 @@ #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ #define USARTF1_DATA _SFR_MEM8(0x0BB0) #define USARTF1_STATUS _SFR_MEM8(0x0BB1) #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) @@ -3753,7 +4350,7 @@ #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) -/* SPIF - Serial Peripheral Interface F */ +/* SPI - Serial Peripheral Interface */ #define SPIF_CTRL _SFR_MEM8(0x0BC0) #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) #define SPIF_STATUS _SFR_MEM8(0x0BC2) @@ -3771,12 +4368,30 @@ #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - /* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ /* CPU - CPU */ /* CPU.CCP bit masks and bit positions */ @@ -3799,7 +4414,6 @@ #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - /* CPU.SREG bit masks and bit positions */ #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ @@ -3825,7 +4439,6 @@ #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ #define CPU_C_bp 0 /* Carry Flag bit position. */ - /* CLK - Clock System */ /* CLK.CTRL bit masks and bit positions */ #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ @@ -3837,7 +4450,6 @@ #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - /* CLK.PSCTRL bit masks and bit positions */ #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ @@ -3859,12 +4471,10 @@ #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - /* CLK.LOCK bit masks and bit positions */ #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - /* CLK.RTCCTRL bit masks and bit positions */ #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ @@ -3878,7 +4488,6 @@ #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - /* CLK.USBCTRL bit masks and bit positions */ #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ @@ -3896,9 +4505,8 @@ #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ - +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ /* PR.PRGEN bit masks and bit positions */ #define PR_USB_bm 0x40 /* USB bit mask. */ @@ -3919,7 +4527,6 @@ #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ #define PR_DMA_bp 0 /* DMA-Controller bit position. */ - /* PR.PRPA bit masks and bit positions */ #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ #define PR_DAC_bp 2 /* Port A DAC bit position. */ @@ -3930,17 +4537,15 @@ #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - /* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ - -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ /* PR.PRPC bit masks and bit positions */ #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ @@ -3964,75 +4569,71 @@ #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - /* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* PR.PRPF bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ /* SLEEP - Sleep Controller */ /* SLEEP.CTRL bit masks and bit positions */ @@ -4048,7 +4649,6 @@ #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - /* OSC - Oscillator */ /* OSC.CTRL bit masks and bit positions */ #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ @@ -4066,7 +4666,6 @@ #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - /* OSC.STATUS bit masks and bit positions */ #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ @@ -4083,7 +4682,6 @@ #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - /* OSC.XOSCCTRL bit masks and bit positions */ #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ @@ -4095,6 +4693,9 @@ #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ @@ -4106,7 +4707,6 @@ #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - /* OSC.XOSCFAIL bit masks and bit positions */ #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ @@ -4120,7 +4720,6 @@ #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - /* OSC.PLLCTRL bit masks and bit positions */ #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ @@ -4129,6 +4728,9 @@ #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ @@ -4142,25 +4744,22 @@ #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - /* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz Calibration Reference bit 1 position. */ - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ /* DFLL - DFLL */ /* DFLL.CTRL bit masks and bit positions */ #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - /* DFLL.CALA bit masks and bit positions */ #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ @@ -4179,7 +4778,6 @@ #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - /* DFLL.CALB bit masks and bit positions */ #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ @@ -4196,7 +4794,6 @@ #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - /* RST - Reset */ /* RST.STATUS bit masks and bit positions */ #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ @@ -4220,12 +4817,10 @@ #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - /* RST.CTRL bit masks and bit positions */ #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ #define RST_SWRST_bp 0 /* Software Reset bit position. */ - /* WDT - Watch-Dog Timer */ /* WDT.CTRL bit masks and bit positions */ #define WDT_PER_gm 0x3C /* Period group mask. */ @@ -4245,7 +4840,6 @@ #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ #define WDT_CEN_bp 0 /* Change Enable bit position. */ - /* WDT.WINCTRL bit masks and bit positions */ #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ @@ -4264,33 +4858,29 @@ #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - /* WDT.STATUS bit masks and bit positions */ #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - /* MCU - MCU Control */ /* MCU.MCUCR bit masks and bit positions */ #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - /* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port A bit 1 position. */ - -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port B group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port B group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port B bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port B bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ - +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ /* MCU.EVSYSLOCK bit masks and bit positions */ #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ @@ -4299,15 +4889,19 @@ #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - /* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - /* PMIC - Programmable Multi-level Interrupt Controller */ /* PMIC.STATUS bit masks and bit positions */ #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ @@ -4322,6 +4916,25 @@ #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ /* PMIC.CTRL bit masks and bit positions */ #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ @@ -4339,7 +4952,6 @@ #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - /* PORTCFG - Port Configuration */ /* PORTCFG.VPCTRLA bit masks and bit positions */ #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ @@ -4364,7 +4976,6 @@ #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - /* PORTCFG.VPCTRLB bit masks and bit positions */ #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ @@ -4388,7 +4999,6 @@ #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - /* PORTCFG.CLKEVOUT bit masks and bit positions */ #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ @@ -4417,6 +5027,30 @@ #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ /* AES - AES Module */ /* AES.CTRL bit masks and bit positions */ @@ -4435,7 +5069,6 @@ #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - /* AES.STATUS bit masks and bit positions */ #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ #define AES_ERROR_bp 7 /* AES Error bit position. */ @@ -4443,7 +5076,6 @@ #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - /* AES.INTCTRL bit masks and bit positions */ #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define AES_INTLVL_gp 0 /* Interrupt level group position. */ @@ -4452,38 +5084,35 @@ #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - /* CRC - Cyclic Redundancy Checker */ /* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ -#define CRC_RESET_gp 6 /* CRC Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* CRC Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* CRC Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* CRC Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* CRC Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* CRC Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ - +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ /* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Enable bit mask. */ -#define CRC_BUSY_bp 0 /* Enable bit position. */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ /* DMA - DMA Controller */ /* DMA_CH.CTRLA bit masks and bit positions */ @@ -4509,7 +5138,6 @@ #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - /* DMA_CH.CTRLB bit masks and bit positions */ #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ @@ -4537,7 +5165,6 @@ #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - /* DMA_CH.ADDRCTRL bit masks and bit positions */ #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ @@ -4567,7 +5194,6 @@ #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - /* DMA_CH.TRIGSRC bit masks and bit positions */ #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ @@ -4588,7 +5214,6 @@ #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - /* DMA.CTRL bit masks and bit positions */ #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ #define DMA_ENABLE_bp 7 /* Enable bit position. */ @@ -4610,7 +5235,6 @@ #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - /* DMA.INTFLAGS bit masks and bit positions */ #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ @@ -4636,7 +5260,6 @@ #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - /* DMA.STATUS bit masks and bit positions */ #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ @@ -4662,7 +5285,6 @@ #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - /* EVSYS - Event System */ /* EVSYS.CH0MUX bit masks and bit positions */ #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ @@ -4684,153 +5306,33 @@ #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - /* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ -/* EVSYS_CHMUX0_bp Predefined. */ -/* EVSYS_CHMUX1_bm Predefined. */ -/* EVSYS_CHMUX1_bp Predefined. */ -/* EVSYS_CHMUX2_bm Predefined. */ -/* EVSYS_CHMUX2_bp Predefined. */ -/* EVSYS_CHMUX3_bm Predefined. */ -/* EVSYS_CHMUX3_bp Predefined. */ -/* EVSYS_CHMUX4_bm Predefined. */ -/* EVSYS_CHMUX4_bp Predefined. */ -/* EVSYS_CHMUX5_bm Predefined. */ -/* EVSYS_CHMUX5_bp Predefined. */ -/* EVSYS_CHMUX6_bm Predefined. */ -/* EVSYS_CHMUX6_bp Predefined. */ -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ /* EVSYS.CH0CTRL bit masks and bit positions */ #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ @@ -4855,109 +5357,51 @@ #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - /* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ -/* EVSYS_QDIRM0_bp Predefined. */ -/* EVSYS_QDIRM1_bm Predefined. */ -/* EVSYS_QDIRM1_bp Predefined. */ - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ - -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ - -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ -/* EVSYS_DIGFILT0_bp Predefined. */ -/* EVSYS_DIGFILT1_bm Predefined. */ -/* EVSYS_DIGFILT1_bp Predefined. */ -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ /* NVM - Non Volatile Memory Controller */ /* NVM.CMD bit masks and bit positions */ @@ -4978,12 +5422,10 @@ #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ #define NVM_CMD6_bp 6 /* Command bit 6 position. */ - /* NVM.CTRLA bit masks and bit positions */ #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - /* NVM.CTRLB bit masks and bit positions */ #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ @@ -4997,7 +5439,6 @@ #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - /* NVM.INTCTRL bit masks and bit positions */ #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ @@ -5013,7 +5454,6 @@ #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - /* NVM.STATUS bit masks and bit positions */ #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ @@ -5027,7 +5467,6 @@ #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - /* NVM.LOCKBITS bit masks and bit positions */ #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ @@ -5057,7 +5496,6 @@ #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - /* ADC - Analog/Digital Converter */ /* ADC_CH.CTRL bit masks and bit positions */ #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ @@ -5079,7 +5517,6 @@ #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - /* ADC_CH.MUXCTRL bit masks and bit positions */ #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ @@ -5103,13 +5540,14 @@ #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ /* ADC_CH.INTCTRL bit masks and bit positions */ #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ @@ -5126,11 +5564,32 @@ #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - /* ADC_CH.INTFLAGS bit masks and bit positions */ #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ /* ADC.CTRLA bit masks and bit positions */ #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ @@ -5158,17 +5617,16 @@ #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - /* ADC.CTRLB bit masks and bit positions */ #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRENT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ @@ -5183,7 +5641,6 @@ #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - /* ADC.REFCTRL bit masks and bit positions */ #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ @@ -5200,7 +5657,6 @@ #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - /* ADC.EVCTRL bit masks and bit positions */ #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ @@ -5227,7 +5683,6 @@ #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - /* ADC.PRESCALER bit masks and bit positions */ #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ @@ -5238,7 +5693,6 @@ #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - /* ADC.INTFLAGS bit masks and bit positions */ #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ @@ -5252,7 +5706,6 @@ #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - /* DAC - Digital/Analog Converter */ /* DAC.CTRLA bit masks and bit positions */ #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ @@ -5270,7 +5723,6 @@ #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ #define DAC_ENABLE_bp 0 /* Enable bit position. */ - /* DAC.CTRLB bit masks and bit positions */ #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ #define DAC_CHSEL_gp 5 /* Channel Select group position. */ @@ -5285,7 +5737,6 @@ #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - /* DAC.CTRLC bit masks and bit positions */ #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ #define DAC_REFSEL_gp 3 /* Reference Select group position. */ @@ -5297,7 +5748,6 @@ #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - /* DAC.EVCTRL bit masks and bit positions */ #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ @@ -5311,29 +5761,6 @@ #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ -#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ -#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ -#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ -#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ -#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ -#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ -#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ - -#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ -#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ -#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ -#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ -#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ -#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ -#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ -#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ -#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - /* DAC.STATUS bit masks and bit positions */ #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ @@ -5341,7 +5768,6 @@ #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - /* DAC.CH0GAINCAL bit masks and bit positions */ #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ @@ -5360,7 +5786,6 @@ #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - /* DAC.CH0OFFSETCAL bit masks and bit positions */ #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ @@ -5379,7 +5804,6 @@ #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - /* DAC.CH1GAINCAL bit masks and bit positions */ #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ @@ -5398,7 +5822,6 @@ #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - /* DAC.CH1OFFSETCAL bit masks and bit positions */ #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ @@ -5417,7 +5840,6 @@ #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - /* AC - Analog Comparator */ /* AC.AC0CTRL bit masks and bit positions */ #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ @@ -5447,35 +5869,21 @@ #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ #define AC_ENABLE_bp 0 /* Enable bit position. */ - /* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ -/* AC_INTMODE0_bp Predefined. */ -/* AC_INTMODE1_bm Predefined. */ -/* AC_INTMODE1_bp Predefined. */ - -/* AC_INTLVL_gm Predefined. */ -/* AC_INTLVL_gp Predefined. */ -/* AC_INTLVL0_bm Predefined. */ -/* AC_INTLVL0_bp Predefined. */ -/* AC_INTLVL1_bm Predefined. */ -/* AC_INTLVL1_bp Predefined. */ - -/* AC_HSMODE_bm Predefined. */ -/* AC_HSMODE_bp Predefined. */ - -/* AC_HYSMODE_gm Predefined. */ -/* AC_HYSMODE_gp Predefined. */ -/* AC_HYSMODE0_bm Predefined. */ -/* AC_HYSMODE0_bp Predefined. */ -/* AC_HYSMODE1_bm Predefined. */ -/* AC_HYSMODE1_bp Predefined. */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ /* AC.AC0MUXCTRL bit masks and bit positions */ #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ @@ -5496,32 +5904,20 @@ #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - /* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ -/* AC_MUXPOS0_bp Predefined. */ -/* AC_MUXPOS1_bm Predefined. */ -/* AC_MUXPOS1_bp Predefined. */ -/* AC_MUXPOS2_bm Predefined. */ -/* AC_MUXPOS2_bp Predefined. */ - -/* AC_MUXNEG_gm Predefined. */ -/* AC_MUXNEG_gp Predefined. */ -/* AC_MUXNEG0_bm Predefined. */ -/* AC_MUXNEG0_bp Predefined. */ -/* AC_MUXNEG1_bm Predefined. */ -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ /* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - /* AC.CTRLB bit masks and bit positions */ #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ @@ -5538,7 +5934,6 @@ #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - /* AC.WINCTRL bit masks and bit positions */ #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ @@ -5557,7 +5952,6 @@ #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - /* AC.STATUS bit masks and bit positions */ #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ #define AC_WSTATE_gp 6 /* Window Mode State group position. */ @@ -5581,8 +5975,7 @@ #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* RTC - Real-Time Clounter */ +/* RTC - Real-Time Counter */ /* RTC.CTRL bit masks and bit positions */ #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ @@ -5593,12 +5986,10 @@ #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - /* RTC.STATUS bit masks and bit positions */ #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - /* RTC.INTCTRL bit masks and bit positions */ #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ @@ -5614,7 +6005,6 @@ #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - /* RTC.INTFLAGS bit masks and bit positions */ #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ @@ -5622,21 +6012,20 @@ #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - /* EBI - External Bus Interface */ /* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ -#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ -#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ -#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ -#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ -#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ -#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ +#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ +#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ +#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ +#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ +#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ +#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ +#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ +#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ +#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ +#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ +#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ @@ -5645,7 +6034,6 @@ #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - /* EBI_CS.CTRLB bit masks and bit positions */ #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ @@ -5669,7 +6057,6 @@ #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - /* EBI.CTRL bit masks and bit positions */ #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ @@ -5699,7 +6086,6 @@ #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - /* EBI.SDRAMCTRLA bit masks and bit positions */ #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ @@ -5714,7 +6100,6 @@ #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - /* EBI.SDRAMCTRLB bit masks and bit positions */ #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ @@ -5741,7 +6126,6 @@ #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - /* EBI.SDRAMCTRLC bit masks and bit positions */ #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ @@ -5768,7 +6152,6 @@ #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - /* TWI - Two-Wire Interface */ /* TWI_MASTER.CTRLA bit masks and bit positions */ #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ @@ -5787,14 +6170,13 @@ #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - /* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ @@ -5802,7 +6184,6 @@ #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - /* TWI_MASTER.CTRLC bit masks and bit positions */ #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ @@ -5814,7 +6195,6 @@ #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - /* TWI_MASTER.STATUS bit masks and bit positions */ #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ @@ -5841,7 +6221,6 @@ #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - /* TWI_SLAVE.CTRLA bit masks and bit positions */ #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ @@ -5868,7 +6247,6 @@ #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - /* TWI_SLAVE.CTRLB bit masks and bit positions */ #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ @@ -5880,7 +6258,6 @@ #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - /* TWI_SLAVE.STATUS bit masks and bit positions */ #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ @@ -5906,7 +6283,6 @@ #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ @@ -5928,31 +6304,36 @@ #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - /* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* USB - USB Module */ +/* USB - USB */ /* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ @@ -5969,7 +6350,6 @@ #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - /* USB_EP.CTRL bit masks and bit positions */ #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ @@ -5987,30 +6367,21 @@ #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -/* USB_EP_STALL_bm Predefined. */ -/* USB_EP_STALL_bp Predefined. */ - -#define USB_EP_SIZE_gm 0x07 /* Data Buffer Size group mask. */ -#define USB_EP_SIZE_gp 0 /* Data Buffer Size group position. */ -#define USB_EP_SIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -#define USB_EP_SIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -#define USB_EP_SIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -#define USB_EP_SIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -#define USB_EP_SIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -#define USB_EP_SIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - - -/* USB_EP.CNTH bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ - -#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ -#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ -#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ -#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ -#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ -#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ /* USB.CTRLA bit masks and bit positions */ #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ @@ -6036,7 +6407,6 @@ #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - /* USB.CTRLB bit masks and bit positions */ #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ @@ -6050,7 +6420,6 @@ #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ #define USB_ATTACH_bp 0 /* Attach bit position. */ - /* USB.STATUS bit masks and bit positions */ #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ @@ -6064,7 +6433,6 @@ #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - /* USB.ADDR bit masks and bit positions */ #define USB_ADDR_gm 0x7F /* Device Address group mask. */ #define USB_ADDR_gp 0 /* Device Address group position. */ @@ -6083,7 +6451,6 @@ #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - /* USB.FIFOWP bit masks and bit positions */ #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ @@ -6098,7 +6465,6 @@ #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - /* USB.FIFORP bit masks and bit positions */ #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ @@ -6113,7 +6479,6 @@ #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - /* USB.INTCTRLA bit masks and bit positions */ #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ @@ -6134,7 +6499,6 @@ #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - /* USB.INTCTRLB bit masks and bit positions */ #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ @@ -6142,7 +6506,6 @@ #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - /* USB.INTFLAGSACLR bit masks and bit positions */ #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ @@ -6168,32 +6531,30 @@ #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - /* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF_bm Predefined. */ -/* USB_SOFIF_bp Predefined. */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ -/* USB_SUSPENDIF_bm Predefined. */ -/* USB_SUSPENDIF_bp Predefined. */ +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ -/* USB_RESUMEIF_bm Predefined. */ -/* USB_RESUMEIF_bp Predefined. */ +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ -/* USB_RSTIF_bm Predefined. */ -/* USB_RSTIF_bp Predefined. */ +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ -/* USB_CRCIF_bm Predefined. */ -/* USB_CRCIF_bp Predefined. */ +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ -/* USB_UNFIF_bm Predefined. */ -/* USB_UNFIF_bp Predefined. */ +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ -/* USB_OVFIF_bm Predefined. */ -/* USB_OVFIF_bp Predefined. */ - -/* USB_STALLIF_bm Predefined. */ -/* USB_STALLIF_bp Predefined. */ +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ /* USB.INTFLAGSBCLR bit masks and bit positions */ #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ @@ -6202,14 +6563,12 @@ #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - /* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF_bm Predefined. */ -/* USB_TRNIF_bp Predefined. */ - -/* USB_SETUPIF_bm Predefined. */ -/* USB_SETUPIF_bp Predefined. */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ /* PORT - I/O Port Configuration */ /* PORT.INTCTRL bit masks and bit positions */ @@ -6227,7 +6586,6 @@ #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - /* PORT.INTFLAGS bit masks and bit positions */ #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ @@ -6235,6 +6593,24 @@ #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ /* PORT.PIN0CTRL bit masks and bit positions */ #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ @@ -6261,188 +6637,96 @@ #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - /* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ -/* PORT_INVEN_bm Predefined. */ -/* PORT_INVEN_bp Predefined. */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ -/* PORT_OPC_gm Predefined. */ -/* PORT_OPC_gp Predefined. */ -/* PORT_OPC0_bm Predefined. */ -/* PORT_OPC0_bp Predefined. */ -/* PORT_OPC1_bm Predefined. */ -/* PORT_OPC1_bp Predefined. */ -/* PORT_OPC2_bm Predefined. */ -/* PORT_OPC2_bp Predefined. */ - -/* PORT_ISC_gm Predefined. */ -/* PORT_ISC_gp Predefined. */ -/* PORT_ISC0_bm Predefined. */ -/* PORT_ISC0_bp Predefined. */ -/* PORT_ISC1_bm Predefined. */ -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ /* TC - 16-bit Timer/Counter With PWM */ /* TC0.CTRLA bit masks and bit positions */ @@ -6457,7 +6741,6 @@ #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - /* TC0.CTRLB bit masks and bit positions */ #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ @@ -6480,7 +6763,6 @@ #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - /* TC0.CTRLC bit masks and bit positions */ #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ @@ -6494,7 +6776,6 @@ #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - /* TC0.CTRLD bit masks and bit positions */ #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC0_EVACT_gp 5 /* Event Action group position. */ @@ -6519,11 +6800,13 @@ #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - /* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ /* TC0.INTCTRLA bit masks and bit positions */ #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ @@ -6540,7 +6823,6 @@ #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - /* TC0.INTCTRLB bit masks and bit positions */ #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ @@ -6570,7 +6852,6 @@ #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - /* TC0.CTRLFCLR bit masks and bit positions */ #define TC0_CMD_gm 0x0C /* Command group mask. */ #define TC0_CMD_gp 2 /* Command group position. */ @@ -6585,21 +6866,15 @@ #define TC0_DIR_bm 0x01 /* Direction bit mask. */ #define TC0_DIR_bp 0 /* Direction bit position. */ - /* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ -/* TC0_CMD0_bp Predefined. */ -/* TC0_CMD1_bm Predefined. */ -/* TC0_CMD1_bp Predefined. */ - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ /* TC0.CTRLGCLR bit masks and bit positions */ #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ @@ -6617,23 +6892,21 @@ #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - /* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ /* TC0.INTFLAGS bit masks and bit positions */ #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ @@ -6654,7 +6927,6 @@ #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - /* TC1.CTRLA bit masks and bit positions */ #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ @@ -6667,7 +6939,6 @@ #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - /* TC1.CTRLB bit masks and bit positions */ #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ @@ -6684,7 +6955,6 @@ #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - /* TC1.CTRLC bit masks and bit positions */ #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ @@ -6692,7 +6962,6 @@ #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - /* TC1.CTRLD bit masks and bit positions */ #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ #define TC1_EVACT_gp 5 /* Event Action group position. */ @@ -6717,12 +6986,10 @@ #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - /* TC1.CTRLE bit masks and bit positions */ #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - /* TC1.INTCTRLA bit masks and bit positions */ #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ @@ -6738,7 +7005,6 @@ #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - /* TC1.INTCTRLB bit masks and bit positions */ #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ @@ -6754,7 +7020,6 @@ #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - /* TC1.CTRLFCLR bit masks and bit positions */ #define TC1_CMD_gm 0x0C /* Command group mask. */ #define TC1_CMD_gp 2 /* Command group position. */ @@ -6769,21 +7034,15 @@ #define TC1_DIR_bm 0x01 /* Direction bit mask. */ #define TC1_DIR_bp 0 /* Direction bit position. */ - /* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ -/* TC1_CMD0_bp Predefined. */ -/* TC1_CMD1_bm Predefined. */ -/* TC1_CMD1_bp Predefined. */ - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ /* TC1.CTRLGCLR bit masks and bit positions */ #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ @@ -6795,17 +7054,15 @@ #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - /* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ - -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ /* TC1.INTFLAGS bit masks and bit positions */ #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ @@ -6820,6 +7077,154 @@ #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ /* AWEX - Timer/Counter Advanced Waveform Extension */ /* AWEX.CTRL bit masks and bit positions */ @@ -6841,7 +7246,6 @@ #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - /* AWEX.FDCTRL bit masks and bit positions */ #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ @@ -6856,7 +7260,6 @@ #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - /* AWEX.STATUS bit masks and bit positions */ #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ @@ -6867,6 +7270,15 @@ #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ /* HIRES - Timer/Counter High-Resolution Extension */ /* HIRES.CTRLA bit masks and bit positions */ @@ -6877,7 +7289,6 @@ #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - /* USART - Universal Asynchronous Receiver-Transmitter */ /* USART.STATUS bit masks and bit positions */ #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ @@ -6901,7 +7312,6 @@ #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - /* USART.CTRLA bit masks and bit positions */ #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ @@ -6924,7 +7334,6 @@ #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - /* USART.CTRLB bit masks and bit positions */ #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ @@ -6941,7 +7350,6 @@ #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - /* USART.CTRLC bit masks and bit positions */ #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ #define USART_CMODE_gp 6 /* Communication Mode group position. */ @@ -6969,7 +7377,6 @@ #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - /* USART.BAUDCTRLA bit masks and bit positions */ #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ @@ -6990,7 +7397,6 @@ #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - /* USART.BAUDCTRLB bit masks and bit positions */ #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ @@ -7003,17 +7409,8 @@ #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ -/* USART_BSEL0_bp Predefined. */ -/* USART_BSEL1_bm Predefined. */ -/* USART_BSEL1_bp Predefined. */ -/* USART_BSEL2_bm Predefined. */ -/* USART_BSEL2_bp Predefined. */ -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ /* SPI - Serial Peripheral Interface */ /* SPI.CTRL bit masks and bit positions */ @@ -7043,7 +7440,6 @@ #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - /* SPI.INTCTRL bit masks and bit positions */ #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ @@ -7052,7 +7448,6 @@ #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - /* SPI.STATUS bit masks and bit positions */ #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ @@ -7060,7 +7455,6 @@ #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - /* IRCOM - IR Communication Module */ /* IRCOM.CTRL bit masks and bit positions */ #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ @@ -7074,34 +7468,152 @@ #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* PRESC - Prescaler */ -/* PRESC.PRESCALER bit masks and bit positions */ -#define PRESC_RESET_bm 0x01 /* Reset bit mask. */ -#define PRESC_RESET_bp 0 /* Reset bit position. */ +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ // Generic Port Pins -#define PIN0_bm 0x01 +#define PIN0_bm 0x01 #define PIN0_bp 0 #define PIN1_bm 0x02 #define PIN1_bp 1 -#define PIN2_bm 0x04 +#define PIN2_bm 0x04 #define PIN2_bp 2 -#define PIN3_bm 0x08 +#define PIN3_bm 0x08 #define PIN3_bp 3 -#define PIN4_bm 0x10 +#define PIN4_bm 0x10 #define PIN4_bp 4 -#define PIN5_bm 0x20 +#define PIN5_bm 0x20 #define PIN5_bp 5 -#define PIN6_bm 0x40 +#define PIN6_bm 0x40 #define PIN6_bp 6 -#define PIN7_bm 0x80 +#define PIN7_bm 0x80 #define PIN7_bp 7 - /* ========== Interrupt Vector Definitions ========== */ /* Vector 0 is the reset vector */ @@ -7146,17 +7658,51 @@ /* TCC0 interrupt vectors */ #define TCC0_OVF_vect_num 14 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_ERR_vect_num 15 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCA_vect_num 16 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCB_vect_num 17 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCC_vect_num 18 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ #define TCC0_CCD_vect_num 19 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + /* TCC1 interrupt vectors */ #define TCC1_OVF_vect_num 20 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ @@ -7236,17 +7782,51 @@ /* TCE0 interrupt vectors */ #define TCE0_OVF_vect_num 47 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_ERR_vect_num 48 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCA_vect_num 49 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCB_vect_num 50 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCC_vect_num 51 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ #define TCE0_CCD_vect_num 52 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + /* TCE1 interrupt vectors */ #define TCE1_OVF_vect_num 53 #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ @@ -7316,17 +7896,51 @@ /* TCD0 interrupt vectors */ #define TCD0_OVF_vect_num 77 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_ERR_vect_num 78 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCA_vect_num 79 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCB_vect_num 80 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCC_vect_num 81 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ #define TCD0_CCD_vect_num 82 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + /* TCD1 interrupt vectors */ #define TCD1_OVF_vect_num 83 #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ @@ -7396,17 +8010,51 @@ /* TCF0 interrupt vectors */ #define TCF0_OVF_vect_num 108 #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_ERR_vect_num 109 #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCA_vect_num 110 #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCB_vect_num 111 #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCC_vect_num 112 #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ #define TCF0_CCD_vect_num 113 #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + /* TCF1 interrupt vectors */ #define TCF1_OVF_vect_num 114 #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ @@ -7449,34 +8097,27 @@ /* ========== Constants ========== */ -#define PROGMEM_START (0x00000) +#define PROGMEM_START (0x0000) #define PROGMEM_SIZE (69632) -#define PROGMEM_PAGE_SIZE (512) #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -#define APP_SECTION_START (0x00000) +#define APP_SECTION_START (0x0000) #define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_PAGE_SIZE (256) #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_START (0xF000) #define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_PAGE_SIZE (256) #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_START (0x10000) #define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_PAGE_SIZE (256) #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - #define DATAMEM_START (0x0000) #define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) #define IO_START (0x0000) @@ -7494,51 +8135,96 @@ #define INTERNAL_SRAM_PAGE_SIZE (0) #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -#define EXTERNAL_SRAM_START (0x4000) -#define EXTERNAL_SRAM_SIZE (16760832) -#define EXTERNAL_SRAM_PAGE_SIZE (0) -#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) - -#define FUSE_START (0x0000) -#define FUSE_SIZE (6) -#define FUSE_PAGE_SIZE (0) -#define FUSE_END (FUSE_START + FUSE_SIZE - 1) - -#define LOCKBIT_START (0x0000) -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) #define SIGNATURES_START (0x0000) #define SIGNATURES_SIZE (3) #define SIGNATURES_PAGE_SIZE (0) #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + #define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) #define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +#define FLASHSTART PROGMEM_START #define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define SPM_PAGESIZE 256 #define RAMSTART INTERNAL_SRAM_START #define RAMSIZE INTERNAL_SRAM_SIZE #define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END #define E2END EEPROM_END #define E2PAGESIZE EEPROM_PAGE_SIZE /* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 0 +#define FUSE_MEMORY_SIZE 6 +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) /* ========== Lock Bits ========== */ #define __LOCK_BITS_EXIST @@ -7546,7 +8232,6 @@ #define __BOOT_LOCK_APPLICATION_BITS_EXIST #define __BOOT_LOCK_BOOT_BITS_EXIST - /* ========== Signature ========== */ #define SIGNATURE_0 0x1E #define SIGNATURE_1 0x96 @@ -7615,5 +8300,6 @@ #define __AVR_HAVE_PRPF_TC1 #define __AVR_HAVE_PRPF_TC0 -#endif /* _AVR_ATxmega64A1U_H_ */ + +#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64a3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64a3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ /* avr/iox64a3.h - definitions for ATxmega64A3 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64a3u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64a3u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -7007,14 +7004,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7613,9 +7610,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64a4u.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64a4u.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -301,13 +299,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -1111,7 +1108,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -1294,18 +1291,18 @@ /* Negative input multiplexer selection */ typedef enum ADC_CH_MUXNEG_enum { - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ - ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ - ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ } ADC_CH_MUXNEG_t; /* Input mode */ @@ -2702,7 +2699,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2725,7 +2722,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6765,14 +6762,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -7225,9 +7222,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64b1.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64b1.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -264,13 +262,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -958,7 +955,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2374,7 +2371,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2397,7 +2394,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -6036,14 +6033,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6398,9 +6395,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64b3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64b3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -264,13 +262,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -958,7 +955,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2374,7 +2371,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2397,7 +2394,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5916,14 +5913,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6232,9 +6229,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64c3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64c3.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -277,13 +275,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -792,7 +789,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2266,7 +2263,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2289,7 +2286,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5699,14 +5696,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -6201,9 +6198,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64d3.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64d3.h @@ -28,7 +28,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* $Id$ */ +/* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ /* avr/iox64d3.h - definitions for ATxmega64D3 */ @@ -887,12 +887,13 @@ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ - BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ } BODLVL_t; --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox64d4.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox64d4.h @@ -1,6 +1,6 @@ /***************************************************************************** * - * Copyright (C) 2014 Atmel Corporation + * Copyright (C) 2015 Atmel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,8 +32,6 @@ ****************************************************************************/ -/* $Id$ */ - #ifndef _AVR_IO_H_ # error "Include instead of this file." #endif @@ -259,13 +257,12 @@ } SLEEP_SMODE_t; + #define SLEEP_MODE_IDLE (0x00<<1) #define SLEEP_MODE_PWR_DOWN (0x02<<1) #define SLEEP_MODE_PWR_SAVE (0x03<<1) #define SLEEP_MODE_STANDBY (0x06<<1) #define SLEEP_MODE_EXT_STANDBY (0x07<<1) - - /* -------------------------------------------------------------------------- OSC - Oscillator @@ -772,7 +769,7 @@ register8_t INTCTRL; /* Interrupt Control */ register8_t reserved_0x0E; register8_t STATUS; /* Status */ - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_t; /* NVM Command */ @@ -2073,7 +2070,7 @@ SUT_64MS_gc = (0x00<<2), /* 64 ms */ } SUT_t; -/* Brown Out Detection Voltage Level */ +/* Brownout Detection Voltage Level */ typedef enum BODLVL_enum { BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ @@ -2096,7 +2093,7 @@ /* Lock Bits */ typedef struct NVM_LOCKBITS_struct { - register8_t LOCKBITS; /* Lock Bits */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ } NVM_LOCKBITS_t; /* Boot lock bits - boot setcion */ @@ -5088,14 +5085,14 @@ #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ /* LOCKBIT - Fuses and Lockbits */ /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ @@ -5496,9 +5493,9 @@ #define FUSE4_DEFAULT (0xFF) /* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/include/avr/iox8e5.h +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/include/avr/iox8e5.h @@ -1,7699 +1,7699 @@ -/***************************************************************************** - * - * Copyright (C) 2016 Atmel Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _AVR_IO_H_ -# error "Include instead of this file." -#endif - -#ifndef _AVR_IOXXX_H_ -# define _AVR_IOXXX_H_ "iox8e5.h" -#else -# error "Attempt to include more than one file." -#endif - -#ifndef _AVR_ATXMEGA8E5_H_INCLUDED -#define _AVR_ATXMEGA8E5_H_INCLUDED - -/* Ungrouped common registers */ -#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -/* Deprecated */ -#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ - -#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -#define SREG _SFR_MEM8(0x003F) /* Status Register */ - -/* C Language Only */ -#if !defined (__ASSEMBLER__) - -#include - -typedef volatile uint8_t register8_t; -typedef volatile uint16_t register16_t; -typedef volatile uint32_t register32_t; - - -#ifdef _WORDREGISTER -#undef _WORDREGISTER -#endif -#define _WORDREGISTER(regname) \ - __extension__ union \ - { \ - register16_t regname; \ - struct \ - { \ - register8_t regname ## L; \ - register8_t regname ## H; \ - }; \ - } - -#ifdef _DWORDREGISTER -#undef _DWORDREGISTER -#endif -#define _DWORDREGISTER(regname) \ - __extension__ union \ - { \ - register32_t regname; \ - struct \ - { \ - register8_t regname ## 0; \ - register8_t regname ## 1; \ - register8_t regname ## 2; \ - register8_t regname ## 3; \ - }; \ - } - - -/* -========================================================================== -IO Module Structures -========================================================================== -*/ - - -/* --------------------------------------------------------------------------- -VPORT - Virtual Ports --------------------------------------------------------------------------- -*/ - -/* Virtual Port */ -typedef struct VPORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t OUT; /* I/O Port Output */ - register8_t IN; /* I/O Port Input */ - register8_t INTFLAGS; /* Interrupt Flag Register */ -} VPORT_t; - - -/* --------------------------------------------------------------------------- -XOCD - On-Chip Debug System --------------------------------------------------------------------------- -*/ - -/* On-Chip Debug System */ -typedef struct OCD_struct -{ - register8_t OCDR0; /* OCD Register 0 */ - register8_t OCDR1; /* OCD Register 1 */ -} OCD_t; - - -/* --------------------------------------------------------------------------- -CPU - CPU --------------------------------------------------------------------------- -*/ - -/* CCP signatures */ -typedef enum CCP_enum -{ - CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ - CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -} CCP_t; - - -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - -/* Clock System */ -typedef struct CLK_struct -{ - register8_t CTRL; /* Control Register */ - register8_t PSCTRL; /* Prescaler Control Register */ - register8_t LOCK; /* Lock register */ - register8_t RTCCTRL; /* RTC Control Register */ - register8_t reserved_0x04; -} CLK_t; - - -/* Power Reduction */ -typedef struct PR_struct -{ - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ - register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t reserved_0x05; - register8_t reserved_0x06; -} PR_t; - -/* System Clock Selection */ -typedef enum CLK_SCLKSEL_enum -{ - CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ - CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ - CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ - CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ - CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ - CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -} CLK_SCLKSEL_t; - -/* Prescaler A Division Factor */ -typedef enum CLK_PSADIV_enum -{ - CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ - CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ - CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ - CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ - CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ - CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ - CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ - CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ - CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ - CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ - CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ - CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ - CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ - CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ - CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -} CLK_PSADIV_t; - -/* Prescaler B and C Division Factor */ -typedef enum CLK_PSBCDIV_enum -{ - CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ - CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ - CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ - CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -} CLK_PSBCDIV_t; - -/* RTC Clock Source */ -typedef enum CLK_RTCSRC_enum -{ - CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ - CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ - CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ - CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -} CLK_RTCSRC_t; - - -/* --------------------------------------------------------------------------- -SLEEP - Sleep Controller --------------------------------------------------------------------------- -*/ - -/* Sleep Controller */ -typedef struct SLEEP_struct -{ - register8_t CTRL; /* Control Register */ -} SLEEP_t; - -/* Sleep Mode */ -typedef enum SLEEP_SMODE_enum -{ - SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ - SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ - SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ - SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ - SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -} SLEEP_SMODE_t; - - - -#define SLEEP_MODE_IDLE (0x00<<1) -#define SLEEP_MODE_PWR_DOWN (0x02<<1) -#define SLEEP_MODE_PWR_SAVE (0x03<<1) -#define SLEEP_MODE_STANDBY (0x06<<1) -#define SLEEP_MODE_EXT_STANDBY (0x07<<1) -/* --------------------------------------------------------------------------- -OSC - Oscillator --------------------------------------------------------------------------- -*/ - -/* Oscillator */ -typedef struct OSC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -} OSC_t; - -/* Oscillator Frequency Range */ -typedef enum OSC_FRQRANGE_enum -{ - OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ - OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ - OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ - OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -} OSC_FRQRANGE_t; - -/* External Oscillator Selection and Startup Time */ -typedef enum OSC_XOSCSEL_enum -{ - OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ - OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ - OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ - OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ - OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ - OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -} OSC_XOSCSEL_t; - -/* PLL Clock Source */ -typedef enum OSC_PLLSRC_enum -{ - OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ - OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ - OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -} OSC_PLLSRC_t; - -/* 32 MHz DFLL Calibration Reference */ -typedef enum OSC_RC32MCREF_enum -{ - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -} OSC_RC32MCREF_t; - - -/* --------------------------------------------------------------------------- -DFLL - DFLL --------------------------------------------------------------------------- -*/ - -/* DFLL */ -typedef struct DFLL_struct -{ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x01; - register8_t CALA; /* Calibration Register A */ - register8_t CALB; /* Calibration Register B */ - register8_t COMP0; /* Oscillator Compare Register 0 */ - register8_t COMP1; /* Oscillator Compare Register 1 */ - register8_t COMP2; /* Oscillator Compare Register 2 */ - register8_t reserved_0x07; -} DFLL_t; - - -/* --------------------------------------------------------------------------- -RST - Reset --------------------------------------------------------------------------- -*/ - -/* Reset */ -typedef struct RST_struct -{ - register8_t STATUS; /* Status Register */ - register8_t CTRL; /* Control Register */ -} RST_t; - - -/* --------------------------------------------------------------------------- -WDT - Watch-Dog Timer --------------------------------------------------------------------------- -*/ - -/* Watch-Dog Timer */ -typedef struct WDT_struct -{ - register8_t CTRL; /* Control */ - register8_t WINCTRL; /* Windowed Mode Control */ - register8_t STATUS; /* Status */ -} WDT_t; - -/* Period setting */ -typedef enum WDT_PER_enum -{ - WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_PER_t; - -/* Closed window period */ -typedef enum WDT_WPER_enum -{ - WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ - WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ - WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ - WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -} WDT_WPER_t; - - -/* --------------------------------------------------------------------------- -MCU - MCU Control --------------------------------------------------------------------------- -*/ - -/* MCU Control */ -typedef struct MCU_struct -{ - register8_t DEVID0; /* Device ID byte 0 */ - register8_t DEVID1; /* Device ID byte 1 */ - register8_t DEVID2; /* Device ID byte 2 */ - register8_t REVID; /* Revision ID */ - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t ANAINIT; /* Analog Startup Delay */ - register8_t EVSYSLOCK; /* Event System Lock */ - register8_t WEXLOCK; /* WEX Lock */ - register8_t FAULTLOCK; /* FAULT Lock */ - register8_t reserved_0x0B; -} MCU_t; - - -/* --------------------------------------------------------------------------- -PMIC - Programmable Multi-level Interrupt Controller --------------------------------------------------------------------------- -*/ - -/* Programmable Multi-level Interrupt Controller */ -typedef struct PMIC_struct -{ - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ - register8_t reserved_0x03; - register8_t reserved_0x04; - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} PMIC_t; - - -/* --------------------------------------------------------------------------- -PORTCFG - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O port Configuration */ -typedef struct PORTCFG_struct -{ - register8_t MPCMASK; /* Multi-pin Configuration Mask */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t reserved_0x03; - register8_t CLKOUT; /* Clock Out Register */ - register8_t reserved_0x05; - register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ - register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -} PORTCFG_t; - -/* Clock and Event Output Port */ -typedef enum PORTCFG_CLKEVPIN_enum -{ - PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ - PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -} PORTCFG_CLKEVPIN_t; - -/* RTC Clock Output Port */ -typedef enum PORTCFG_RTCCLKOUT_enum -{ - PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ - PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ - PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ - PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -} PORTCFG_RTCCLKOUT_t; - -/* Peripheral Clock Output Select */ -typedef enum PORTCFG_CLKOUTSEL_enum -{ - PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ - PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -} PORTCFG_CLKOUTSEL_t; - -/* System Clock Output Port */ -typedef enum PORTCFG_CLKOUT_enum -{ - PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ - PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ - PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ - PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -} PORTCFG_CLKOUT_t; - -/* Analog Comparator Output Port */ -typedef enum PORTCFG_ACOUT_enum -{ - PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ - PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ - PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ - PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -} PORTCFG_ACOUT_t; - -/* Event Output Port */ -typedef enum PORTCFG_EVOUT_enum -{ - PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ - PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ - PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ - PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -} PORTCFG_EVOUT_t; - -/* Event Output Select */ -typedef enum PORTCFG_EVOUTSEL_enum -{ - PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ - PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ - PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ - PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ - PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ - PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ - PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ - PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -} PORTCFG_EVOUTSEL_t; - - -/* --------------------------------------------------------------------------- -CRC - Cyclic Redundancy Checker --------------------------------------------------------------------------- -*/ - -/* Cyclic Redundancy Checker */ -typedef struct CRC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t reserved_0x02; - register8_t DATAIN; /* Data Input */ - register8_t CHECKSUM0; /* Checksum byte 0 */ - register8_t CHECKSUM1; /* Checksum byte 1 */ - register8_t CHECKSUM2; /* Checksum byte 2 */ - register8_t CHECKSUM3; /* Checksum byte 3 */ -} CRC_t; - -/* Reset */ -typedef enum CRC_RESET_enum -{ - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ - CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -} CRC_RESET_t; - -/* Input Source */ -typedef enum CRC_SOURCE_enum -{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ - CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ - CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ - CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -} CRC_SOURCE_t; - - -/* --------------------------------------------------------------------------- -EDMA - Enhanced DMA Controller --------------------------------------------------------------------------- -*/ - -/* EDMA Channel */ -typedef struct EDMA_CH_struct -{ - register8_t CTRLA; /* Channel Control A */ - register8_t CTRLB; /* Channel Control */ - register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ - register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ - register8_t TRIGSRC; /* Channel Trigger Source */ - register8_t reserved_0x05; - _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ - _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} EDMA_CH_t; - - -/* Enhanced DMA Controller */ -typedef struct EDMA_struct -{ - register8_t CTRL; /* Control */ - register8_t reserved_0x01; - register8_t reserved_0x02; - register8_t INTFLAGS; /* Transfer Interrupt Status */ - register8_t STATUS; /* Status */ - register8_t reserved_0x05; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - EDMA_CH_t CH0; /* EDMA Channel 0 */ - EDMA_CH_t CH1; /* EDMA Channel 1 */ - EDMA_CH_t CH2; /* EDMA Channel 2 */ - EDMA_CH_t CH3; /* EDMA Channel 3 */ -} EDMA_t; - -/* Channel mode */ -typedef enum EDMA_CHMODE_enum -{ - EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ - EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ - EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ - EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -} EDMA_CHMODE_t; - -/* Double buffer mode */ -typedef enum EDMA_DBUFMODE_enum -{ - EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ - EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ - EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ - EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -} EDMA_DBUFMODE_t; - -/* Priority mode */ -typedef enum EDMA_PRIMODE_enum -{ - EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ - EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ - EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ - EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -} EDMA_PRIMODE_t; - -/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -typedef enum EDMA_CH_RELOAD_enum -{ - EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ - EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ - EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ - EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -} EDMA_CH_RELOAD_t; - -/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -typedef enum EDMA_CH_DIR_enum -{ - EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ - EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -} EDMA_CH_DIR_t; - -/* Destination addressing mode */ -typedef enum EDMA_CH_DESTDIR_enum -{ - EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ - EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ - EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ - EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ - EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -} EDMA_CH_DESTDIR_t; - -/* Transfer trigger source */ -typedef enum EDMA_CH_TRIGSRC_enum -{ - EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ - EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ - EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ - EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ - EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ - EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ - EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ - EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ - EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -} EDMA_CH_TRIGSRC_t; - -/* Interrupt level */ -typedef enum EDMA_CH_INTLVL_enum -{ - EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ - EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ - EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -} EDMA_CH_INTLVL_t; - - -/* --------------------------------------------------------------------------- -EVSYS - Event System --------------------------------------------------------------------------- -*/ - -/* Event System */ -typedef struct EVSYS_struct -{ - register8_t CH0MUX; /* Event Channel 0 Multiplexer */ - register8_t CH1MUX; /* Event Channel 1 Multiplexer */ - register8_t CH2MUX; /* Event Channel 2 Multiplexer */ - register8_t CH3MUX; /* Event Channel 3 Multiplexer */ - register8_t CH4MUX; /* Event Channel 4 Multiplexer */ - register8_t CH5MUX; /* Event Channel 5 Multiplexer */ - register8_t CH6MUX; /* Event Channel 6 Multiplexer */ - register8_t CH7MUX; /* Event Channel 7 Multiplexer */ - register8_t CH0CTRL; /* Channel 0 Control Register */ - register8_t CH1CTRL; /* Channel 1 Control Register */ - register8_t CH2CTRL; /* Channel 2 Control Register */ - register8_t CH3CTRL; /* Channel 3 Control Register */ - register8_t CH4CTRL; /* Channel 4 Control Register */ - register8_t CH5CTRL; /* Channel 5 Control Register */ - register8_t CH6CTRL; /* Channel 6 Control Register */ - register8_t CH7CTRL; /* Channel 7 Control Register */ - register8_t STROBE; /* Event Strobe */ - register8_t DATA; /* Event Data */ - register8_t DFCTRL; /* Digital Filter Control Register */ -} EVSYS_t; - -/* Event Channel multiplexer input selection */ -typedef enum EVSYS_CHMUX_enum -{ - EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ - EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ - EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ - EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ - EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ - EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ - EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ - EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ - EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ - EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ - EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ - EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ - EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ - EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ - EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ - EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ - EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ - EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ - EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ - EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ - EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ - EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ - EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ - EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ - EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ - EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ - EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ - EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ - EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ - EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ - EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ - EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ - EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ - EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ - EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ - EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ - EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ - EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ - EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ - EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ - EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ - EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ - EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ - EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ - EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ - EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ - EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ - EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ - EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ - EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ - EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ - EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ - EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ - EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ - EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ - EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ - EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ - EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ - EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ - EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ - EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ - EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ - EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ - EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ - EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ - EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ - EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ - EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -} EVSYS_CHMUX_t; - -/* Quadrature Decoder Index Recognition Mode */ -typedef enum EVSYS_QDIRM_enum -{ - EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ - EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ - EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ - EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -} EVSYS_QDIRM_t; - -/* Digital filter coefficient */ -typedef enum EVSYS_DIGFILT_enum -{ - EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ - EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ - EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ - EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ - EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ - EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ - EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ - EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -} EVSYS_DIGFILT_t; - -/* Prescaler Filter */ -typedef enum EVSYS_PRESCFILT_enum -{ - EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ - EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ - EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ - EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -} EVSYS_PRESCFILT_t; - -/* Prescaler */ -typedef enum EVSYS_PRESCALER_enum -{ - EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ - EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ - EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ - EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ - EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -} EVSYS_PRESCALER_t; - - -/* --------------------------------------------------------------------------- -NVM - Non Volatile Memory Controller --------------------------------------------------------------------------- -*/ - -/* Non-volatile Memory Controller */ -typedef struct NVM_struct -{ - register8_t ADDR0; /* Address Register 0 */ - register8_t ADDR1; /* Address Register 1 */ - register8_t ADDR2; /* Address Register 2 */ - register8_t reserved_0x03; - register8_t DATA0; /* Data Register 0 */ - register8_t DATA1; /* Data Register 1 */ - register8_t DATA2; /* Data Register 2 */ - register8_t reserved_0x07; - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t CMD; /* Command */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t INTCTRL; /* Interrupt Control */ - register8_t reserved_0x0E; - register8_t STATUS; /* Status */ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_t; - -/* NVM Command */ -typedef enum NVM_CMD_enum -{ - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ - NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ - NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ - NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ - NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ - NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ - NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ - NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ - NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ - NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ - NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ - NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ - NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ - NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ - NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ - NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ - NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -} NVM_CMD_t; - -/* SPM ready interrupt level */ -typedef enum NVM_SPMLVL_enum -{ - NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ - NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ - NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ - NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -} NVM_SPMLVL_t; - -/* EEPROM ready interrupt level */ -typedef enum NVM_EELVL_enum -{ - NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ - NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ - NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -} NVM_EELVL_t; - -/* Boot lock bits - boot setcion */ -typedef enum NVM_BLBB_enum -{ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} NVM_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum NVM_BLBA_enum -{ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} NVM_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum NVM_BLBAT_enum -{ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} NVM_BLBAT_t; - -/* Lock bits */ -typedef enum NVM_LB_enum -{ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} NVM_LB_t; - - -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - -/* ADC Channel */ -typedef struct ADC_CH_struct -{ - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ - register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ - register8_t SCAN; /* Input Channel Scan */ - register8_t CORRCTRL; /* Correction Control Register */ - register8_t OFFSETCORR0; /* Offset Correction Register 0 */ - register8_t OFFSETCORR1; /* Offset Correction Register 1 */ - register8_t GAINCORR0; /* Gain Correction Register 0 */ - register8_t GAINCORR1; /* Gain Correction Register 1 */ - register8_t AVGCTRL; /* Average Control Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; -} ADC_CH_t; - - -/* Analog-to-Digital Converter */ -typedef struct ADC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t REFCTRL; /* Reference Control */ - register8_t EVCTRL; /* Event Control */ - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary Register */ - register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ - register8_t reserved_0x09; - register8_t reserved_0x0A; - register8_t reserved_0x0B; - _WORDREGISTER(CAL); /* Calibration Value */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - _WORDREGISTER(CH0RES); /* Channel 0 Result */ - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CMP); /* Compare Value */ - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - ADC_CH_t CH0; /* ADC Channel 0 */ -} ADC_t; - -/* Current Limitation */ -typedef enum ADC_CURRLIMIT_enum -{ - ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ - ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ - ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ - ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -} ADC_CURRLIMIT_t; - -/* Conversion result resolution */ -typedef enum ADC_RESOLUTION_enum -{ - ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ - ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ - ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -} ADC_RESOLUTION_t; - -/* Voltage reference selection */ -typedef enum ADC_REFSEL_enum -{ - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ - ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -} ADC_REFSEL_t; - -/* Event channel input selection */ -typedef enum ADC_EVSEL_enum -{ - ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ - ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ - ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ - ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ - ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ - ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ - ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ - ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -} ADC_EVSEL_t; - -/* Event action selection */ -typedef enum ADC_EVACT_enum -{ - ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ - ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ - ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -} ADC_EVACT_t; - -/* Clock prescaler */ -typedef enum ADC_PRESCALER_enum -{ - ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ - ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ - ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ - ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ - ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ - ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ - ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ - ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -} ADC_PRESCALER_t; - -/* Gain factor */ -typedef enum ADC_CH_GAIN_enum -{ - ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ - ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ - ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ - ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -} ADC_CH_GAIN_t; - -/* Input mode */ -typedef enum ADC_CH_INPUTMODE_enum -{ - ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ - ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ - ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ - ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -} ADC_CH_INPUTMODE_t; - -/* Positive input multiplexer selection */ -typedef enum ADC_CH_MUXPOS_enum -{ - ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ - ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ - ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ - ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ - ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ - ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ - ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ - ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ - ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ - ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ - ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ - ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ - ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ - ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ - ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ - ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -} ADC_CH_MUXPOS_t; - -/* Internal input multiplexer selections */ -typedef enum ADC_CH_MUXINT_enum -{ - ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ - ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ - ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ - ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -} ADC_CH_MUXINT_t; - -/* Negative input multiplexer selection when gain on 4 LSB pins */ -typedef enum ADC_CH_MUXNEGL_enum -{ - ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ - ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ - ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ - ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ - ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ - ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -} ADC_CH_MUXNEGL_t; - -/* Negative input multiplexer selection when gain on 4 MSB pins */ -typedef enum ADC_CH_MUXNEGH_enum -{ - ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ - ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ - ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -} ADC_CH_MUXNEGH_t; - -/* Negative input multiplexer selection */ -typedef enum ADC_CH_MUXNEG_enum -{ - ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -} ADC_CH_MUXNEG_t; - -/* Interupt mode */ -typedef enum ADC_CH_INTMODE_enum -{ - ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ - ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ - ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -} ADC_CH_INTMODE_t; - -/* Interrupt level */ -typedef enum ADC_CH_INTLVL_enum -{ - ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ - ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ - ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -} ADC_CH_INTLVL_t; - -/* Averaged Number of Samples */ -typedef enum ADC_SAMPNUM_enum -{ - ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ - ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ - ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ - ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ - ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ - ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ - ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ - ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ - ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ - ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ - ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -} ADC_SAMPNUM_t; - - -/* --------------------------------------------------------------------------- -DAC - Digital/Analog Converter --------------------------------------------------------------------------- -*/ - -/* Digital-to-Analog Converter */ -typedef struct DAC_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ - register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t CH0GAINCAL; /* Gain Calibration */ - register8_t CH0OFFSETCAL; /* Offset Calibration */ - register8_t CH1GAINCAL; /* Gain Calibration */ - register8_t CH1OFFSETCAL; /* Offset Calibration */ - register8_t reserved_0x0C; - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - _WORDREGISTER(CH0DATA); /* Channel 0 Data */ - _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -} DAC_t; - -/* Output channel selection */ -typedef enum DAC_CHSEL_enum -{ - DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ - DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ - DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -} DAC_CHSEL_t; - -/* Reference voltage selection */ -typedef enum DAC_REFSEL_enum -{ - DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ - DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ - DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ - DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -} DAC_REFSEL_t; - -/* Event channel selection */ -typedef enum DAC_EVSEL_enum -{ - DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ - DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ - DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ - DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ - DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ - DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ - DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -} DAC_EVSEL_t; - - -/* --------------------------------------------------------------------------- -AC - Analog Comparator --------------------------------------------------------------------------- -*/ - -/* Analog Comparator */ -typedef struct AC_struct -{ - register8_t AC0CTRL; /* Analog Comparator 0 Control */ - register8_t AC1CTRL; /* Analog Comparator 1 Control */ - register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ - register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t WINCTRL; /* Window Mode Control */ - register8_t STATUS; /* Status */ - register8_t CURRCTRL; /* Current Source Control Register */ - register8_t CURRCALIB; /* Current Source Calibration Register */ -} AC_t; - -/* Interrupt mode */ -typedef enum AC_INTMODE_enum -{ - AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ - AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ - AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -} AC_INTMODE_t; - -/* Interrupt level */ -typedef enum AC_INTLVL_enum -{ - AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ - AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ - AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ - AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -} AC_INTLVL_t; - -/* Hysteresis mode selection */ -typedef enum AC_HYSMODE_enum -{ - AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ - AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ - AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -} AC_HYSMODE_t; - -/* Positive input multiplexer selection */ -typedef enum AC_MUXPOS_enum -{ - AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ - AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ - AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ - AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ - AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ - AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ - AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ - AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -} AC_MUXPOS_t; - -/* Negative input multiplexer selection */ -typedef enum AC_MUXNEG_enum -{ - AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ - AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ - AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ - AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ - AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ - AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ - AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ - AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -} AC_MUXNEG_t; - -/* Windows interrupt mode */ -typedef enum AC_WINTMODE_enum -{ - AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ - AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ - AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ - AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -} AC_WINTMODE_t; - -/* Window interrupt level */ -typedef enum AC_WINTLVL_enum -{ - AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ - AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ - AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ - AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -} AC_WINTLVL_t; - -/* Window mode state */ -typedef enum AC_WSTATE_enum -{ - AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ - AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ - AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -} AC_WSTATE_t; - - -/* --------------------------------------------------------------------------- -RTC - Real-Time Clounter --------------------------------------------------------------------------- -*/ - -/* Real-Time Counter */ -typedef struct RTC_struct -{ - register8_t CTRL; /* Control Register */ - register8_t STATUS; /* Status Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ - register8_t reserved_0x05; - register8_t CALIB; /* Calibration Register */ - register8_t reserved_0x07; - _WORDREGISTER(CNT); /* Count Register */ - _WORDREGISTER(PER); /* Period Register */ - _WORDREGISTER(COMP); /* Compare Register */ -} RTC_t; - -/* Prescaler Factor */ -typedef enum RTC_PRESCALER_enum -{ - RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ - RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ - RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ - RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ - RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ - RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ - RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ - RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -} RTC_PRESCALER_t; - -/* Compare Interrupt level */ -typedef enum RTC_COMPINTLVL_enum -{ - RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ - RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -} RTC_COMPINTLVL_t; - -/* Overflow Interrupt level */ -typedef enum RTC_OVFINTLVL_enum -{ - RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} RTC_OVFINTLVL_t; - - -/* --------------------------------------------------------------------------- -XCL - XMEGA Custom Logic --------------------------------------------------------------------------- -*/ - -/* XMEGA Custom Logic */ -typedef struct XCL_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t CTRLG; /* Control Register G */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t PLC; /* Peripheral Lenght Control Register */ - register8_t CNTL; /* Counter Register Low */ - register8_t CNTH; /* Counter Register High */ - register8_t CMPL; /* Compare Register Low */ - register8_t CMPH; /* Compare Register High */ - register8_t PERCAPTL; /* Period or Capture Register Low */ - register8_t PERCAPTH; /* Period or Capture Register High */ -} XCL_t; - -/* LUT0 Output Enable */ -typedef enum XCL_LUTOUTEN_enum -{ - XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ - XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ - XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -} XCL_LUTOUTEN_t; - -/* Port Selection */ -typedef enum XCL_PORTSEL_enum -{ - XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ - XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -} XCL_PORTSEL_t; - -/* LUT Configuration */ -typedef enum XCL_LUTCONF_enum -{ - XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ - XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ - XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ - XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ - XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ - XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ - XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ - XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -} XCL_LUTCONF_t; - -/* Input Selection */ -typedef enum XCL_INSEL_enum -{ - XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ - XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ - XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ - XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -} XCL_INSEL_t; - -/* Delay Configuration on LUT */ -typedef enum XCL_DLYCONF_enum -{ - XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ - XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ - XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -} XCL_DLYCONF_t; - -/* Delay Selection */ -typedef enum XCL_DLYSEL_enum -{ - XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ - XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ - XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ - XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -} XCL_DLYSEL_t; - -/* Clock Selection */ -typedef enum XCL_CLKSEL_enum -{ - XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ - XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ - XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ - XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ - XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ - XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ - XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ - XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ - XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ - XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ - XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ - XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ - XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ - XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ - XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ - XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -} XCL_CLKSEL_t; - -/* Timer/Counter Command Selection */ -typedef enum XCL_CMDSEL_enum -{ - XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ - XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -} XCL_CMDSEL_t; - -/* Timer/Counter Selection */ -typedef enum XCL_TCSEL_enum -{ - XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ - XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ - XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ - XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ - XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ - XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -} XCL_TCSEL_t; - -/* Timer/Counter Mode */ -typedef enum XCL_TCMODE_enum -{ - XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ - XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ - XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -} XCL_TCMODE_t; - -/* Compare Output Value Timer */ -typedef enum XCL_CMPEN_enum -{ - XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ - XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -} XCL_CMPEN_t; - -/* Command Enable */ -typedef enum XCL_CMDEN_enum -{ - XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ - XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ - XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ - XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -} XCL_CMDEN_t; - -/* Timer/Counter Event Source Selection */ -typedef enum XCL_EVSRC_enum -{ - XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ - XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ - XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ - XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ - XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ - XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ - XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ - XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -} XCL_EVSRC_t; - -/* Timer/Counter Event Action Selection */ -typedef enum XCL_EVACT_enum -{ - XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ - XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ - XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ - XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -} XCL_EVACT_t; - -/* Underflow Interrupt level */ -typedef enum XCL_UNF_INTLVL_enum -{ - XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ - XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ - XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -} XCL_UNF_INTLVL_t; - -/* Compare/Capture Interrupt level */ -typedef enum XCL_CC_INTLVL_enum -{ - XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} XCL_CC_INTLVL_t; - - -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - -/* */ -typedef struct TWI_MASTER_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t STATUS; /* Status Register */ - register8_t BAUD; /* Baurd Rate Control Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ -} TWI_MASTER_t; - - -/* */ -typedef struct TWI_SLAVE_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t STATUS; /* Status Register */ - register8_t ADDR; /* Address Register */ - register8_t DATA; /* Data Register */ - register8_t ADDRMASK; /* Address Mask Register */ -} TWI_SLAVE_t; - - -/* */ -typedef struct TWI_TIMEOUT_struct -{ - register8_t TOS; /* Timeout Status Register */ - register8_t TOCONF; /* Timeout Configuration Register */ -} TWI_TIMEOUT_t; - - -/* Two-Wire Interface */ -typedef struct TWI_struct -{ - register8_t CTRL; /* TWI Common Control Register */ - TWI_MASTER_t MASTER; /* TWI master module */ - TWI_SLAVE_t SLAVE; /* TWI slave module */ - TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -} TWI_t; - -/* SDA Hold Time */ -typedef enum TWI_SDAHOLD_enum -{ - TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ - TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ - TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ - TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -} TWI_SDAHOLD_t; - -/* Master Interrupt Level */ -typedef enum TWI_MASTER_INTLVL_enum -{ - TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_MASTER_INTLVL_t; - -/* Inactive Timeout */ -typedef enum TWI_MASTER_TIMEOUT_enum -{ - TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ - TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ - TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ - TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -} TWI_MASTER_TIMEOUT_t; - -/* Master Command */ -typedef enum TWI_MASTER_CMD_enum -{ - TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ - TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ - TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -} TWI_MASTER_CMD_t; - -/* Master Bus State */ -typedef enum TWI_MASTER_BUSSTATE_enum -{ - TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ - TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ - TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ - TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -} TWI_MASTER_BUSSTATE_t; - -/* Slave Interrupt Level */ -typedef enum TWI_SLAVE_INTLVL_enum -{ - TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ - TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -} TWI_SLAVE_INTLVL_t; - -/* Slave Command */ -typedef enum TWI_SLAVE_CMD_enum -{ - TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ - TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -} TWI_SLAVE_CMD_t; - -/* Master Timeout */ -typedef enum TWI_MASTER_TTIMEOUT_enum -{ - TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ - TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ - TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ - TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ - TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ - TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ - TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ - TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -} TWI_MASTER_TTIMEOUT_t; - -/* Slave Ttimeout */ -typedef enum TWI_SLAVE_TTIMEOUT_enum -{ - TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ - TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ - TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ - TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ - TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ - TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ - TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ - TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -} TWI_SLAVE_TTIMEOUT_t; - -/* Master/Slave Extend Timeout */ -typedef enum TWI_MASTER_TMSEXT_enum -{ - TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ - TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ - TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ - TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -} TWI_MASTER_TMSEXT_t; - - -/* --------------------------------------------------------------------------- -PORT - Port Configuration --------------------------------------------------------------------------- -*/ - -/* I/O Ports */ -typedef struct PORT_struct -{ - register8_t DIR; /* I/O Port Data Direction */ - register8_t DIRSET; /* I/O Port Data Direction Set */ - register8_t DIRCLR; /* I/O Port Data Direction Clear */ - register8_t DIRTGL; /* I/O Port Data Direction Toggle */ - register8_t OUT; /* I/O Port Output */ - register8_t OUTSET; /* I/O Port Output Set */ - register8_t OUTCLR; /* I/O Port Output Clear */ - register8_t OUTTGL; /* I/O Port Output Toggle */ - register8_t IN; /* I/O port Input */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t INTMASK; /* Port Interrupt Mask */ - register8_t reserved_0x0B; - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t REMAP; /* Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ - register8_t PIN2CTRL; /* Pin 2 Control Register */ - register8_t PIN3CTRL; /* Pin 3 Control Register */ - register8_t PIN4CTRL; /* Pin 4 Control Register */ - register8_t PIN5CTRL; /* Pin 5 Control Register */ - register8_t PIN6CTRL; /* Pin 6 Control Register */ - register8_t PIN7CTRL; /* Pin 7 Control Register */ -} PORT_t; - -/* Port Interrupt Level */ -typedef enum PORT_INTLVL_enum -{ - PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} PORT_INTLVL_t; - -/* Output/Pull Configuration */ -typedef enum PORT_OPC_enum -{ - PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ - PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ - PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ - PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ - PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ - PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ - PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ - PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -} PORT_OPC_t; - -/* Input/Sense Configuration */ -typedef enum PORT_ISC_enum -{ - PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ - PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ - PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ - PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ - PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ - PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -} PORT_ISC_t; - - -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - -/* 16-bit Timer/Counter 4 */ -typedef struct TC4_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - _WORDREGISTER(CCC); /* Compare or Capture C */ - _WORDREGISTER(CCD); /* Compare or Capture D */ - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -} TC4_t; - - -/* 16-bit Timer/Counter 5 */ -typedef struct TC5_struct -{ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control register C */ - register8_t CTRLD; /* Control Register D */ - register8_t CTRLE; /* Control Register E */ - register8_t CTRLF; /* Control Register F */ - register8_t INTCTRLA; /* Interrupt Control Register A */ - register8_t INTCTRLB; /* Interrupt Control Register B */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G Set */ - register8_t CTRLHCLR; /* Control Register H Clear */ - register8_t CTRLHSET; /* Control Register H Set */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t TEMP; /* Temporary Register For 16-bit Access */ - register8_t reserved_0x10; - register8_t reserved_0x11; - register8_t reserved_0x12; - register8_t reserved_0x13; - register8_t reserved_0x14; - register8_t reserved_0x15; - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t reserved_0x1E; - register8_t reserved_0x1F; - _WORDREGISTER(CNT); /* Count */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - _WORDREGISTER(PER); /* Period */ - _WORDREGISTER(CCA); /* Compare or Capture A */ - _WORDREGISTER(CCB); /* Compare or Capture B */ - register8_t reserved_0x2C; - register8_t reserved_0x2D; - register8_t reserved_0x2E; - register8_t reserved_0x2F; - register8_t reserved_0x30; - register8_t reserved_0x31; - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t reserved_0x34; - register8_t reserved_0x35; - _WORDREGISTER(PERBUF); /* Period Buffer */ - _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ - _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} TC5_t; - -/* Clock Selection */ -typedef enum TC45_CLKSEL_enum -{ - TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ - TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ - TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ - TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ - TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ - TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ - TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ - TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ - TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_CLKSEL_t; - -/* Byte Mode */ -typedef enum TC45_BYTEM_enum -{ - TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ - TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -} TC45_BYTEM_t; - -/* Circular Enable Mode */ -typedef enum TC45_CIRCEN_enum -{ - TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ - TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ - TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ - TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -} TC45_CIRCEN_t; - -/* Waveform Generation Mode */ -typedef enum TC45_WGMODE_enum -{ - TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ - TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ - TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -} TC45_WGMODE_t; - -/* Event Action */ -typedef enum TC45_EVACT_enum -{ - TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ - TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ - TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ - TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ - TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ - TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ - TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -} TC45_EVACT_t; - -/* Event Selection */ -typedef enum TC45_EVSEL_enum -{ - TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ - TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ - TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ - TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ - TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ - TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ - TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ - TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -} TC45_EVSEL_t; - -/* Compare or Capture Channel A Mode */ -typedef enum TC45_CCAMODE_enum -{ - TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_CCAMODE_t; - -/* Compare or Capture Channel B Mode */ -typedef enum TC45_CCBMODE_enum -{ - TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_CCBMODE_t; - -/* Compare or Capture Channel C Mode */ -typedef enum TC45_CCCMODE_enum -{ - TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_CCCMODE_t; - -/* Compare or Capture Channel D Mode */ -typedef enum TC45_CCDMODE_enum -{ - TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_CCDMODE_t; - -/* Compare or Capture Low Channel A Mode */ -typedef enum TC45_LCCAMODE_enum -{ - TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_LCCAMODE_t; - -/* Compare or Capture Low Channel B Mode */ -typedef enum TC45_LCCBMODE_enum -{ - TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_LCCBMODE_t; - -/* Compare or Capture Low Channel C Mode */ -typedef enum TC45_LCCCMODE_enum -{ - TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_LCCCMODE_t; - -/* Compare or Capture Low Channel D Mode */ -typedef enum TC45_LCCDMODE_enum -{ - TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_LCCDMODE_t; - -/* Compare or Capture High Channel A Mode */ -typedef enum TC45_HCCAMODE_enum -{ - TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ - TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ - TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ - TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -} TC45_HCCAMODE_t; - -/* Compare or Capture High Channel B Mode */ -typedef enum TC45_HCCBMODE_enum -{ - TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ - TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ - TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ - TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -} TC45_HCCBMODE_t; - -/* Compare or Capture High Channel C Mode */ -typedef enum TC45_HCCCMODE_enum -{ - TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ - TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ - TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ - TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -} TC45_HCCCMODE_t; - -/* Compare or Capture High Channel D Mode */ -typedef enum TC45_HCCDMODE_enum -{ - TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ - TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ - TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ - TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -} TC45_HCCDMODE_t; - -/* Timer Trigger Restart Interrupt Level */ -typedef enum TC45_TRGINTLVL_enum -{ - TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_TRGINTLVL_t; - -/* Error Interrupt Level */ -typedef enum TC45_ERRINTLVL_enum -{ - TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_ERRINTLVL_t; - -/* Overflow Interrupt Level */ -typedef enum TC45_OVFINTLVL_enum -{ - TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_OVFINTLVL_t; - -/* Compare or Capture Channel A Interrupt Level */ -typedef enum TC45_CCAINTLVL_enum -{ - TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_CCAINTLVL_t; - -/* Compare or Capture Channel B Interrupt Level */ -typedef enum TC45_CCBINTLVL_enum -{ - TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_CCBINTLVL_t; - -/* Compare or Capture Channel C Interrupt Level */ -typedef enum TC45_CCCINTLVL_enum -{ - TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_CCCINTLVL_t; - -/* Compare or Capture Channel D Interrupt Level */ -typedef enum TC45_CCDINTLVL_enum -{ - TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_CCDINTLVL_t; - -/* Compare or Capture Low Channel A Interrupt Level */ -typedef enum TC45_LCCAINTLVL_enum -{ - TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ - TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -} TC45_LCCAINTLVL_t; - -/* Compare or Capture Low Channel B Interrupt Level */ -typedef enum TC45_LCCBINTLVL_enum -{ - TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ - TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -} TC45_LCCBINTLVL_t; - -/* Compare or Capture Low Channel C Interrupt Level */ -typedef enum TC45_LCCCINTLVL_enum -{ - TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} TC45_LCCCINTLVL_t; - -/* Compare or Capture Low Channel D Interrupt Level */ -typedef enum TC45_LCCDINTLVL_enum -{ - TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ - TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ - TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ - TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -} TC45_LCCDINTLVL_t; - -/* Timer/Counter Command */ -typedef enum TC45_CMD_enum -{ - TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ - TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ - TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ - TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -} TC45_CMD_t; - - -/* --------------------------------------------------------------------------- -FAULT - Fault Extension --------------------------------------------------------------------------- -*/ - -/* Fault Extension */ -typedef struct FAULT_struct -{ - register8_t CTRLA; /* Control A Register */ - register8_t CTRLB; /* Control B Register */ - register8_t CTRLC; /* Control C Register */ - register8_t CTRLD; /* Control D Register */ - register8_t CTRLE; /* Control E Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLGCLR; /* Control Register G Clear */ - register8_t CTRLGSET; /* Control Register G set */ -} FAULT_t; - -/* Ramp Mode Selection */ -typedef enum FAULT_RAMP_enum -{ - FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ - FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -} FAULT_RAMP_t; - -/* Fault E Input Source Selection */ -typedef enum FAULT_SRCE_enum -{ - FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ - FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -} FAULT_SRCE_t; - -/* Fault A Halt Action Selection */ -typedef enum FAULT_HALTA_enum -{ - FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTA_t; - -/* Fault A Source Selection */ -typedef enum FAULT_SRCA_enum -{ - FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ - FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -} FAULT_SRCA_t; - -/* Fault B Halt Action Selection */ -typedef enum FAULT_HALTB_enum -{ - FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ - FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ - FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -} FAULT_HALTB_t; - -/* Fault B Source Selection */ -typedef enum FAULT_SRCB_enum -{ - FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ - FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ - FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ - FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -} FAULT_SRCB_t; - -/* Channel index Command */ -typedef enum FAULT_IDXCMD_enum -{ - FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ - FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ - FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ - FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -} FAULT_IDXCMD_t; - - -/* --------------------------------------------------------------------------- -WEX - Waveform Extension --------------------------------------------------------------------------- -*/ - -/* Waveform Extension */ -typedef struct WEX_struct -{ - register8_t CTRL; /* Control Register */ - register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ - register8_t DTLS; /* Dead-time Low Side Register */ - register8_t DTHS; /* Dead-time High Side Register */ - register8_t STATUSCLR; /* Status Clear Register */ - register8_t STATUSSET; /* Status Set Register */ - register8_t SWAP; /* Swap Register */ - register8_t PGO; /* Pattern Generation Override Register */ - register8_t PGV; /* Pattern Generation Value Register */ - register8_t reserved_0x09; - register8_t SWAPBUF; /* Dead Time Low Side Buffer */ - register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ - register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ - register8_t reserved_0x0D; - register8_t reserved_0x0E; - register8_t OUTOVDIS; /* Output Override Disable Register */ -} WEX_t; - -/* Output Matrix Mode */ -typedef enum WEX_OTMX_enum -{ - WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ - WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ - WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ - WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ - WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -} WEX_OTMX_t; - - -/* --------------------------------------------------------------------------- -HIRES - High-Resolution Extension --------------------------------------------------------------------------- -*/ - -/* High-Resolution Extension */ -typedef struct HIRES_struct -{ - register8_t CTRLA; /* Control Register A */ -} HIRES_t; - -/* High Resolution Plus Mode */ -typedef enum HIRES_HRPLUS_enum -{ - HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ - HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ - HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ - HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -} HIRES_HRPLUS_t; - -/* High Resolution Mode */ -typedef enum HIRES_HREN_enum -{ - HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ - HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ - HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ - HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -} HIRES_HREN_t; - - -/* --------------------------------------------------------------------------- -USART - Universal Asynchronous Receiver-Transmitter --------------------------------------------------------------------------- -*/ - -/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -typedef struct USART_struct -{ - register8_t DATA; /* Data Register */ - register8_t STATUS; /* Status Register */ - register8_t CTRLA; /* Control Register A */ - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t CTRLD; /* Control Register D */ - register8_t BAUDCTRLA; /* Baud Rate Control Register A */ - register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -} USART_t; - -/* Receive Start Interrupt level */ -typedef enum USART_RXSINTLVL_enum -{ - USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_RXSINTLVL_t; - -/* Receive Complete Interrupt level */ -typedef enum USART_RXCINTLVL_enum -{ - USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ - USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ - USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ - USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -} USART_RXCINTLVL_t; - -/* Transmit Complete Interrupt level */ -typedef enum USART_TXCINTLVL_enum -{ - USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ - USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ - USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ - USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -} USART_TXCINTLVL_t; - -/* Data Register Empty Interrupt level */ -typedef enum USART_DREINTLVL_enum -{ - USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ - USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -} USART_DREINTLVL_t; - -/* Character Size */ -typedef enum USART_CHSIZE_enum -{ - USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ - USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ - USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ - USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ - USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -} USART_CHSIZE_t; - -/* Communication Mode */ -typedef enum USART_CMODE_enum -{ - USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ - USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ - USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ - USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -} USART_CMODE_t; - -/* Parity Mode */ -typedef enum USART_PMODE_enum -{ - USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ - USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ - USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -} USART_PMODE_t; - -/* Encoding and Decoding Type */ -typedef enum USART_DECTYPE_enum -{ - USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ - USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ - USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -} USART_DECTYPE_t; - -/* XCL LUT Action */ -typedef enum USART_LUTACT_enum -{ - USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ - USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ - USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ - USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -} USART_LUTACT_t; - -/* XCL Peripheral Counter Action */ -typedef enum USART_PECACT_enum -{ - USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ - USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ - USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ - USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -} USART_PECACT_t; - - -/* --------------------------------------------------------------------------- -SPI - Serial Peripheral Interface --------------------------------------------------------------------------- -*/ - -/* Serial Peripheral Interface with Buffer Modes */ -typedef struct SPI_struct -{ - register8_t CTRL; /* Control Register */ - register8_t INTCTRL; /* Interrupt Control Register */ - register8_t STATUS; /* Status Register */ - register8_t DATA; /* Data Register */ - register8_t CTRLB; /* Control Register B */ -} SPI_t; - -/* SPI Mode */ -typedef enum SPI_MODE_enum -{ - SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ - SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ - SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ - SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -} SPI_MODE_t; - -/* Prescaler setting */ -typedef enum SPI_PRESCALER_enum -{ - SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ - SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ - SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ - SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -} SPI_PRESCALER_t; - -/* Interrupt level */ -typedef enum SPI_INTLVL_enum -{ - SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ - SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ - SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} SPI_INTLVL_t; - -/* Buffer Modes */ -typedef enum SPI_BUFMODE_enum -{ - SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ - SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ - SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -} SPI_BUFMODE_t; - - -/* --------------------------------------------------------------------------- -IRCOM - IR Communication Module --------------------------------------------------------------------------- -*/ - -/* IR Communication Module */ -typedef struct IRCOM_struct -{ - register8_t CTRL; /* Control Register */ - register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ - register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -} IRCOM_t; - -/* Event channel selection */ -typedef enum IRDA_EVSEL_enum -{ - IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ - IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ - IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ - IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ - IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ - IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ - IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ - IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ - IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -} IRDA_EVSEL_t; - - -/* --------------------------------------------------------------------------- -FUSE - Fuses and Lockbits --------------------------------------------------------------------------- -*/ - -/* Lock Bits */ -typedef struct NVM_LOCKBITS_struct -{ - register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ -} NVM_LOCKBITS_t; - - -/* Fuses */ -typedef struct NVM_FUSES_struct -{ - register8_t reserved_0x00; - register8_t FUSEBYTE1; /* Watchdog Configuration */ - register8_t FUSEBYTE2; /* Reset Configuration */ - register8_t reserved_0x03; - register8_t FUSEBYTE4; /* Start-up Configuration */ - register8_t FUSEBYTE5; /* EESAVE and BOD Level */ - register8_t FUSEBYTE6; /* Fault State */ -} NVM_FUSES_t; - -/* Boot lock bits - boot setcion */ -typedef enum FUSE_BLBB_enum -{ - FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ - FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -} FUSE_BLBB_t; - -/* Boot lock bits - application section */ -typedef enum FUSE_BLBA_enum -{ - FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ - FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -} FUSE_BLBA_t; - -/* Boot lock bits - application table section */ -typedef enum FUSE_BLBAT_enum -{ - FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ - FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -} FUSE_BLBAT_t; - -/* Lock bits */ -typedef enum FUSE_LB_enum -{ - FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ - FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -} FUSE_LB_t; - -/* Boot Loader Section Reset Vector */ -typedef enum BOOTRST_enum -{ - BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ - BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -} BOOTRST_t; - -/* BOD operation */ -typedef enum BOD_enum -{ - BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ - BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ - BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -} BOD_t; - -/* Watchdog (Window) Timeout Period */ -typedef enum WD_enum -{ - WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ - WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ - WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ - WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ - WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ - WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ - WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ - WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ - WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ - WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ - WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -} WD_t; - -/* Start-up Time */ -typedef enum SUT_enum -{ - SUT_0MS_gc = (0x03<<2), /* 0 ms */ - SUT_4MS_gc = (0x01<<2), /* 4 ms */ - SUT_64MS_gc = (0x00<<2), /* 64 ms */ -} SUT_t; - -/* Brownout Detection Voltage Level */ -typedef enum BODLVL_enum -{ - BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ - BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ - BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ - BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ - BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ - BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ - BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ - BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -} BODLVL_t; - - -/* --------------------------------------------------------------------------- -SIGROW - Signature Row --------------------------------------------------------------------------- -*/ - -/* Production Signatures */ -typedef struct NVM_PROD_SIGNATURES_struct -{ - register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ - register8_t reserved_0x01; - register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ - register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ - register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ - register8_t reserved_0x05; - register8_t reserved_0x06; - register8_t reserved_0x07; - register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ - register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ - register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ - register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ - register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ - register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ - register8_t reserved_0x0E; - register8_t reserved_0x0F; - register8_t WAFNUM; /* Wafer Number */ - register8_t reserved_0x11; - register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ - register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ - register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ - register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ - register8_t reserved_0x16; - register8_t reserved_0x17; - register8_t reserved_0x18; - register8_t reserved_0x19; - register8_t reserved_0x1A; - register8_t reserved_0x1B; - register8_t reserved_0x1C; - register8_t reserved_0x1D; - register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ - register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ - register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ - register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ - register8_t reserved_0x22; - register8_t reserved_0x23; - register8_t reserved_0x24; - register8_t reserved_0x25; - register8_t reserved_0x26; - register8_t reserved_0x27; - register8_t ACACURRCAL; /* ACA Current Calibration Byte */ - register8_t reserved_0x29; - register8_t reserved_0x2A; - register8_t reserved_0x2B; - register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ - register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ - register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ - register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ - register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ - register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ - register8_t reserved_0x32; - register8_t reserved_0x33; - register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ - register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ - register8_t reserved_0x36; - register8_t reserved_0x37; - register8_t reserved_0x38; - register8_t reserved_0x39; - register8_t reserved_0x3A; - register8_t reserved_0x3B; - register8_t reserved_0x3C; - register8_t reserved_0x3D; - register8_t reserved_0x3E; - register8_t reserved_0x3F; -} NVM_PROD_SIGNATURES_t; - -/* -========================================================================== -IO Module Instances. Mapped to memory. -========================================================================== -*/ - -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset */ -#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ - - -#endif /* !defined (__ASSEMBLER__) */ - - -/* ========== Flattened fully qualified IO register names ========== */ - -/* GPIO - General Purpose IO Registers */ -#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -#define GPIO_GPIOR3 _SFR_MEM8(0x0003) - -/* Deprecated */ -#define GPIO_GPIO0 _SFR_MEM8(0x0000) -#define GPIO_GPIO1 _SFR_MEM8(0x0001) -#define GPIO_GPIO2 _SFR_MEM8(0x0002) -#define GPIO_GPIO3 _SFR_MEM8(0x0003) - -/* NVM_FUSES - Fuses */ -#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) - -/* NVM_LOCKBITS - Lock Bits */ -#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) - -/* NVM_PROD_SIGNATURES - Production Signatures */ -#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) - -/* VPORT - Virtual Port */ -#define VPORT0_DIR _SFR_MEM8(0x0010) -#define VPORT0_OUT _SFR_MEM8(0x0011) -#define VPORT0_IN _SFR_MEM8(0x0012) -#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - -/* VPORT - Virtual Port */ -#define VPORT1_DIR _SFR_MEM8(0x0014) -#define VPORT1_OUT _SFR_MEM8(0x0015) -#define VPORT1_IN _SFR_MEM8(0x0016) -#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - -/* VPORT - Virtual Port */ -#define VPORT2_DIR _SFR_MEM8(0x0018) -#define VPORT2_OUT _SFR_MEM8(0x0019) -#define VPORT2_IN _SFR_MEM8(0x001A) -#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - -/* VPORT - Virtual Port */ -#define VPORT3_DIR _SFR_MEM8(0x001C) -#define VPORT3_OUT _SFR_MEM8(0x001D) -#define VPORT3_IN _SFR_MEM8(0x001E) -#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) - -/* OCD - On-Chip Debug System */ -#define OCD_OCDR0 _SFR_MEM8(0x002E) -#define OCD_OCDR1 _SFR_MEM8(0x002F) - -/* CPU - CPU registers */ -#define CPU_CCP _SFR_MEM8(0x0034) -#define CPU_RAMPD _SFR_MEM8(0x0038) -#define CPU_RAMPX _SFR_MEM8(0x0039) -#define CPU_RAMPY _SFR_MEM8(0x003A) -#define CPU_RAMPZ _SFR_MEM8(0x003B) -#define CPU_EIND _SFR_MEM8(0x003C) -#define CPU_SPL _SFR_MEM8(0x003D) -#define CPU_SPH _SFR_MEM8(0x003E) -#define CPU_SREG _SFR_MEM8(0x003F) - -/* CLK - Clock System */ -#define CLK_CTRL _SFR_MEM8(0x0040) -#define CLK_PSCTRL _SFR_MEM8(0x0041) -#define CLK_LOCK _SFR_MEM8(0x0042) -#define CLK_RTCCTRL _SFR_MEM8(0x0043) - -/* SLEEP - Sleep Controller */ -#define SLEEP_CTRL _SFR_MEM8(0x0048) - -/* OSC - Oscillator */ -#define OSC_CTRL _SFR_MEM8(0x0050) -#define OSC_STATUS _SFR_MEM8(0x0051) -#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -#define OSC_RC32KCAL _SFR_MEM8(0x0054) -#define OSC_PLLCTRL _SFR_MEM8(0x0055) -#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -#define OSC_RC8MCAL _SFR_MEM8(0x0057) - -/* DFLL - DFLL */ -#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - -/* PR - Power Reduction */ -#define PR_PRGEN _SFR_MEM8(0x0070) -#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPC _SFR_MEM8(0x0073) -#define PR_PRPD _SFR_MEM8(0x0074) - -/* RST - Reset */ -#define RST_STATUS _SFR_MEM8(0x0078) -#define RST_CTRL _SFR_MEM8(0x0079) - -/* WDT - Watch-Dog Timer */ -#define WDT_CTRL _SFR_MEM8(0x0080) -#define WDT_WINCTRL _SFR_MEM8(0x0081) -#define WDT_STATUS _SFR_MEM8(0x0082) - -/* MCU - MCU Control */ -#define MCU_DEVID0 _SFR_MEM8(0x0090) -#define MCU_DEVID1 _SFR_MEM8(0x0091) -#define MCU_DEVID2 _SFR_MEM8(0x0092) -#define MCU_REVID _SFR_MEM8(0x0093) -#define MCU_ANAINIT _SFR_MEM8(0x0097) -#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -#define MCU_WEXLOCK _SFR_MEM8(0x0099) -#define MCU_FAULTLOCK _SFR_MEM8(0x009A) - -/* PMIC - Programmable Multi-level Interrupt Controller */ -#define PMIC_STATUS _SFR_MEM8(0x00A0) -#define PMIC_INTPRI _SFR_MEM8(0x00A1) -#define PMIC_CTRL _SFR_MEM8(0x00A2) - -/* PORTCFG - I/O port Configuration */ -#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) - -/* CRC - Cyclic Redundancy Checker */ -#define CRC_CTRL _SFR_MEM8(0x00D0) -#define CRC_STATUS _SFR_MEM8(0x00D1) -#define CRC_DATAIN _SFR_MEM8(0x00D3) -#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) - -/* EDMA - Enhanced DMA Controller */ -#define EDMA_CTRL _SFR_MEM8(0x0100) -#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -#define EDMA_STATUS _SFR_MEM8(0x0104) -#define EDMA_TEMP _SFR_MEM8(0x0106) -#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) - -/* EVSYS - Event System */ -#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -#define EVSYS_STROBE _SFR_MEM8(0x0190) -#define EVSYS_DATA _SFR_MEM8(0x0191) -#define EVSYS_DFCTRL _SFR_MEM8(0x0192) - -/* NVM - Non-volatile Memory Controller */ -#define NVM_ADDR0 _SFR_MEM8(0x01C0) -#define NVM_ADDR1 _SFR_MEM8(0x01C1) -#define NVM_ADDR2 _SFR_MEM8(0x01C2) -#define NVM_DATA0 _SFR_MEM8(0x01C4) -#define NVM_DATA1 _SFR_MEM8(0x01C5) -#define NVM_DATA2 _SFR_MEM8(0x01C6) -#define NVM_CMD _SFR_MEM8(0x01CA) -#define NVM_CTRLA _SFR_MEM8(0x01CB) -#define NVM_CTRLB _SFR_MEM8(0x01CC) -#define NVM_INTCTRL _SFR_MEM8(0x01CD) -#define NVM_STATUS _SFR_MEM8(0x01CF) -#define NVM_LOCKBITS _SFR_MEM8(0x01D0) - -/* ADC - Analog-to-Digital Converter */ -#define ADCA_CTRLA _SFR_MEM8(0x0200) -#define ADCA_CTRLB _SFR_MEM8(0x0201) -#define ADCA_REFCTRL _SFR_MEM8(0x0202) -#define ADCA_EVCTRL _SFR_MEM8(0x0203) -#define ADCA_PRESCALER _SFR_MEM8(0x0204) -#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -#define ADCA_TEMP _SFR_MEM8(0x0207) -#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -#define ADCA_CAL _SFR_MEM16(0x020C) -#define ADCA_CH0RES _SFR_MEM16(0x0210) -#define ADCA_CMP _SFR_MEM16(0x0218) -#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -#define ADCA_CH0_RES _SFR_MEM16(0x0224) -#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) - -/* DAC - Digital-to-Analog Converter */ -#define DACA_CTRLA _SFR_MEM8(0x0300) -#define DACA_CTRLB _SFR_MEM8(0x0301) -#define DACA_CTRLC _SFR_MEM8(0x0302) -#define DACA_EVCTRL _SFR_MEM8(0x0303) -#define DACA_STATUS _SFR_MEM8(0x0305) -#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -#define DACA_CH0DATA _SFR_MEM16(0x0318) -#define DACA_CH1DATA _SFR_MEM16(0x031A) - -/* AC - Analog Comparator */ -#define ACA_AC0CTRL _SFR_MEM8(0x0380) -#define ACA_AC1CTRL _SFR_MEM8(0x0381) -#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -#define ACA_CTRLA _SFR_MEM8(0x0384) -#define ACA_CTRLB _SFR_MEM8(0x0385) -#define ACA_WINCTRL _SFR_MEM8(0x0386) -#define ACA_STATUS _SFR_MEM8(0x0387) -#define ACA_CURRCTRL _SFR_MEM8(0x0388) -#define ACA_CURRCALIB _SFR_MEM8(0x0389) - -/* RTC - Real-Time Counter */ -#define RTC_CTRL _SFR_MEM8(0x0400) -#define RTC_STATUS _SFR_MEM8(0x0401) -#define RTC_INTCTRL _SFR_MEM8(0x0402) -#define RTC_INTFLAGS _SFR_MEM8(0x0403) -#define RTC_TEMP _SFR_MEM8(0x0404) -#define RTC_CALIB _SFR_MEM8(0x0406) -#define RTC_CNT _SFR_MEM16(0x0408) -#define RTC_PER _SFR_MEM16(0x040A) -#define RTC_COMP _SFR_MEM16(0x040C) - -/* XCL - XMEGA Custom Logic */ -#define XCL_CTRLA _SFR_MEM8(0x0460) -#define XCL_CTRLB _SFR_MEM8(0x0461) -#define XCL_CTRLC _SFR_MEM8(0x0462) -#define XCL_CTRLD _SFR_MEM8(0x0463) -#define XCL_CTRLE _SFR_MEM8(0x0464) -#define XCL_CTRLF _SFR_MEM8(0x0465) -#define XCL_CTRLG _SFR_MEM8(0x0466) -#define XCL_INTCTRL _SFR_MEM8(0x0467) -#define XCL_INTFLAGS _SFR_MEM8(0x0468) -#define XCL_PLC _SFR_MEM8(0x0469) -#define XCL_CNTL _SFR_MEM8(0x046A) -#define XCL_CNTH _SFR_MEM8(0x046B) -#define XCL_CMPL _SFR_MEM8(0x046C) -#define XCL_CMPH _SFR_MEM8(0x046D) -#define XCL_PERCAPTL _SFR_MEM8(0x046E) -#define XCL_PERCAPTH _SFR_MEM8(0x046F) - -/* TWI - Two-Wire Interface */ -#define TWIC_CTRL _SFR_MEM8(0x0480) -#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) - -/* PORT - I/O Ports */ -#define PORTA_DIR _SFR_MEM8(0x0600) -#define PORTA_DIRSET _SFR_MEM8(0x0601) -#define PORTA_DIRCLR _SFR_MEM8(0x0602) -#define PORTA_DIRTGL _SFR_MEM8(0x0603) -#define PORTA_OUT _SFR_MEM8(0x0604) -#define PORTA_OUTSET _SFR_MEM8(0x0605) -#define PORTA_OUTCLR _SFR_MEM8(0x0606) -#define PORTA_OUTTGL _SFR_MEM8(0x0607) -#define PORTA_IN _SFR_MEM8(0x0608) -#define PORTA_INTCTRL _SFR_MEM8(0x0609) -#define PORTA_INTMASK _SFR_MEM8(0x060A) -#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -#define PORTA_REMAP _SFR_MEM8(0x060E) -#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - -/* PORT - I/O Ports */ -#define PORTC_DIR _SFR_MEM8(0x0640) -#define PORTC_DIRSET _SFR_MEM8(0x0641) -#define PORTC_DIRCLR _SFR_MEM8(0x0642) -#define PORTC_DIRTGL _SFR_MEM8(0x0643) -#define PORTC_OUT _SFR_MEM8(0x0644) -#define PORTC_OUTSET _SFR_MEM8(0x0645) -#define PORTC_OUTCLR _SFR_MEM8(0x0646) -#define PORTC_OUTTGL _SFR_MEM8(0x0647) -#define PORTC_IN _SFR_MEM8(0x0648) -#define PORTC_INTCTRL _SFR_MEM8(0x0649) -#define PORTC_INTMASK _SFR_MEM8(0x064A) -#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -#define PORTC_REMAP _SFR_MEM8(0x064E) -#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - -/* PORT - I/O Ports */ -#define PORTD_DIR _SFR_MEM8(0x0660) -#define PORTD_DIRSET _SFR_MEM8(0x0661) -#define PORTD_DIRCLR _SFR_MEM8(0x0662) -#define PORTD_DIRTGL _SFR_MEM8(0x0663) -#define PORTD_OUT _SFR_MEM8(0x0664) -#define PORTD_OUTSET _SFR_MEM8(0x0665) -#define PORTD_OUTCLR _SFR_MEM8(0x0666) -#define PORTD_OUTTGL _SFR_MEM8(0x0667) -#define PORTD_IN _SFR_MEM8(0x0668) -#define PORTD_INTCTRL _SFR_MEM8(0x0669) -#define PORTD_INTMASK _SFR_MEM8(0x066A) -#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -#define PORTD_REMAP _SFR_MEM8(0x066E) -#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - -/* PORT - I/O Ports */ -#define PORTR_DIR _SFR_MEM8(0x07E0) -#define PORTR_DIRSET _SFR_MEM8(0x07E1) -#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -#define PORTR_OUT _SFR_MEM8(0x07E4) -#define PORTR_OUTSET _SFR_MEM8(0x07E5) -#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -#define PORTR_IN _SFR_MEM8(0x07E8) -#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -#define PORTR_INTMASK _SFR_MEM8(0x07EA) -#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -#define PORTR_REMAP _SFR_MEM8(0x07EE) -#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - -/* TC4 - 16-bit Timer/Counter 4 */ -#define TCC4_CTRLA _SFR_MEM8(0x0800) -#define TCC4_CTRLB _SFR_MEM8(0x0801) -#define TCC4_CTRLC _SFR_MEM8(0x0802) -#define TCC4_CTRLD _SFR_MEM8(0x0803) -#define TCC4_CTRLE _SFR_MEM8(0x0804) -#define TCC4_CTRLF _SFR_MEM8(0x0805) -#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -#define TCC4_TEMP _SFR_MEM8(0x080F) -#define TCC4_CNT _SFR_MEM16(0x0820) -#define TCC4_PER _SFR_MEM16(0x0826) -#define TCC4_CCA _SFR_MEM16(0x0828) -#define TCC4_CCB _SFR_MEM16(0x082A) -#define TCC4_CCC _SFR_MEM16(0x082C) -#define TCC4_CCD _SFR_MEM16(0x082E) -#define TCC4_PERBUF _SFR_MEM16(0x0836) -#define TCC4_CCABUF _SFR_MEM16(0x0838) -#define TCC4_CCBBUF _SFR_MEM16(0x083A) -#define TCC4_CCCBUF _SFR_MEM16(0x083C) -#define TCC4_CCDBUF _SFR_MEM16(0x083E) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCC5_CTRLA _SFR_MEM8(0x0840) -#define TCC5_CTRLB _SFR_MEM8(0x0841) -#define TCC5_CTRLC _SFR_MEM8(0x0842) -#define TCC5_CTRLD _SFR_MEM8(0x0843) -#define TCC5_CTRLE _SFR_MEM8(0x0844) -#define TCC5_CTRLF _SFR_MEM8(0x0845) -#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -#define TCC5_TEMP _SFR_MEM8(0x084F) -#define TCC5_CNT _SFR_MEM16(0x0860) -#define TCC5_PER _SFR_MEM16(0x0866) -#define TCC5_CCA _SFR_MEM16(0x0868) -#define TCC5_CCB _SFR_MEM16(0x086A) -#define TCC5_PERBUF _SFR_MEM16(0x0876) -#define TCC5_CCABUF _SFR_MEM16(0x0878) -#define TCC5_CCBBUF _SFR_MEM16(0x087A) - -/* FAULT - Fault Extension */ -#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -#define FAULTC4_STATUS _SFR_MEM8(0x0885) -#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) - -/* FAULT - Fault Extension */ -#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -#define FAULTC5_STATUS _SFR_MEM8(0x0895) -#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) - -/* WEX - Waveform Extension */ -#define WEXC_CTRL _SFR_MEM8(0x08A0) -#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -#define WEXC_DTLS _SFR_MEM8(0x08A2) -#define WEXC_DTHS _SFR_MEM8(0x08A3) -#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -#define WEXC_SWAP _SFR_MEM8(0x08A6) -#define WEXC_PGO _SFR_MEM8(0x08A7) -#define WEXC_PGV _SFR_MEM8(0x08A8) -#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) - -/* HIRES - High-Resolution Extension */ -#define HIRESC_CTRLA _SFR_MEM8(0x08B0) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTC0_DATA _SFR_MEM8(0x08C0) -#define USARTC0_STATUS _SFR_MEM8(0x08C1) -#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) - -/* SPI - Serial Peripheral Interface with Buffer Modes */ -#define SPIC_CTRL _SFR_MEM8(0x08E0) -#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -#define SPIC_STATUS _SFR_MEM8(0x08E2) -#define SPIC_DATA _SFR_MEM8(0x08E3) -#define SPIC_CTRLB _SFR_MEM8(0x08E4) - -/* IRCOM - IR Communication Module */ -#define IRCOM_CTRL _SFR_MEM8(0x08F8) -#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - -/* TC5 - 16-bit Timer/Counter 5 */ -#define TCD5_CTRLA _SFR_MEM8(0x0940) -#define TCD5_CTRLB _SFR_MEM8(0x0941) -#define TCD5_CTRLC _SFR_MEM8(0x0942) -#define TCD5_CTRLD _SFR_MEM8(0x0943) -#define TCD5_CTRLE _SFR_MEM8(0x0944) -#define TCD5_CTRLF _SFR_MEM8(0x0945) -#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -#define TCD5_TEMP _SFR_MEM8(0x094F) -#define TCD5_CNT _SFR_MEM16(0x0960) -#define TCD5_PER _SFR_MEM16(0x0966) -#define TCD5_CCA _SFR_MEM16(0x0968) -#define TCD5_CCB _SFR_MEM16(0x096A) -#define TCD5_PERBUF _SFR_MEM16(0x0976) -#define TCD5_CCABUF _SFR_MEM16(0x0978) -#define TCD5_CCBBUF _SFR_MEM16(0x097A) - -/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -#define USARTD0_DATA _SFR_MEM8(0x09C0) -#define USARTD0_STATUS _SFR_MEM8(0x09C1) -#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) - - - -/*================== Bitfield Definitions ================== */ - -/* VPORT - Virtual Ports */ -/* VPORT.INTFLAGS bit masks and bit positions */ -#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ - -#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ - -#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ - -#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ - -#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ - -#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ - -#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ - -#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ - -/* XOCD - On-Chip Debug System */ -/* OCD.OCDR0 bit masks and bit positions */ -#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -/* OCD.OCDR1 bit masks and bit positions */ -/* OCD_OCDRD Predefined. */ -/* OCD_OCDRD Predefined. */ - -/* CPU - CPU */ -/* CPU.CCP bit masks and bit positions */ -#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -#define CPU_CCP_gp 0 /* CCP signature group position. */ -#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - -/* CPU.SREG bit masks and bit positions */ -#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - -#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -#define CPU_T_bp 6 /* Transfer Bit bit position. */ - -#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -#define CPU_H_bp 5 /* Half Carry Flag bit position. */ - -#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ - -#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ - -#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -#define CPU_N_bp 2 /* Negative Flag bit position. */ - -#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -#define CPU_Z_bp 1 /* Zero Flag bit position. */ - -#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -#define CPU_C_bp 0 /* Carry Flag bit position. */ - -/* CLK - Clock System */ -/* CLK.CTRL bit masks and bit positions */ -#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - -/* CLK.PSCTRL bit masks and bit positions */ -#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ - -#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - -/* CLK.LOCK bit masks and bit positions */ -#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - -/* CLK.RTCCTRL bit masks and bit positions */ -#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ - -#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - -/* PR.PRGEN bit masks and bit positions */ -#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ - -#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -#define PR_RTC_bp 2 /* Real-time Counter bit position. */ - -#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -#define PR_EVSYS_bp 1 /* Event System bit position. */ - -#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ - -/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - -#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -#define PR_ADC_bp 1 /* Port A ADC bit position. */ - -#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -/* PR.PRPC bit masks and bit positions */ -#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - -#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -#define PR_USART0_bp 4 /* Port C USART0 bit position. */ - -#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -#define PR_SPI_bp 3 /* Port C SPI bit position. */ - -#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C WEX bit position. */ - -#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ - -#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ - -/* PR.PRPD bit masks and bit positions */ -/* PR_USART0 Predefined. */ -/* PR_USART0 Predefined. */ - -/* PR_TC5 Predefined. */ -/* PR_TC5 Predefined. */ - -/* SLEEP - Sleep Controller */ -/* SLEEP.CTRL bit masks and bit positions */ -#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ - -#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - -/* OSC - Oscillator */ -/* OSC.CTRL bit masks and bit positions */ -#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ - -#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ - -#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ - -#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ - -#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ - -#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ - -#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - -/* OSC.STATUS bit masks and bit positions */ -#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ - -#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ - -#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ - -#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ - -#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ - -#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - -/* OSC.XOSCCTRL bit masks and bit positions */ -#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ - -#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ - -#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ - -/* OSC.XOSCFAIL bit masks and bit positions */ -#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ - -#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ - -#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ - -#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - -/* OSC.PLLCTRL bit masks and bit positions */ -#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ - -#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - -/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -/* OSC.RC8MCAL bit masks and bit positions */ -#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ - -/* DFLL - DFLL */ -/* DFLL.CTRL bit masks and bit positions */ -#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - -/* DFLL.CALA bit masks and bit positions */ -#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - -/* DFLL.CALB bit masks and bit positions */ -#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - -/* RST - Reset */ -/* RST.STATUS bit masks and bit positions */ -#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - -#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ - -#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ - -#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ - -#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ - -#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ - -#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - -/* RST.CTRL bit masks and bit positions */ -#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -#define RST_SWRST_bp 0 /* Software Reset bit position. */ - -/* WDT - Watch-Dog Timer */ -/* WDT.CTRL bit masks and bit positions */ -#define WDT_PER_gm 0x3C /* Period group mask. */ -#define WDT_PER_gp 2 /* Period group position. */ -#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -#define WDT_PER0_bp 2 /* Period bit 0 position. */ -#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -#define WDT_PER1_bp 3 /* Period bit 1 position. */ -#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -#define WDT_PER2_bp 4 /* Period bit 2 position. */ -#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -#define WDT_PER3_bp 5 /* Period bit 3 position. */ - -#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -#define WDT_ENABLE_bp 1 /* Enable bit position. */ - -#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -#define WDT_CEN_bp 0 /* Change Enable bit position. */ - -/* WDT.WINCTRL bit masks and bit positions */ -#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ - -#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ - -#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - -/* WDT.STATUS bit masks and bit positions */ -#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - -/* MCU - MCU Control */ -/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - -/* MCU.EVSYSLOCK bit masks and bit positions */ -#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - -#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - -/* MCU.WEXLOCK bit masks and bit positions */ -#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ - -/* MCU.FAULTLOCK bit masks and bit positions */ -#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ - -#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ - -/* PMIC - Programmable Multi-level Interrupt Controller */ -/* PMIC.STATUS bit masks and bit positions */ -#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - -#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ - -#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ - -#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -/* PMIC.INTPRI bit masks and bit positions */ -#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - -/* PMIC.CTRL bit masks and bit positions */ -#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ - -#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ - -#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ - -#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ - -#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - -/* PORTCFG - Port Configuration */ -/* PORTCFG.CLKOUT bit masks and bit positions */ -#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ - -#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ - -#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ - -#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ - -/* PORTCFG.ACEVOUT bit masks and bit positions */ -#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ - -#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ - -#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ - -#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ - -/* PORTCFG.SRLCTRL bit masks and bit positions */ -#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ - -#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ - -#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ - -#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ - -/* CRC - Cyclic Redundancy Checker */ -/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -#define CRC_RESET_gp 6 /* Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - -#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - -#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - -/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -#define CRC_BUSY_bp 0 /* Busy bit position. */ - -/* EDMA - Enhanced DMA Controller */ -/* EDMA.CTRL bit masks and bit positions */ -#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -#define EDMA_ENABLE_bp 7 /* Enable bit position. */ - -#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -#define EDMA_RESET_bp 6 /* Software Reset bit position. */ - -#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ - -#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ - -#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ - -/* EDMA.INTFLAGS bit masks and bit positions */ -#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ - -#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - -/* EDMA.STATUS bit masks and bit positions */ -#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ - -#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ - -#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ - -#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ - -#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ - -#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ - -#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ - -#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ - -/* EDMA_CH.CTRLA bit masks and bit positions */ -#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - -#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - -#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - -#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - -#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - -#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ - -/* EDMA_CH.CTRLB bit masks and bit positions */ -#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ - -#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ - -#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ - -#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ - -#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ - -#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ - -/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ - -#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ - -/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ - -#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ - -/* EDMA_CH.TRIGSRC bit masks and bit positions */ -#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - -/* EVSYS - Event System */ -/* EVSYS.CH0MUX bit masks and bit positions */ -#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - -/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX Predefined. */ -/* EVSYS_CHMUX Predefined. */ - -/* EVSYS.CH0CTRL bit masks and bit positions */ -#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ - -#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ - -#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ - -#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ - -#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - -/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH3CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.CH7CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT Predefined. */ -/* EVSYS_DIGFILT Predefined. */ - -/* EVSYS.DFCTRL bit masks and bit positions */ -#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ - -#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ - -#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ - -/* NVM - Non Volatile Memory Controller */ -/* NVM.CMD bit masks and bit positions */ -#define NVM_CMD_gm 0x7F /* Command group mask. */ -#define NVM_CMD_gp 0 /* Command group position. */ -#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - -/* NVM.CTRLA bit masks and bit positions */ -#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - -/* NVM.CTRLB bit masks and bit positions */ -#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ - -#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - -/* NVM.INTCTRL bit masks and bit positions */ -#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ - -#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - -/* NVM.STATUS bit masks and bit positions */ -#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ - -#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ - -#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ - -#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - -/* NVM.LOCKBITS bit masks and bit positions */ -#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* ADC - Analog/Digital Converter */ -/* ADC_CH.CTRL bit masks and bit positions */ -#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ - -#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ - -#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - -/* ADC_CH.MUXCTRL bit masks and bit positions */ -#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ - -#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ - -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ - -#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ - -#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ - -/* ADC_CH.INTCTRL bit masks and bit positions */ -#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ - -#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - -/* ADC_CH.INTFLAGS bit masks and bit positions */ -#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ - -/* ADC_CH.SCAN bit masks and bit positions */ -#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ - -#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ - -/* ADC_CH.CORRCTRL bit masks and bit positions */ -#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ - -/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ - -/* ADC_CH.GAINCORR1 bit masks and bit positions */ -#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ - -/* ADC_CH.AVGCTRL bit masks and bit positions */ -#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ - -#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ - -/* ADC.CTRLA bit masks and bit positions */ -#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -#define ADC_START_bp 2 /* Start Conversion bit position. */ - -#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ - -#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - -/* ADC.CTRLB bit masks and bit positions */ -#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - -#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - -#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - -/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - -#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - -#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - -/* ADC.EVCTRL bit masks and bit positions */ -#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ - -#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - -/* ADC.PRESCALER bit masks and bit positions */ -#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - -/* ADC.INTFLAGS bit masks and bit positions */ -#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - -/* ADC.SAMPCTRL bit masks and bit positions */ -#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ - -/* DAC - Digital/Analog Converter */ -/* DAC.CTRLA bit masks and bit positions */ -#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ - -#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ - -#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ - -#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ - -#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define DAC_ENABLE_bp 0 /* Enable bit position. */ - -/* DAC.CTRLB bit masks and bit positions */ -#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ - -#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ - -#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - -/* DAC.CTRLC bit masks and bit positions */ -#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ - -#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - -/* DAC.EVCTRL bit masks and bit positions */ -#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ - -#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - -/* DAC.STATUS bit masks and bit positions */ -#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - -#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - -/* DAC.CH0GAINCAL bit masks and bit positions */ -#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH0OFFSETCAL bit masks and bit positions */ -#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* DAC.CH1GAINCAL bit masks and bit positions */ -#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - -/* DAC.CH1OFFSETCAL bit masks and bit positions */ -#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - -/* AC - Analog Comparator */ -/* AC.AC0CTRL bit masks and bit positions */ -#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ - -#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ - -#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ - -#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -#define AC_ENABLE_bp 0 /* Enable bit position. */ - -/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE Predefined. */ -/* AC_INTMODE Predefined. */ - -/* AC_INTLVL Predefined. */ -/* AC_INTLVL Predefined. */ - -/* AC_HYSMODE Predefined. */ -/* AC_HYSMODE Predefined. */ - -/* AC_ENABLE Predefined. */ -/* AC_ENABLE Predefined. */ - -/* AC.AC0MUXCTRL bit masks and bit positions */ -#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ - -#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - -/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS Predefined. */ -/* AC_MUXPOS Predefined. */ - -/* AC_MUXNEG Predefined. */ -/* AC_MUXNEG Predefined. */ - -/* AC.CTRLA bit masks and bit positions */ -#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ - -#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ - -#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ - -#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - -/* AC.CTRLB bit masks and bit positions */ -#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - -/* AC.WINCTRL bit masks and bit positions */ -#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ - -#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ - -#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - -/* AC.STATUS bit masks and bit positions */ -#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ - -#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ - -#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ - -#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ - -#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ - -#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - -/* AC.CURRCTRL bit masks and bit positions */ -#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ - -#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ - -#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ - -#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ - -/* AC.CURRCALIB bit masks and bit positions */ -#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ - -/* RTC - Real-Time Clounter */ -/* RTC.CTRL bit masks and bit positions */ -#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ - -#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - -/* RTC.STATUS bit masks and bit positions */ -#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - -/* RTC.INTCTRL bit masks and bit positions */ -#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ - -#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - -/* RTC.INTFLAGS bit masks and bit positions */ -#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ - -#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -/* RTC.CALIB bit masks and bit positions */ -#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ - -#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -#define RTC_ERROR_gp 0 /* Error Value group position. */ -#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ - -/* XCL - XMEGA Custom Logic */ -/* XCL.CTRLA bit masks and bit positions */ -#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ - -#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ - -#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ - -/* XCL.CTRLB bit masks and bit positions */ -#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ - -#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ - -#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ - -#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ - -/* XCL.CTRLC bit masks and bit positions */ -#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ - -#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ - -#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ - -#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ - -#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ - -/* XCL.CTRLD bit masks and bit positions */ -#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ - -#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ - -/* XCL.CTRLE bit masks and bit positions */ -#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ - -#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ - -#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - -/* XCL.CTRLF bit masks and bit positions */ -#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ - -#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ - -#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ - -#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ - -#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ - -#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ - -/* XCL.CTRLG bit masks and bit positions */ -#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ - -#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ - -#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ - -#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ - -/* XCL.INTCTRL bit masks and bit positions */ -#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ - -#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ - -#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ - -#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ - -#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ - -#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ - -#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ - -#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ - -#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ - -#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ - -/* XCL.INTFLAGS bit masks and bit positions */ -#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ - -#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ - -#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ - -#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ - -#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ - -#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ - -#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ - -/* XCL.PLC bit masks and bit positions */ -#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ - -/* XCL.CNTL bit masks and bit positions */ -#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ - -#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ - -#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ - -/* XCL.CNTH bit masks and bit positions */ -#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ - -#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ - -#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ - -#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ - -#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ - -/* XCL.CMPL bit masks and bit positions */ -#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ - -#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ - -/* XCL.CMPH bit masks and bit positions */ -#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ - -#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ - -/* XCL.PERCAPTL bit masks and bit positions */ -#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ - -#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ - -#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ - -#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ - -/* XCL.PERCAPTH bit masks and bit positions */ -#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ - -#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ - -#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ - -#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ - -/* TWI - Two-Wire Interface */ -/* TWI.CTRL bit masks and bit positions */ -#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ - -#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ - -#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ - -#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ - -#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - -#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - -/* TWI_MASTER.CTRLA bit masks and bit positions */ -#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ - -#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ - -#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - -/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ - -#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - -#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ - -#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_MASTER.CTRLC bit masks and bit positions */ -#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - -/* TWI_MASTER.STATUS bit masks and bit positions */ -#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ - -#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ - -#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ - -#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - -/* TWI_SLAVE.CTRLA bit masks and bit positions */ -#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ - -#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ - -#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ - -#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ - -#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ - -#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - -/* TWI_SLAVE.CTRLB bit masks and bit positions */ -#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ - -#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - -#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ - -#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ - -/* TWI_SLAVE.STATUS bit masks and bit positions */ -#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ - -#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ - -#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ - -#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ - -#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ - -#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ - -#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ - -#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - -/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ - -#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - -/* TWI_TIMEOUT.TOS bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ - -#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ - -/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ - -#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ - -#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ - -/* PORT - Port Configuration */ -/* PORT.INTCTRL bit masks and bit positions */ -#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ - -/* PORT.INTFLAGS bit masks and bit positions */ -#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ - -#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ - -#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ - -#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ - -#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ - -#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ - -#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ - -#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ - -/* PORT.REMAP bit masks and bit positions */ -#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -#define PORT_USART0_bp 4 /* Usart0 bit position. */ - -#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ - -#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ - -#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ - -#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ - -/* PORT.PIN0CTRL bit masks and bit positions */ -#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ - -#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ - -#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - -/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_INVEN Predefined. */ -/* PORT_INVEN Predefined. */ - -/* PORT_OPC Predefined. */ -/* PORT_OPC Predefined. */ - -/* PORT_ISC Predefined. */ -/* PORT_ISC Predefined. */ - -/* TC - 16-bit Timer/Counter With PWM */ -/* TC4.CTRLA bit masks and bit positions */ -#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC4.CTRLB bit masks and bit positions */ -#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC4.CTRLC bit masks and bit positions */ -#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ - -#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ - -#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ - -#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ - -#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ - -#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ - -#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ - -#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ - -#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC4.CTRLD bit masks and bit positions */ -#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC4_EVACT_gp 5 /* Event Action group position. */ -#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC4.CTRLE bit masks and bit positions */ -#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ - -#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ - -#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC4.CTRLF bit masks and bit positions */ -#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC4.INTCTRLA bit masks and bit positions */ -#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC4.INTCTRLB bit masks and bit positions */ -#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC4.CTRLGCLR bit masks and bit positions */ -#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC4_CMD_gm 0x0C /* Command group mask. */ -#define TC4_CMD_gp 2 /* Command group position. */ -#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC4_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC4_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC4_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC4.CTRLGSET bit masks and bit positions */ -/* TC4_STOP Predefined. */ -/* TC4_STOP Predefined. */ - -/* TC4_CMD Predefined. */ -/* TC4_CMD Predefined. */ - -/* TC4_LUPD Predefined. */ -/* TC4_LUPD Predefined. */ - -/* TC4_DIR Predefined. */ -/* TC4_DIR Predefined. */ - -/* TC4.CTRLHCLR bit masks and bit positions */ -#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC4.CTRLHSET bit masks and bit positions */ -/* TC4_CCDBV Predefined. */ -/* TC4_CCDBV Predefined. */ - -/* TC4_CCCBV Predefined. */ -/* TC4_CCCBV Predefined. */ - -/* TC4_CCBBV Predefined. */ -/* TC4_CCBBV Predefined. */ - -/* TC4_CCABV Predefined. */ -/* TC4_CCABV Predefined. */ - -/* TC4_PERBV Predefined. */ -/* TC4_PERBV Predefined. */ - -/* TC4_LCCDBV Predefined. */ -/* TC4_LCCDBV Predefined. */ - -/* TC4_LCCCBV Predefined. */ -/* TC4_LCCCBV Predefined. */ - -/* TC4_LCCBBV Predefined. */ -/* TC4_LCCBBV Predefined. */ - -/* TC4_LCCABV Predefined. */ -/* TC4_LCCABV Predefined. */ - -/* TC4_LPERBV Predefined. */ -/* TC4_LPERBV Predefined. */ - -/* TC4.INTFLAGS bit masks and bit positions */ -#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* TC5.CTRLA bit masks and bit positions */ -#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ - -#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ - -#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ - -#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ - -/* TC5.CTRLB bit masks and bit positions */ -#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ - -#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ - -#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ - -/* TC5.CTRLC bit masks and bit positions */ -#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ - -#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ - -#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ - -#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ - -#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ - -#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ - -#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ - -#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ - -/* TC5.CTRLD bit masks and bit positions */ -#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -#define TC5_EVACT_gp 5 /* Event Action group position. */ -#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ - -#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ - -#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - -/* TC5.CTRLE bit masks and bit positions */ -#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ - -#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ - -#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ - -/* TC5.CTRLF bit masks and bit positions */ -#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ - -#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ - -/* TC5.INTCTRLA bit masks and bit positions */ -#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ - -#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ - -#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ - -/* TC5.INTCTRLB bit masks and bit positions */ -#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ - -#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ - -/* TC5.CTRLGCLR bit masks and bit positions */ -#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ - -#define TC5_CMD_gm 0x0C /* Command group mask. */ -#define TC5_CMD_gp 2 /* Command group position. */ -#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -#define TC5_CMD1_bp 3 /* Command bit 1 position. */ - -#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -#define TC5_LUPD_bp 1 /* Lock Update bit position. */ - -#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -#define TC5_DIR_bp 0 /* Counter Direction bit position. */ - -/* TC5.CTRLGSET bit masks and bit positions */ -/* TC5_STOP Predefined. */ -/* TC5_STOP Predefined. */ - -/* TC5_CMD Predefined. */ -/* TC5_CMD Predefined. */ - -/* TC5_LUPD Predefined. */ -/* TC5_LUPD Predefined. */ - -/* TC5_DIR Predefined. */ -/* TC5_DIR Predefined. */ - -/* TC5.CTRLHCLR bit masks and bit positions */ -#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ - -#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ - -#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ - -#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ - -#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ - -#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ - -/* TC5.CTRLHSET bit masks and bit positions */ -/* TC5_CCBBV Predefined. */ -/* TC5_CCBBV Predefined. */ - -/* TC5_CCABV Predefined. */ -/* TC5_CCABV Predefined. */ - -/* TC5_PERBV Predefined. */ -/* TC5_PERBV Predefined. */ - -/* TC5_LCCBBV Predefined. */ -/* TC5_LCCBBV Predefined. */ - -/* TC5_LCCABV Predefined. */ -/* TC5_LCCABV Predefined. */ - -/* TC5_LPERBV Predefined. */ -/* TC5_LPERBV Predefined. */ - -/* TC5.INTFLAGS bit masks and bit positions */ -#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ - -#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ - -#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - -#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ - -#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ - -#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ - -/* FAULT - Fault Extension */ -/* FAULT.CTRLA bit masks and bit positions */ -#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ - -#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ - -#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ - -#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ - -#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ - -#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ - -/* FAULT.CTRLB bit masks and bit positions */ -#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ - -#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ - -#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ - -#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ - -#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ - -/* FAULT.CTRLC bit masks and bit positions */ -#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ - -#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ - -#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ - -#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ - -/* FAULT.CTRLD bit masks and bit positions */ -#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ - -#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ - -#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ - -#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ - -#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ - -/* FAULT.CTRLE bit masks and bit positions */ -#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ - -#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ - -#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ - -#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ - -/* FAULT.STATUS bit masks and bit positions */ -#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ - -#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ - -#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ - -#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ - -#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGCLR bit masks and bit positions */ -#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ - -#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ - -#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ - -#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ - -#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ - -#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ - -/* FAULT.CTRLGSET bit masks and bit positions */ -#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ - -#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ - -#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ - -#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ - -/* WEX - Waveform Extension */ -/* WEX.CTRL bit masks and bit positions */ -#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ - -#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ - -#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ - -#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ - -#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ - -#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ - -/* WEX.STATUSCLR bit masks and bit positions */ -#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ - -#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ - -#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ - -/* WEX.STATUSSET bit masks and bit positions */ -/* WEX_SWAPBUF Predefined. */ -/* WEX_SWAPBUF Predefined. */ - -/* WEX_PGVBUFV Predefined. */ -/* WEX_PGVBUFV Predefined. */ - -/* WEX_PGOBUFV Predefined. */ -/* WEX_PGOBUFV Predefined. */ - -/* WEX.SWAP bit masks and bit positions */ -#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* WEX.SWAPBUF bit masks and bit positions */ -#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ - -#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ - -#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ - -#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ - -/* HIRES - High-Resolution Extension */ -/* HIRES.CTRLA bit masks and bit positions */ -#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ - -#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ - -/* USART - Universal Asynchronous Receiver-Transmitter */ -/* USART.STATUS bit masks and bit positions */ -#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ - -#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ - -#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ - -#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -#define USART_FERR_bp 4 /* Frame Error bit position. */ - -#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ - -#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -#define USART_PERR_bp 2 /* Parity Error bit position. */ - -#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ - -#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - -#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ - -/* USART.CTRLA bit masks and bit positions */ -#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ - -#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ - -#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.CTRLB bit masks and bit positions */ -#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ - -#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ - -#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ - -#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ - -#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ - -#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ - -#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - -/* USART.CTRLC bit masks and bit positions */ -#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -#define USART_CMODE_gp 6 /* Communication Mode group position. */ -#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ - -#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -#define USART_PMODE_gp 4 /* Parity Mode group position. */ -#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ - -#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ - -#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -#define USART_CHSIZE_gp 0 /* Character Size group position. */ -#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - -/* USART.CTRLD bit masks and bit positions */ -#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ - -#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ - -#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - -/* USART.BAUDCTRLA bit masks and bit positions */ -#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - -/* USART.BAUDCTRLB bit masks and bit positions */ -#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL Predefined. */ -/* USART_BSEL Predefined. */ - -/* SPI - Serial Peripheral Interface */ -/* SPI.CTRL bit masks and bit positions */ -#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - -#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ - -#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ - -#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ - -#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -#define SPI_MODE_gp 2 /* SPI Mode group position. */ -#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ - -#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - -/* SPI.INTCTRL bit masks and bit positions */ -#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ - -#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - -/* SPI.STATUS bit masks and bit positions */ -#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ - -#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ - -#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ - -#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ - -/* SPI.CTRLB bit masks and bit positions */ -#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ - -#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ - -/* IRCOM - IR Communication Module */ -/* IRCOM.CTRL bit masks and bit positions */ -#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - -/* FUSE - Fuses and Lockbits */ -/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ - -#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ - -#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ - -#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ - -/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ - -#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ - -/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ - -#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ - -#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ - -/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ - -#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ - -#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ -#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ -#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ -#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ -#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ -#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ -#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ -#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ - -/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ - -#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ - -#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ - - - -// Generic Port Pins - -#define PIN0_bm 0x01 -#define PIN0_bp 0 -#define PIN1_bm 0x02 -#define PIN1_bp 1 -#define PIN2_bm 0x04 -#define PIN2_bp 2 -#define PIN3_bm 0x08 -#define PIN3_bp 3 -#define PIN4_bm 0x10 -#define PIN4_bp 4 -#define PIN5_bm 0x20 -#define PIN5_bp 5 -#define PIN6_bm 0x40 -#define PIN6_bp 6 -#define PIN7_bm 0x80 -#define PIN7_bp 7 - -/* ========== Interrupt Vector Definitions ========== */ -/* Vector 0 is the reset vector */ - -/* OSC interrupt vectors */ -#define OSC_OSCF_vect_num 1 -#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ - -/* PORTR interrupt vectors */ -#define PORTR_INT_vect_num 2 -#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ - -/* EDMA interrupt vectors */ -#define EDMA_CH0_vect_num 3 -#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -#define EDMA_CH1_vect_num 4 -#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -#define EDMA_CH2_vect_num 5 -#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -#define EDMA_CH3_vect_num 6 -#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ - -/* RTC interrupt vectors */ -#define RTC_OVF_vect_num 7 -#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -#define RTC_COMP_vect_num 8 -#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ - -/* PORTC interrupt vectors */ -#define PORTC_INT_vect_num 9 -#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ - -/* TWIC interrupt vectors */ -#define TWIC_TWIS_vect_num 10 -#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -#define TWIC_TWIM_vect_num 11 -#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ - -/* TCC4 interrupt vectors */ -#define TCC4_OVF_vect_num 12 -#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -#define TCC4_ERR_vect_num 13 -#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -#define TCC4_CCA_vect_num 14 -#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -#define TCC4_CCB_vect_num 15 -#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -#define TCC4_CCC_vect_num 16 -#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -#define TCC4_CCD_vect_num 17 -#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ - -/* TCC5 interrupt vectors */ -#define TCC5_OVF_vect_num 18 -#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -#define TCC5_ERR_vect_num 19 -#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -#define TCC5_CCA_vect_num 20 -#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -#define TCC5_CCB_vect_num 21 -#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ - -/* SPIC interrupt vectors */ -#define SPIC_INT_vect_num 22 -#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ - -/* USARTC0 interrupt vectors */ -#define USARTC0_RXC_vect_num 23 -#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -#define USARTC0_DRE_vect_num 24 -#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -#define USARTC0_TXC_vect_num 25 -#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ - -/* NVM interrupt vectors */ -#define NVM_EE_vect_num 26 -#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -#define NVM_SPM_vect_num 27 -#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ - -/* XCL interrupt vectors */ -#define XCL_UNF_vect_num 28 -#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -#define XCL_CC_vect_num 29 -#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ - -/* PORTA interrupt vectors */ -#define PORTA_INT_vect_num 30 -#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ - -/* ACA interrupt vectors */ -#define ACA_AC0_vect_num 31 -#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -#define ACA_AC1_vect_num 32 -#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -#define ACA_ACW_vect_num 33 -#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ - -/* ADCA interrupt vectors */ -#define ADCA_CH0_vect_num 34 -#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ - -/* PORTD interrupt vectors */ -#define PORTD_INT_vect_num 35 -#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ - -/* TCD5 interrupt vectors */ -#define TCD5_OVF_vect_num 36 -#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -#define TCD5_ERR_vect_num 37 -#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -#define TCD5_CCA_vect_num 38 -#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -#define TCD5_CCB_vect_num 39 -#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ - -/* USARTD0 interrupt vectors */ -#define USARTD0_RXC_vect_num 40 -#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -#define USARTD0_DRE_vect_num 41 -#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -#define USARTD0_TXC_vect_num 42 -#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ - -#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (43 * _VECTOR_SIZE) - - -/* ========== Constants ========== */ - -#define PROGMEM_START (0x0000) -#define PROGMEM_SIZE (10240) -#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - -#define APP_SECTION_START (0x0000) -#define APP_SECTION_SIZE (8192) -#define APP_SECTION_PAGE_SIZE (128) -#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - -#define APPTABLE_SECTION_START (0x1800) -#define APPTABLE_SECTION_SIZE (2048) -#define APPTABLE_SECTION_PAGE_SIZE (128) -#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - -#define BOOT_SECTION_START (0x2000) -#define BOOT_SECTION_SIZE (2048) -#define BOOT_SECTION_PAGE_SIZE (128) -#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - -#define DATAMEM_START (0x0000) -#define DATAMEM_SIZE (9216) -#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - -#define IO_START (0x0000) -#define IO_SIZE (4096) -#define IO_PAGE_SIZE (0) -#define IO_END (IO_START + IO_SIZE - 1) - -#define MAPPED_EEPROM_START (0x1000) -#define MAPPED_EEPROM_SIZE (512) -#define MAPPED_EEPROM_PAGE_SIZE (0) -#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) - -#define INTERNAL_SRAM_START (0x2000) -#define INTERNAL_SRAM_SIZE (1024) -#define INTERNAL_SRAM_PAGE_SIZE (0) -#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (512) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - -#define SIGNATURES_START (0x0000) -#define SIGNATURES_SIZE (3) -#define SIGNATURES_PAGE_SIZE (0) -#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -#define FUSES_START (0x0000) -#define FUSES_SIZE (7) -#define FUSES_PAGE_SIZE (0) -#define FUSES_END (FUSES_START + FUSES_SIZE - 1) - -#define LOCKBITS_START (0x0000) -#define LOCKBITS_SIZE (1) -#define LOCKBITS_PAGE_SIZE (0) -#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) - -#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (128) -#define USER_SIGNATURES_PAGE_SIZE (128) -#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - -#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (54) -#define PROD_SIGNATURES_PAGE_SIZE (128) -#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -#define FLASHSTART PROGMEM_START -#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE 128 -#define RAMSTART INTERNAL_SRAM_START -#define RAMSIZE INTERNAL_SRAM_SIZE -#define RAMEND INTERNAL_SRAM_END -#define E2END EEPROM_END -#define E2PAGESIZE EEPROM_PAGE_SIZE - - -/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 7 - -/* Fuse Byte 0 Reserved */ - -/* Fuse Byte 1 */ -#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -#define FUSE1_DEFAULT (0xFF) - -/* Fuse Byte 2 */ -#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -#define FUSE2_DEFAULT (0xFF) - -/* Fuse Byte 3 Reserved */ - -/* Fuse Byte 4 */ -#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -#define FUSE4_DEFAULT (0xFF) - -/* Fuse Byte 5 */ -#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ -#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ -#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -#define FUSE5_DEFAULT (0xFF) - -/* Fuse Byte 6 */ -#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -#define FUSE6_DEFAULT (0xFF) - -/* ========== Lock Bits ========== */ -#define __LOCK_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -#define __BOOT_LOCK_APPLICATION_BITS_EXIST -#define __BOOT_LOCK_BOOT_BITS_EXIST - -/* ========== Signature ========== */ -#define SIGNATURE_0 0x1E -#define SIGNATURE_1 0x93 -#define SIGNATURE_2 0x41 - -/* ========== Power Reduction Condition Definitions ========== */ - -/* PR.PRGEN */ -#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) -#define __AVR_HAVE_PRGEN_XCL -#define __AVR_HAVE_PRGEN_RTC -#define __AVR_HAVE_PRGEN_EVSYS -#define __AVR_HAVE_PRGEN_EDMA - -/* PR.PRPA */ -#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) -#define __AVR_HAVE_PRPA_DAC -#define __AVR_HAVE_PRPA_ADC -#define __AVR_HAVE_PRPA_AC - -/* PR.PRPC */ -#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) -#define __AVR_HAVE_PRPC_TWI -#define __AVR_HAVE_PRPC_USART0 -#define __AVR_HAVE_PRPC_SPI -#define __AVR_HAVE_PRPC_HIRES -#define __AVR_HAVE_PRPC_TC5 -#define __AVR_HAVE_PRPC_TC4 - -/* PR.PRPD */ -#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) -#define __AVR_HAVE_PRPD_USART0 -#define __AVR_HAVE_PRPD_TC5 - - -#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox8e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA8E5_H_INCLUDED +#define _AVR_ATXMEGA8E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (10240) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (8192) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1800) +#define APPTABLE_SECTION_SIZE (2048) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x2000) +#define BOOT_SECTION_SIZE (2048) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (9216) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (512) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (1024) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (512) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ + --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/install-sh +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/install-sh @@ -0,0 +1,508 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2014-09-12.12; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +tab=' ' +nl=' +' +IFS=" $tab$nl" + +# Set DOITPROG to "echo" to test this script. + +doit=${DOITPROG-} +doit_exec=${doit:-exec} + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +is_target_a_directory=possibly + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *"$tab"* | *"$nl"* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) + is_target_a_directory=always + dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) is_target_a_directory=never;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +# We allow the use of options -d and -T together, by making -d +# take the precedence; this is for compatibility with GNU install. + +if test -n "$dir_arg"; then + if test -n "$dst_arg"; then + echo "$0: target directory not allowed when installing a directory." >&2 + exit 1 + fi +fi + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + if test $# -gt 1 || test "$is_target_a_directory" = always; then + if test ! -d "$dst_arg"; then + echo "$0: $dst_arg: Is not a directory." >&2 + exit 1 + fi + fi +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test "$is_target_a_directory" = never; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + dstdir=`dirname "$dst"` + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + # $RANDOM is not portable (e.g. dash); use it when possible to + # lower collision chance + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null; exit $ret' 0 + + # As "mkdir -p" follows symlinks and we work in /tmp possibly; so + # create the $tmpdir first (and fail if unsuccessful) to make sure + # that nobody tries to guess the $tmpdir name. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + oIFS=$IFS + IFS=/ + set -f + set fnord $dstdir + shift + set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + set +f && + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/libc/avr-libc/missing +++ avr-libc-2.0.0+Atmel3.6.1/libc/avr-libc/missing @@ -0,0 +1,215 @@ +#! /bin/sh +# Common wrapper for a few potentially missing GNU programs. + +scriptversion=2013-10-28.13; # UTC + +# Copyright (C) 1996-2014 Free Software Foundation, Inc. +# Originally written by Fran,cois Pinard , 1996. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +if test $# -eq 0; then + echo 1>&2 "Try '$0 --help' for more information" + exit 1 +fi + +case $1 in + + --is-lightweight) + # Used by our autoconf macros to check whether the available missing + # script is modern enough. + exit 0 + ;; + + --run) + # Back-compat with the calling convention used by older automake. + shift + ;; + + -h|--h|--he|--hel|--help) + echo "\ +$0 [OPTION]... PROGRAM [ARGUMENT]... + +Run 'PROGRAM [ARGUMENT]...', returning a proper advice when this fails due +to PROGRAM being missing or too old. + +Options: + -h, --help display this help and exit + -v, --version output version information and exit + +Supported PROGRAM values: + aclocal autoconf autoheader autom4te automake makeinfo + bison yacc flex lex help2man + +Version suffixes to PROGRAM as well as the prefixes 'gnu-', 'gnu', and +'g' are ignored when checking the name. + +Send bug reports to ." + exit $? + ;; + + -v|--v|--ve|--ver|--vers|--versi|--versio|--version) + echo "missing $scriptversion (GNU Automake)" + exit $? + ;; + + -*) + echo 1>&2 "$0: unknown '$1' option" + echo 1>&2 "Try '$0 --help' for more information" + exit 1 + ;; + +esac + +# Run the given program, remember its exit status. +"$@"; st=$? + +# If it succeeded, we are done. +test $st -eq 0 && exit 0 + +# Also exit now if we it failed (or wasn't found), and '--version' was +# passed; such an option is passed most likely to detect whether the +# program is present and works. +case $2 in --version|--help) exit $st;; esac + +# Exit code 63 means version mismatch. This often happens when the user +# tries to use an ancient version of a tool on a file that requires a +# minimum version. +if test $st -eq 63; then + msg="probably too old" +elif test $st -eq 127; then + # Program was missing. + msg="missing on your system" +else + # Program was found and executed, but failed. Give up. + exit $st +fi + +perl_URL=http://www.perl.org/ +flex_URL=http://flex.sourceforge.net/ +gnu_software_URL=http://www.gnu.org/software + +program_details () +{ + case $1 in + aclocal|automake) + echo "The '$1' program is part of the GNU Automake package:" + echo "<$gnu_software_URL/automake>" + echo "It also requires GNU Autoconf, GNU m4 and Perl in order to run:" + echo "<$gnu_software_URL/autoconf>" + echo "<$gnu_software_URL/m4/>" + echo "<$perl_URL>" + ;; + autoconf|autom4te|autoheader) + echo "The '$1' program is part of the GNU Autoconf package:" + echo "<$gnu_software_URL/autoconf/>" + echo "It also requires GNU m4 and Perl in order to run:" + echo "<$gnu_software_URL/m4/>" + echo "<$perl_URL>" + ;; + esac +} + +give_advice () +{ + # Normalize program name to check for. + normalized_program=`echo "$1" | sed ' + s/^gnu-//; t + s/^gnu//; t + s/^g//; t'` + + printf '%s\n' "'$1' is $msg." + + configure_deps="'configure.ac' or m4 files included by 'configure.ac'" + case $normalized_program in + autoconf*) + echo "You should only need it if you modified 'configure.ac'," + echo "or m4 files included by it." + program_details 'autoconf' + ;; + autoheader*) + echo "You should only need it if you modified 'acconfig.h' or" + echo "$configure_deps." + program_details 'autoheader' + ;; + automake*) + echo "You should only need it if you modified 'Makefile.am' or" + echo "$configure_deps." + program_details 'automake' + ;; + aclocal*) + echo "You should only need it if you modified 'acinclude.m4' or" + echo "$configure_deps." + program_details 'aclocal' + ;; + autom4te*) + echo "You might have modified some maintainer files that require" + echo "the 'autom4te' program to be rebuilt." + program_details 'autom4te' + ;; + bison*|yacc*) + echo "You should only need it if you modified a '.y' file." + echo "You may want to install the GNU Bison package:" + echo "<$gnu_software_URL/bison/>" + ;; + lex*|flex*) + echo "You should only need it if you modified a '.l' file." + echo "You may want to install the Fast Lexical Analyzer package:" + echo "<$flex_URL>" + ;; + help2man*) + echo "You should only need it if you modified a dependency" \ + "of a man page." + echo "You may want to install the GNU Help2man package:" + echo "<$gnu_software_URL/help2man/>" + ;; + makeinfo*) + echo "You should only need it if you modified a '.texi' file, or" + echo "any other file indirectly affecting the aspect of the manual." + echo "You might want to install the Texinfo package:" + echo "<$gnu_software_URL/texinfo/>" + echo "The spurious makeinfo call might also be the consequence of" + echo "using a buggy 'make' (AIX, DU, IRIX), in which case you might" + echo "want to install GNU make:" + echo "<$gnu_software_URL/make/>" + ;; + *) + echo "You might have modified some files without having the proper" + echo "tools for further handling them. Check the 'README' file, it" + echo "often tells you about the needed prerequisites for installing" + echo "this package. You may also peek at any GNU archive site, in" + echo "case some other package contains this missing '$1' program." + ;; + esac +} + +give_advice "$1" | sed -e '1s/^/WARNING: /' \ + -e '2,$s/^/ /' >&2 + +# Propagate the correct exit status (expected to be 127 for a program +# not found, 63 for a program that failed due to version mismatch). +exit $st + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: --- avr-libc-2.0.0+Atmel3.6.1.orig/new_upstream.sh +++ avr-libc-2.0.0+Atmel3.6.1/new_upstream.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +if [ $# -ne 1 ]; then + echo Usage: $0 '' + echo Exmpl: $0 2.0.0+Atmel3.5.4 + exit -1 +fi + + +mkdir ../avr-libc-$1".orig" +cp avr8-headers.zip avr-libc.tar.bz2 ../avr-libc-$1".orig" +dch -v "1:"$1"-1" New upstream release +dch -r ok +echo +echo Now update debian/control +echo --- avr-libc-2.0.0+Atmel3.6.1.orig/release.sh +++ avr-libc-2.0.0+Atmel3.6.1/release.sh @@ -0,0 +1,8 @@ +set -x +set -e +sudo cowbuilder update +gbp buildpackage --git-pbuilder +sudo debi +make -B -C /home/hakan/src/avr/nolle07 stampable3.srec +debsign +debrelease